Bug Summary

File:hw/pci.c
Location:line 1957, column 68
Description:Dereference of null pointer

Annotated Source Code

1/*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#include "hw.h"
25#include "pci.h"
26#include "pci_bridge.h"
27#include "pci_internals.h"
28#include "monitor.h"
29#include "net.h"
30#include "sysemu.h"
31#include "loader.h"
32#include "range.h"
33#include "qmp-commands.h"
34#include "msi.h"
35#include "msix.h"
36
37//#define DEBUG_PCI
38#ifdef DEBUG_PCI
39# define PCI_DPRINTF(format, ...)do { } while (0) printf(format, ## __VA_ARGS__)
40#else
41# define PCI_DPRINTF(format, ...)do { } while (0) do { } while (0)
42#endif
43
44static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
45static char *pcibus_get_dev_path(DeviceState *dev);
46static char *pcibus_get_fw_dev_path(DeviceState *dev);
47static int pcibus_reset(BusState *qbus);
48
49static Property pci_props[] = {
50 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1){ .name = ("addr"), .info = &(qdev_prop_pci_devfn), .offset
= __builtin_offsetof(PCIDevice, devfn) + ((int32_t*)0 - (typeof
(((PCIDevice *)0)->devfn)*)0), .qtype = QTYPE_QINT, .defval
= (int32_t)-1, },
51 DEFINE_PROP_STRING("romfile", PCIDevice, romfile){ .name = ("romfile"), .info = &(qdev_prop_string), .offset
= __builtin_offsetof(PCIDevice, romfile) + ((char**)0 - (typeof
(((PCIDevice *)0)->romfile)*)0), },
52 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1){ .name = ("rombar"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(PCIDevice, rom_bar) + ((uint32_t*)0 - (
typeof(((PCIDevice *)0)->rom_bar)*)0), .qtype = QTYPE_QINT
, .defval = (uint32_t)1, },
53 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,{ .name = ("multifunction"), .info = &(qdev_prop_bit), .bitnr
= (3), .offset = __builtin_offsetof(PCIDevice, cap_present) +
((uint32_t*)0 - (typeof(((PCIDevice *)0)->cap_present)*)0
), .qtype = QTYPE_QBOOL, .defval = (_Bool)0, }
54 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false){ .name = ("multifunction"), .info = &(qdev_prop_bit), .bitnr
= (3), .offset = __builtin_offsetof(PCIDevice, cap_present) +
((uint32_t*)0 - (typeof(((PCIDevice *)0)->cap_present)*)0
), .qtype = QTYPE_QBOOL, .defval = (_Bool)0, },
55 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,{ .name = ("command_serr_enable"), .info = &(qdev_prop_bit
), .bitnr = (4), .offset = __builtin_offsetof(PCIDevice, cap_present
) + ((uint32_t*)0 - (typeof(((PCIDevice *)0)->cap_present)
*)0), .qtype = QTYPE_QBOOL, .defval = (_Bool)1, }
56 QEMU_PCI_CAP_SERR_BITNR, true){ .name = ("command_serr_enable"), .info = &(qdev_prop_bit
), .bitnr = (4), .offset = __builtin_offsetof(PCIDevice, cap_present
) + ((uint32_t*)0 - (typeof(((PCIDevice *)0)->cap_present)
*)0), .qtype = QTYPE_QBOOL, .defval = (_Bool)1, },
57 DEFINE_PROP_END_OF_LIST(){}
58};
59
60static void pci_bus_class_init(ObjectClass *klass, void *data)
61{
62 BusClass *k = BUS_CLASS(klass)((BusClass *)object_class_dynamic_cast_assert(((ObjectClass *
)((klass))), ("bus")));
63
64 k->print_dev = pcibus_dev_print;
65 k->get_dev_path = pcibus_get_dev_path;
66 k->get_fw_dev_path = pcibus_get_fw_dev_path;
67 k->reset = pcibus_reset;
68}
69
70static const TypeInfo pci_bus_info = {
71 .name = TYPE_PCI_BUS"PCI",
72 .parent = TYPE_BUS"bus",
73 .instance_size = sizeof(PCIBus),
74 .class_init = pci_bus_class_init,
75};
76
77static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
78static void pci_update_mappings(PCIDevice *d);
79static void pci_set_irq(void *opaque, int irq_num, int level);
80static int pci_add_option_rom(PCIDevice *pdev, bool_Bool is_default_rom);
81static void pci_del_option_rom(PCIDevice *pdev);
82
83static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET0x1af4;
84static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU0x1100;
85
86struct PCIHostBus {
87 int domain;
88 struct PCIBus *bus;
89 QLIST_ENTRY(PCIHostBus)struct { struct PCIHostBus *le_next; struct PCIHostBus **le_prev
; } next;
90};
91static QLIST_HEAD(, PCIHostBus)struct { struct PCIHostBus *lh_first; } host_buses;
92
93static const VMStateDescription vmstate_pcibus = {
94 .name = "PCIBUS",
95 .version_id = 1,
96 .minimum_version_id = 1,
97 .minimum_version_id_old = 1,
98 .fields = (VMStateField []) {
99 VMSTATE_INT32_EQUAL(nirq, PCIBus){ .name = ("nirq"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(int32_t), .info = &(vmstate_info_int32_equal
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(PCIBus,
nirq) + ((int32_t*)0 - (typeof(((PCIBus *)0)->nirq)*)0)),
},
100 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t){ .name = ("irq_count"), .version_id = (0), .num_offset = (__builtin_offsetof
(PCIBus, nirq) + ((int32_t*)0 - (typeof(((PCIBus *)0)->nirq
)*)0)), .info = &(vmstate_info_int32), .size = sizeof(int32_t
), .flags = VMS_VARRAY_INT32|VMS_POINTER, .offset = (__builtin_offsetof
(PCIBus, irq_count) + ((int32_t**)0 - (typeof(((PCIBus *)0)->
irq_count)*)0)), },
101 VMSTATE_END_OF_LIST(){}
102 }
103};
104static int pci_bar(PCIDevice *d, int reg)
105{
106 uint8_t type;
107
108 if (reg != PCI_ROM_SLOT6)
109 return PCI_BASE_ADDRESS_00x10 + reg * 4;
110
111 type = d->config[PCI_HEADER_TYPE0x0e] & ~PCI_HEADER_TYPE_MULTI_FUNCTION0x80;
112 return type == PCI_HEADER_TYPE_BRIDGE1 ? PCI_ROM_ADDRESS10x38 : PCI_ROM_ADDRESS0x30;
113}
114
115static inline int pci_irq_state(PCIDevice *d, int irq_num)
116{
117 return (d->irq_state >> irq_num) & 0x1;
118}
119
120static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
121{
122 d->irq_state &= ~(0x1 << irq_num);
123 d->irq_state |= level << irq_num;
124}
125
126static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
127{
128 PCIBus *bus;
129 for (;;) {
130 bus = pci_dev->bus;
131 irq_num = bus->map_irq(pci_dev, irq_num);
132 if (bus->set_irq)
133 break;
134 pci_dev = bus->parent_dev;
135 }
136 bus->irq_count[irq_num] += change;
137 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
138}
139
140int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
141{
142 assert(irq_num >= 0)((irq_num >= 0) ? (void) (0) : __assert_fail ("irq_num >= 0"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c", 142, __PRETTY_FUNCTION__
));
143 assert(irq_num < bus->nirq)((irq_num < bus->nirq) ? (void) (0) : __assert_fail ("irq_num < bus->nirq"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c", 143, __PRETTY_FUNCTION__
));
144 return !!bus->irq_count[irq_num];
145}
146
147/* Update interrupt status bit in config space on interrupt
148 * state change. */
149static void pci_update_irq_status(PCIDevice *dev)
150{
151 if (dev->irq_state) {
152 dev->config[PCI_STATUS0x06] |= PCI_STATUS_INTERRUPT0x08;
153 } else {
154 dev->config[PCI_STATUS0x06] &= ~PCI_STATUS_INTERRUPT0x08;
155 }
156}
157
158void pci_device_deassert_intx(PCIDevice *dev)
159{
160 int i;
161 for (i = 0; i < PCI_NUM_PINS4; ++i) {
162 qemu_set_irq(dev->irq[i], 0);
163 }
164}
165
166/*
167 * This function is called on #RST and FLR.
168 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
169 */
170void pci_device_reset(PCIDevice *dev)
171{
172 int r;
173
174 qdev_reset_all(&dev->qdev);
175
176 dev->irq_state = 0;
177 pci_update_irq_status(dev);
178 pci_device_deassert_intx(dev);
179 /* Clear all writable bits */
180 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND0x04,
181 pci_get_word(dev->wmask + PCI_COMMAND0x04) |
182 pci_get_word(dev->w1cmask + PCI_COMMAND0x04));
183 pci_word_test_and_clear_mask(dev->config + PCI_STATUS0x06,
184 pci_get_word(dev->wmask + PCI_STATUS0x06) |
185 pci_get_word(dev->w1cmask + PCI_STATUS0x06));
186 dev->config[PCI_CACHE_LINE_SIZE0x0c] = 0x0;
187 dev->config[PCI_INTERRUPT_LINE0x3c] = 0x0;
188 for (r = 0; r < PCI_NUM_REGIONS7; ++r) {
189 PCIIORegion *region = &dev->io_regions[r];
190 if (!region->size) {
191 continue;
192 }
193
194 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO0x01) &&
195 region->type & PCI_BASE_ADDRESS_MEM_TYPE_640x04) {
196 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
197 } else {
198 pci_set_long(dev->config + pci_bar(dev, r), region->type);
199 }
200 }
201 pci_update_mappings(dev);
202
203 msi_reset(dev);
204 msix_reset(dev);
205}
206
207/*
208 * Trigger pci bus reset under a given bus.
209 * To be called on RST# assert.
210 */
211void pci_bus_reset(PCIBus *bus)
212{
213 int i;
214
215 for (i = 0; i < bus->nirq; i++) {
216 bus->irq_count[i] = 0;
217 }
218 for (i = 0; i < ARRAY_SIZE(bus->devices)(sizeof(bus->devices) / sizeof((bus->devices)[0])); ++i) {
219 if (bus->devices[i]) {
220 pci_device_reset(bus->devices[i]);
221 }
222 }
223}
224
225static int pcibus_reset(BusState *qbus)
226{
227 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(PCIBus, qbus)]; ({ const typeof(((PCIBus
*) 0)->qbus) *__mptr = (qbus); (PCIBus *) ((char *) __mptr
- __builtin_offsetof(PCIBus, qbus));});})));
228
229 /* topology traverse is done by pci_bus_reset().
230 Tell qbus/qdev walker not to traverse the tree */
231 return 1;
232}
233
234static void pci_host_bus_register(int domain, PCIBus *bus)
235{
236 struct PCIHostBus *host;
237 host = g_malloc0(sizeof(*host));
238 host->domain = domain;
239 host->bus = bus;
240 QLIST_INSERT_HEAD(&host_buses, host, next)do { if (((host)->next.le_next = (&host_buses)->lh_first
) != ((void*)0)) (&host_buses)->lh_first->next.le_prev
= &(host)->next.le_next; (&host_buses)->lh_first
= (host); (host)->next.le_prev = &(&host_buses)->
lh_first; } while ( 0);
241}
242
243PCIBus *pci_find_root_bus(int domain)
244{
245 struct PCIHostBus *host;
246
247 QLIST_FOREACH(host, &host_buses, next)for ((host) = ((&host_buses)->lh_first); (host); (host
) = ((host)->next.le_next)) {
248 if (host->domain == domain) {
249 return host->bus;
250 }
251 }
252
253 return NULL((void*)0);
254}
255
256int pci_find_domain(const PCIBus *bus)
257{
258 PCIDevice *d;
259 struct PCIHostBus *host;
260
261 /* obtain root bus */
262 while ((d = bus->parent_dev) != NULL((void*)0)) {
263 bus = d->bus;
264 }
265
266 QLIST_FOREACH(host, &host_buses, next)for ((host) = ((&host_buses)->lh_first); (host); (host
) = ((host)->next.le_next)) {
267 if (host->bus == bus) {
268 return host->domain;
269 }
270 }
271
272 abort(); /* should not be reached */
273 return -1;
274}
275
276void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
277 const char *name,
278 MemoryRegion *address_space_mem,
279 MemoryRegion *address_space_io,
280 uint8_t devfn_min)
281{
282 qbus_create_inplace(&bus->qbus, TYPE_PCI_BUS"PCI", parent, name);
283 assert(PCI_FUNC(devfn_min) == 0)((((devfn_min) & 0x07) == 0) ? (void) (0) : __assert_fail
("((devfn_min) & 0x07) == 0", "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c"
, 283, __PRETTY_FUNCTION__));
284 bus->devfn_min = devfn_min;
285 bus->address_space_mem = address_space_mem;
286 bus->address_space_io = address_space_io;
287
288 /* host bridge */
289 QLIST_INIT(&bus->child)do { (&bus->child)->lh_first = ((void*)0); } while (
0);
290 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
291
292 vmstate_register(NULL((void*)0), -1, &vmstate_pcibus, bus);
293}
294
295PCIBus *pci_bus_new(DeviceState *parent, const char *name,
296 MemoryRegion *address_space_mem,
297 MemoryRegion *address_space_io,
298 uint8_t devfn_min)
299{
300 PCIBus *bus;
301
302 bus = g_malloc0(sizeof(*bus));
303 bus->qbus.glib_allocated = true1;
304 pci_bus_new_inplace(bus, parent, name, address_space_mem,
305 address_space_io, devfn_min);
306 return bus;
307}
308
309void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
310 void *irq_opaque, int nirq)
311{
312 bus->set_irq = set_irq;
313 bus->map_irq = map_irq;
314 bus->irq_opaque = irq_opaque;
315 bus->nirq = nirq;
316 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
317}
318
319void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
320{
321 bus->qbus.allow_hotplug = 1;
322 bus->hotplug = hotplug;
323 bus->hotplug_qdev = qdev;
324}
325
326PCIBus *pci_register_bus(DeviceState *parent, const char *name,
327 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
328 void *irq_opaque,
329 MemoryRegion *address_space_mem,
330 MemoryRegion *address_space_io,
331 uint8_t devfn_min, int nirq)
332{
333 PCIBus *bus;
334
335 bus = pci_bus_new(parent, name, address_space_mem,
336 address_space_io, devfn_min);
337 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
338 return bus;
339}
340
341int pci_bus_num(PCIBus *s)
342{
343 if (!s->parent_dev)
344 return 0; /* pci host bridge */
345 return s->parent_dev->config[PCI_SECONDARY_BUS0x19];
346}
347
348static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
349{
350 PCIDevice *s = container_of(pv, PCIDevice, config)({ const typeof(((PCIDevice *) 0)->config) *__mptr = (pv);
(PCIDevice *) ((char *) __mptr - __builtin_offsetof(PCIDevice
, config));});
351 uint8_t *config;
352 int i;
353
354 assert(size == pci_config_size(s))((size == pci_config_size(s)) ? (void) (0) : __assert_fail ("size == pci_config_size(s)"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c", 354, __PRETTY_FUNCTION__
));
355 config = g_malloc(size);
356
357 qemu_get_buffer(f, config, size);
358 for (i = 0; i < size; ++i) {
359 if ((config[i] ^ s->config[i]) &
360 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
361 g_free(config);
362 return -EINVAL22;
363 }
364 }
365 memcpy(s->config, config, size);
366
367 pci_update_mappings(s);
368
369 g_free(config);
370 return 0;
371}
372
373/* just put buffer */
374static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
375{
376 const uint8_t **v = pv;
377 assert(size == pci_config_size(container_of(pv, PCIDevice, config)))((size == pci_config_size(({ const typeof(((PCIDevice *) 0)->
config) *__mptr = (pv); (PCIDevice *) ((char *) __mptr - __builtin_offsetof
(PCIDevice, config));}))) ? (void) (0) : __assert_fail ("size == pci_config_size(({ const typeof(((PCIDevice *) 0)->config) *__mptr = (pv); (PCIDevice *) ((char *) __mptr - __builtin_offsetof(PCIDevice, config));}))"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c", 377, __PRETTY_FUNCTION__
));
378 qemu_put_buffer(f, *v, size);
379}
380
381static VMStateInfo vmstate_info_pci_config = {
382 .name = "pci config",
383 .get = get_pci_config_device,
384 .put = put_pci_config_device,
385};
386
387static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
388{
389 PCIDevice *s = container_of(pv, PCIDevice, irq_state)({ const typeof(((PCIDevice *) 0)->irq_state) *__mptr = (pv
); (PCIDevice *) ((char *) __mptr - __builtin_offsetof(PCIDevice
, irq_state));});
390 uint32_t irq_state[PCI_NUM_PINS4];
391 int i;
392 for (i = 0; i < PCI_NUM_PINS4; ++i) {
393 irq_state[i] = qemu_get_be32(f);
394 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
395 fprintf(stderrstderr, "irq state %d: must be 0 or 1.\n",
396 irq_state[i]);
397 return -EINVAL22;
398 }
399 }
400
401 for (i = 0; i < PCI_NUM_PINS4; ++i) {
402 pci_set_irq_state(s, i, irq_state[i]);
403 }
404
405 return 0;
406}
407
408static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
409{
410 int i;
411 PCIDevice *s = container_of(pv, PCIDevice, irq_state)({ const typeof(((PCIDevice *) 0)->irq_state) *__mptr = (pv
); (PCIDevice *) ((char *) __mptr - __builtin_offsetof(PCIDevice
, irq_state));});
412
413 for (i = 0; i < PCI_NUM_PINS4; ++i) {
414 qemu_put_be32(f, pci_irq_state(s, i));
415 }
416}
417
418static VMStateInfo vmstate_info_pci_irq_state = {
419 .name = "pci irq state",
420 .get = get_pci_irq_state,
421 .put = put_pci_irq_state,
422};
423
424const VMStateDescription vmstate_pci_device = {
425 .name = "PCIDevice",
426 .version_id = 2,
427 .minimum_version_id = 1,
428 .minimum_version_id_old = 1,
429 .fields = (VMStateField []) {
430 VMSTATE_INT32_LE(version_id, PCIDevice){ .name = ("version_id"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(int32_t), .info = &(vmstate_info_int32_le
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(PCIDevice
, version_id) + ((int32_t*)0 - (typeof(((PCIDevice *)0)->version_id
)*)0)), },
431 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,{ .name = ("config"), .version_id = (0), .size = (0x100), .info
= &(vmstate_info_pci_config), .flags = VMS_BUFFER, .offset
= __builtin_offsetof(PCIDevice, config), }
432 vmstate_info_pci_config,{ .name = ("config"), .version_id = (0), .size = (0x100), .info
= &(vmstate_info_pci_config), .flags = VMS_BUFFER, .offset
= __builtin_offsetof(PCIDevice, config), }
433 PCI_CONFIG_SPACE_SIZE){ .name = ("config"), .version_id = (0), .size = (0x100), .info
= &(vmstate_info_pci_config), .flags = VMS_BUFFER, .offset
= __builtin_offsetof(PCIDevice, config), },
434 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,{ .name = ("irq_state"), .version_id = (2), .size = (4 * sizeof
(int32_t)), .info = &(vmstate_info_pci_irq_state), .flags
= VMS_BUFFER, .offset = __builtin_offsetof(PCIDevice, irq_state
), }
435 vmstate_info_pci_irq_state,{ .name = ("irq_state"), .version_id = (2), .size = (4 * sizeof
(int32_t)), .info = &(vmstate_info_pci_irq_state), .flags
= VMS_BUFFER, .offset = __builtin_offsetof(PCIDevice, irq_state
), }
436 PCI_NUM_PINS * sizeof(int32_t)){ .name = ("irq_state"), .version_id = (2), .size = (4 * sizeof
(int32_t)), .info = &(vmstate_info_pci_irq_state), .flags
= VMS_BUFFER, .offset = __builtin_offsetof(PCIDevice, irq_state
), },
437 VMSTATE_END_OF_LIST(){}
438 }
439};
440
441const VMStateDescription vmstate_pcie_device = {
442 .name = "PCIDevice",
443 .version_id = 2,
444 .minimum_version_id = 1,
445 .minimum_version_id_old = 1,
446 .fields = (VMStateField []) {
447 VMSTATE_INT32_LE(version_id, PCIDevice){ .name = ("version_id"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(int32_t), .info = &(vmstate_info_int32_le
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(PCIDevice
, version_id) + ((int32_t*)0 - (typeof(((PCIDevice *)0)->version_id
)*)0)), },
448 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,{ .name = ("config"), .version_id = (0), .size = (0x1000), .info
= &(vmstate_info_pci_config), .flags = VMS_BUFFER, .offset
= __builtin_offsetof(PCIDevice, config), }
449 vmstate_info_pci_config,{ .name = ("config"), .version_id = (0), .size = (0x1000), .info
= &(vmstate_info_pci_config), .flags = VMS_BUFFER, .offset
= __builtin_offsetof(PCIDevice, config), }
450 PCIE_CONFIG_SPACE_SIZE){ .name = ("config"), .version_id = (0), .size = (0x1000), .info
= &(vmstate_info_pci_config), .flags = VMS_BUFFER, .offset
= __builtin_offsetof(PCIDevice, config), },
451 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,{ .name = ("irq_state"), .version_id = (2), .size = (4 * sizeof
(int32_t)), .info = &(vmstate_info_pci_irq_state), .flags
= VMS_BUFFER, .offset = __builtin_offsetof(PCIDevice, irq_state
), }
452 vmstate_info_pci_irq_state,{ .name = ("irq_state"), .version_id = (2), .size = (4 * sizeof
(int32_t)), .info = &(vmstate_info_pci_irq_state), .flags
= VMS_BUFFER, .offset = __builtin_offsetof(PCIDevice, irq_state
), }
453 PCI_NUM_PINS * sizeof(int32_t)){ .name = ("irq_state"), .version_id = (2), .size = (4 * sizeof
(int32_t)), .info = &(vmstate_info_pci_irq_state), .flags
= VMS_BUFFER, .offset = __builtin_offsetof(PCIDevice, irq_state
), },
454 VMSTATE_END_OF_LIST(){}
455 }
456};
457
458static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
459{
460 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
461}
462
463void pci_device_save(PCIDevice *s, QEMUFile *f)
464{
465 /* Clear interrupt status bit: it is implicit
466 * in irq_state which we are saving.
467 * This makes us compatible with old devices
468 * which never set or clear this bit. */
469 s->config[PCI_STATUS0x06] &= ~PCI_STATUS_INTERRUPT0x08;
470 vmstate_save_state(f, pci_get_vmstate(s), s);
471 /* Restore the interrupt status bit. */
472 pci_update_irq_status(s);
473}
474
475int pci_device_load(PCIDevice *s, QEMUFile *f)
476{
477 int ret;
478 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
479 /* Restore the interrupt status bit. */
480 pci_update_irq_status(s);
481 return ret;
482}
483
484static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
485{
486 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID0x2c,
487 pci_default_sub_vendor_id);
488 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID0x2e,
489 pci_default_sub_device_id);
490}
491
492/*
493 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
494 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
495 */
496static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
497 unsigned int *slotp, unsigned int *funcp)
498{
499 const char *p;
500 char *e;
501 unsigned long val;
502 unsigned long dom = 0, bus = 0;
503 unsigned int slot = 0;
504 unsigned int func = 0;
505
506 p = addr;
507 val = strtoul(p, &e, 16);
508 if (e == p)
509 return -1;
510 if (*e == ':') {
511 bus = val;
512 p = e + 1;
513 val = strtoul(p, &e, 16);
514 if (e == p)
515 return -1;
516 if (*e == ':') {
517 dom = bus;
518 bus = val;
519 p = e + 1;
520 val = strtoul(p, &e, 16);
521 if (e == p)
522 return -1;
523 }
524 }
525
526 slot = val;
527
528 if (funcp != NULL((void*)0)) {
529 if (*e != '.')
530 return -1;
531
532 p = e + 1;
533 val = strtoul(p, &e, 16);
534 if (e == p)
535 return -1;
536
537 func = val;
538 }
539
540 /* if funcp == NULL func is 0 */
541 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
542 return -1;
543
544 if (*e)
545 return -1;
546
547 *domp = dom;
548 *busp = bus;
549 *slotp = slot;
550 if (funcp != NULL((void*)0))
551 *funcp = func;
552 return 0;
553}
554
555int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
556 unsigned *slotp)
557{
558 /* strip legacy tag */
559 if (!strncmp(addr, "pci_addr=", 9)) {
560 addr += 9;
561 }
562 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL((void*)0))) {
563 monitor_printf(mon, "Invalid pci address\n");
564 return -1;
565 }
566 return 0;
567}
568
569PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
570{
571 int dom, bus;
572 unsigned slot;
573
574 if (!devaddr) {
575 *devfnp = -1;
576 return pci_find_bus_nr(pci_find_root_bus(0), 0);
577 }
578
579 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL((void*)0)) < 0) {
580 return NULL((void*)0);
581 }
582
583 *devfnp = PCI_DEVFN(slot, 0)((((slot) & 0x1f) << 3) | ((0) & 0x07));
584 return pci_find_bus_nr(pci_find_root_bus(dom), bus);
585}
586
587static void pci_init_cmask(PCIDevice *dev)
588{
589 pci_set_word(dev->cmask + PCI_VENDOR_ID0x00, 0xffff);
590 pci_set_word(dev->cmask + PCI_DEVICE_ID0x02, 0xffff);
591 dev->cmask[PCI_STATUS0x06] = PCI_STATUS_CAP_LIST0x10;
592 dev->cmask[PCI_REVISION_ID0x08] = 0xff;
593 dev->cmask[PCI_CLASS_PROG0x09] = 0xff;
594 pci_set_word(dev->cmask + PCI_CLASS_DEVICE0x0a, 0xffff);
595 dev->cmask[PCI_HEADER_TYPE0x0e] = 0xff;
596 dev->cmask[PCI_CAPABILITY_LIST0x34] = 0xff;
597}
598
599static void pci_init_wmask(PCIDevice *dev)
600{
601 int config_size = pci_config_size(dev);
602
603 dev->wmask[PCI_CACHE_LINE_SIZE0x0c] = 0xff;
604 dev->wmask[PCI_INTERRUPT_LINE0x3c] = 0xff;
605 pci_set_word(dev->wmask + PCI_COMMAND0x04,
606 PCI_COMMAND_IO0x1 | PCI_COMMAND_MEMORY0x2 | PCI_COMMAND_MASTER0x4 |
607 PCI_COMMAND_INTX_DISABLE0x400);
608 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
609 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND0x04, PCI_COMMAND_SERR0x100);
610 }
611
612 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE0x40, 0xff,
613 config_size - PCI_CONFIG_HEADER_SIZE0x40);
614}
615
616static void pci_init_w1cmask(PCIDevice *dev)
617{
618 /*
619 * Note: It's okay to set w1cmask even for readonly bits as
620 * long as their value is hardwired to 0.
621 */
622 pci_set_word(dev->w1cmask + PCI_STATUS0x06,
623 PCI_STATUS_PARITY0x100 | PCI_STATUS_SIG_TARGET_ABORT0x800 |
624 PCI_STATUS_REC_TARGET_ABORT0x1000 | PCI_STATUS_REC_MASTER_ABORT0x2000 |
625 PCI_STATUS_SIG_SYSTEM_ERROR0x4000 | PCI_STATUS_DETECTED_PARITY0x8000);
626}
627
628static void pci_init_mask_bridge(PCIDevice *d)
629{
630 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
631 PCI_SEC_LETENCY_TIMER */
632 memset(d->wmask + PCI_PRIMARY_BUS0x18, 0xff, 4);
633
634 /* base and limit */
635 d->wmask[PCI_IO_BASE0x1c] = PCI_IO_RANGE_MASK(~0x0fUL) & 0xff;
636 d->wmask[PCI_IO_LIMIT0x1d] = PCI_IO_RANGE_MASK(~0x0fUL) & 0xff;
637 pci_set_word(d->wmask + PCI_MEMORY_BASE0x20,
638 PCI_MEMORY_RANGE_MASK(~0x0fUL) & 0xffff);
639 pci_set_word(d->wmask + PCI_MEMORY_LIMIT0x22,
640 PCI_MEMORY_RANGE_MASK(~0x0fUL) & 0xffff);
641 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE0x24,
642 PCI_PREF_RANGE_MASK(~0x0fUL) & 0xffff);
643 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT0x26,
644 PCI_PREF_RANGE_MASK(~0x0fUL) & 0xffff);
645
646 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
647 memset(d->wmask + PCI_PREF_BASE_UPPER320x28, 0xff, 8);
648
649 /* Supported memory and i/o types */
650 d->config[PCI_IO_BASE0x1c] |= PCI_IO_RANGE_TYPE_160x00;
651 d->config[PCI_IO_LIMIT0x1d] |= PCI_IO_RANGE_TYPE_160x00;
652 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE0x24,
653 PCI_PREF_RANGE_TYPE_640x01);
654 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT0x26,
655 PCI_PREF_RANGE_TYPE_640x01);
656
657/* TODO: add this define to pci_regs.h in linux and then in qemu. */
658#define PCI_BRIDGE_CTL_VGA_16BIT0x10 0x10 /* VGA 16-bit decode */
659#define PCI_BRIDGE_CTL_DISCARD0x100 0x100 /* Primary discard timer */
660#define PCI_BRIDGE_CTL_SEC_DISCARD0x200 0x200 /* Secondary discard timer */
661#define PCI_BRIDGE_CTL_DISCARD_STATUS0x400 0x400 /* Discard timer status */
662#define PCI_BRIDGE_CTL_DISCARD_SERR0x800 0x800 /* Discard timer SERR# enable */
663 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL0x3e,
664 PCI_BRIDGE_CTL_PARITY0x01 |
665 PCI_BRIDGE_CTL_SERR0x02 |
666 PCI_BRIDGE_CTL_ISA0x04 |
667 PCI_BRIDGE_CTL_VGA0x08 |
668 PCI_BRIDGE_CTL_VGA_16BIT0x10 |
669 PCI_BRIDGE_CTL_MASTER_ABORT0x20 |
670 PCI_BRIDGE_CTL_BUS_RESET0x40 |
671 PCI_BRIDGE_CTL_FAST_BACK0x80 |
672 PCI_BRIDGE_CTL_DISCARD0x100 |
673 PCI_BRIDGE_CTL_SEC_DISCARD0x200 |
674 PCI_BRIDGE_CTL_DISCARD_SERR0x800);
675 /* Below does not do anything as we never set this bit, put here for
676 * completeness. */
677 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL0x3e,
678 PCI_BRIDGE_CTL_DISCARD_STATUS0x400);
679 d->cmask[PCI_IO_BASE0x1c] |= PCI_IO_RANGE_TYPE_MASK0x0fUL;
680 d->cmask[PCI_IO_LIMIT0x1d] |= PCI_IO_RANGE_TYPE_MASK0x0fUL;
681 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE0x24,
682 PCI_PREF_RANGE_TYPE_MASK0x0fUL);
683 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT0x26,
684 PCI_PREF_RANGE_TYPE_MASK0x0fUL);
685}
686
687static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
688{
689 uint8_t slot = PCI_SLOT(dev->devfn)(((dev->devfn) >> 3) & 0x1f);
690 uint8_t func;
691
692 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
693 dev->config[PCI_HEADER_TYPE0x0e] |= PCI_HEADER_TYPE_MULTI_FUNCTION0x80;
694 }
695
696 /*
697 * multifunction bit is interpreted in two ways as follows.
698 * - all functions must set the bit to 1.
699 * Example: Intel X53
700 * - function 0 must set the bit, but the rest function (> 0)
701 * is allowed to leave the bit to 0.
702 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
703 *
704 * So OS (at least Linux) checks the bit of only function 0,
705 * and doesn't see the bit of function > 0.
706 *
707 * The below check allows both interpretation.
708 */
709 if (PCI_FUNC(dev->devfn)((dev->devfn) & 0x07)) {
710 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)((((slot) & 0x1f) << 3) | ((0) & 0x07))];
711 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
712 /* function 0 should set multifunction bit */
713 error_report("PCI: single function device can't be populated "
714 "in function %x.%x", slot, PCI_FUNC(dev->devfn)((dev->devfn) & 0x07));
715 return -1;
716 }
717 return 0;
718 }
719
720 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
721 return 0;
722 }
723 /* function 0 indicates single function, so function > 0 must be NULL */
724 for (func = 1; func < PCI_FUNC_MAX8; ++func) {
725 if (bus->devices[PCI_DEVFN(slot, func)((((slot) & 0x1f) << 3) | ((func) & 0x07))]) {
726 error_report("PCI: %x.0 indicates single function, "
727 "but %x.%x is already populated.",
728 slot, slot, func);
729 return -1;
730 }
731 }
732 return 0;
733}
734
735static void pci_config_alloc(PCIDevice *pci_dev)
736{
737 int config_size = pci_config_size(pci_dev);
738
739 pci_dev->config = g_malloc0(config_size);
740 pci_dev->cmask = g_malloc0(config_size);
741 pci_dev->wmask = g_malloc0(config_size);
742 pci_dev->w1cmask = g_malloc0(config_size);
743 pci_dev->used = g_malloc0(config_size);
744}
745
746static void pci_config_free(PCIDevice *pci_dev)
747{
748 g_free(pci_dev->config);
749 g_free(pci_dev->cmask);
750 g_free(pci_dev->wmask);
751 g_free(pci_dev->w1cmask);
752 g_free(pci_dev->used);
753}
754
755/* -1 for devfn means auto assign */
756static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
757 const char *name, int devfn)
758{
759 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev)((PCIDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)(object_get_class(((Object *)((pci_dev)))))), ("pci-device"
)));
760 PCIConfigReadFunc *config_read = pc->config_read;
761 PCIConfigWriteFunc *config_write = pc->config_write;
762
763 if (devfn < 0) {
764 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices)(sizeof(bus->devices) / sizeof((bus->devices)[0]));
765 devfn += PCI_FUNC_MAX8) {
766 if (!bus->devices[devfn])
767 goto found;
768 }
769 error_report("PCI: no slot/function available for %s, all in use", name);
770 return NULL((void*)0);
771 found: ;
772 } else if (bus->devices[devfn]) {
773 error_report("PCI: slot %d function %d not available for %s, in use by %s",
774 PCI_SLOT(devfn)(((devfn) >> 3) & 0x1f), PCI_FUNC(devfn)((devfn) & 0x07), name, bus->devices[devfn]->name);
775 return NULL((void*)0);
776 }
777 pci_dev->bus = bus;
778 if (bus->dma_context_fn) {
779 pci_dev->dma = bus->dma_context_fn(bus, bus->dma_context_opaque, devfn);
780 }
781 pci_dev->devfn = devfn;
782 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
783 pci_dev->irq_state = 0;
784 pci_config_alloc(pci_dev);
785
786 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
787 pci_config_set_device_id(pci_dev->config, pc->device_id);
788 pci_config_set_revision(pci_dev->config, pc->revision);
789 pci_config_set_class(pci_dev->config, pc->class_id);
790
791 if (!pc->is_bridge) {
792 if (pc->subsystem_vendor_id || pc->subsystem_id) {
793 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID0x2c,
794 pc->subsystem_vendor_id);
795 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID0x2e,
796 pc->subsystem_id);
797 } else {
798 pci_set_default_subsystem_id(pci_dev);
799 }
800 } else {
801 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
802 assert(!pc->subsystem_vendor_id)((!pc->subsystem_vendor_id) ? (void) (0) : __assert_fail (
"!pc->subsystem_vendor_id", "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c"
, 802, __PRETTY_FUNCTION__));
803 assert(!pc->subsystem_id)((!pc->subsystem_id) ? (void) (0) : __assert_fail ("!pc->subsystem_id"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c", 803, __PRETTY_FUNCTION__
));
804 }
805 pci_init_cmask(pci_dev);
806 pci_init_wmask(pci_dev);
807 pci_init_w1cmask(pci_dev);
808 if (pc->is_bridge) {
809 pci_init_mask_bridge(pci_dev);
810 }
811 if (pci_init_multifunction(bus, pci_dev)) {
812 pci_config_free(pci_dev);
813 return NULL((void*)0);
814 }
815
816 if (!config_read)
817 config_read = pci_default_read_config;
818 if (!config_write)
819 config_write = pci_default_write_config;
820 pci_dev->config_read = config_read;
821 pci_dev->config_write = config_write;
822 bus->devices[devfn] = pci_dev;
823 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS4);
824 pci_dev->version_id = 2; /* Current pci device vmstate version */
825 return pci_dev;
826}
827
828static void do_pci_unregister_device(PCIDevice *pci_dev)
829{
830 qemu_free_irqs(pci_dev->irq);
831 pci_dev->bus->devices[pci_dev->devfn] = NULL((void*)0);
832 pci_config_free(pci_dev);
833}
834
835static void pci_unregister_io_regions(PCIDevice *pci_dev)
836{
837 PCIIORegion *r;
838 int i;
839
840 for(i = 0; i < PCI_NUM_REGIONS7; i++) {
841 r = &pci_dev->io_regions[i];
842 if (!r->size || r->addr == PCI_BAR_UNMAPPED(~(pcibus_t)0))
843 continue;
844 memory_region_del_subregion(r->address_space, r->memory);
845 }
846}
847
848static int pci_unregister_device(DeviceState *dev)
849{
850 PCIDevice *pci_dev = PCI_DEVICE(dev)((PCIDevice *)object_dynamic_cast_assert(((Object *)((dev))),
("pci-device")));
851 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev)((PCIDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)(object_get_class(((Object *)((pci_dev)))))), ("pci-device"
)));
852 int ret = 0;
853
854 if (pc->exit)
855 ret = pc->exit(pci_dev);
856 if (ret)
857 return ret;
858
859 pci_unregister_io_regions(pci_dev);
860 pci_del_option_rom(pci_dev);
861 do_pci_unregister_device(pci_dev);
862 return 0;
863}
864
865void pci_register_bar(PCIDevice *pci_dev, int region_num,
866 uint8_t type, MemoryRegion *memory)
867{
868 PCIIORegion *r;
869 uint32_t addr;
870 uint64_t wmask;
871 pcibus_t size = memory_region_size(memory);
872
873 assert(region_num >= 0)((region_num >= 0) ? (void) (0) : __assert_fail ("region_num >= 0"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c", 873, __PRETTY_FUNCTION__
));
874 assert(region_num < PCI_NUM_REGIONS)((region_num < 7) ? (void) (0) : __assert_fail ("region_num < 7"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c", 874, __PRETTY_FUNCTION__
));
875 if (size & (size-1)) {
876 fprintf(stderrstderr, "ERROR: PCI region size must be pow2 "
877 "type=0x%x, size=0x%"FMT_PCIBUS"l" "x""\n", type, size);
878 exit(1);
879 }
880
881 r = &pci_dev->io_regions[region_num];
882 r->addr = PCI_BAR_UNMAPPED(~(pcibus_t)0);
883 r->size = size;
884 r->type = type;
885 r->memory = NULL((void*)0);
886
887 wmask = ~(size - 1);
888 addr = pci_bar(pci_dev, region_num);
889 if (region_num == PCI_ROM_SLOT6) {
890 /* ROM enable bit is writable */
891 wmask |= PCI_ROM_ADDRESS_ENABLE0x01;
892 }
893 pci_set_long(pci_dev->config + addr, type);
894 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO0x01) &&
895 r->type & PCI_BASE_ADDRESS_MEM_TYPE_640x04) {
896 pci_set_quad(pci_dev->wmask + addr, wmask);
897 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
898 } else {
899 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
900 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
901 }
902 pci_dev->io_regions[region_num].memory = memory;
903 pci_dev->io_regions[region_num].address_space
904 = type & PCI_BASE_ADDRESS_SPACE_IO0x01
905 ? pci_dev->bus->address_space_io
906 : pci_dev->bus->address_space_mem;
907}
908
909pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
910{
911 return pci_dev->io_regions[region_num].addr;
912}
913
914static pcibus_t pci_bar_address(PCIDevice *d,
915 int reg, uint8_t type, pcibus_t size)
916{
917 pcibus_t new_addr, last_addr;
918 int bar = pci_bar(d, reg);
919 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND0x04);
920
921 if (type & PCI_BASE_ADDRESS_SPACE_IO0x01) {
922 if (!(cmd & PCI_COMMAND_IO0x1)) {
923 return PCI_BAR_UNMAPPED(~(pcibus_t)0);
924 }
925 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
926 last_addr = new_addr + size - 1;
927 /* NOTE: we have only 64K ioports on PC */
928 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX(65535)) {
929 return PCI_BAR_UNMAPPED(~(pcibus_t)0);
930 }
931 return new_addr;
932 }
933
934 if (!(cmd & PCI_COMMAND_MEMORY0x2)) {
935 return PCI_BAR_UNMAPPED(~(pcibus_t)0);
936 }
937 if (type & PCI_BASE_ADDRESS_MEM_TYPE_640x04) {
938 new_addr = pci_get_quad(d->config + bar);
939 } else {
940 new_addr = pci_get_long(d->config + bar);
941 }
942 /* the ROM slot has a specific enable bit */
943 if (reg == PCI_ROM_SLOT6 && !(new_addr & PCI_ROM_ADDRESS_ENABLE0x01)) {
944 return PCI_BAR_UNMAPPED(~(pcibus_t)0);
945 }
946 new_addr &= ~(size - 1);
947 last_addr = new_addr + size - 1;
948 /* NOTE: we do not support wrapping */
949 /* XXX: as we cannot support really dynamic
950 mappings, we handle specific values as invalid
951 mappings. */
952 if (last_addr <= new_addr || new_addr == 0 ||
953 last_addr == PCI_BAR_UNMAPPED(~(pcibus_t)0)) {
954 return PCI_BAR_UNMAPPED(~(pcibus_t)0);
955 }
956
957 /* Now pcibus_t is 64bit.
958 * Check if 32 bit BAR wraps around explicitly.
959 * Without this, PC ide doesn't work well.
960 * TODO: remove this work around.
961 */
962 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_640x04) && last_addr >= UINT32_MAX(4294967295U)) {
963 return PCI_BAR_UNMAPPED(~(pcibus_t)0);
964 }
965
966 /*
967 * OS is allowed to set BAR beyond its addressable
968 * bits. For example, 32 bit OS can set 64bit bar
969 * to >4G. Check it. TODO: we might need to support
970 * it in the future for e.g. PAE.
971 */
972 if (last_addr >= TARGET_PHYS_ADDR_MAX(4294967295U)) {
973 return PCI_BAR_UNMAPPED(~(pcibus_t)0);
974 }
975
976 return new_addr;
977}
978
979static void pci_update_mappings(PCIDevice *d)
980{
981 PCIIORegion *r;
982 int i;
983 pcibus_t new_addr;
984
985 for(i = 0; i < PCI_NUM_REGIONS7; i++) {
986 r = &d->io_regions[i];
987
988 /* this region isn't registered */
989 if (!r->size)
990 continue;
991
992 new_addr = pci_bar_address(d, i, r->type, r->size);
993
994 /* This bar isn't changed */
995 if (new_addr == r->addr)
996 continue;
997
998 /* now do the real mapping */
999 if (r->addr != PCI_BAR_UNMAPPED(~(pcibus_t)0)) {
1000 memory_region_del_subregion(r->address_space, r->memory);
1001 }
1002 r->addr = new_addr;
1003 if (r->addr != PCI_BAR_UNMAPPED(~(pcibus_t)0)) {
1004 memory_region_add_subregion_overlap(r->address_space,
1005 r->addr, r->memory, 1);
1006 }
1007 }
1008}
1009
1010static inline int pci_irq_disabled(PCIDevice *d)
1011{
1012 return pci_get_word(d->config + PCI_COMMAND0x04) & PCI_COMMAND_INTX_DISABLE0x400;
1013}
1014
1015/* Called after interrupt disabled field update in config space,
1016 * assert/deassert interrupts if necessary.
1017 * Gets original interrupt disable bit value (before update). */
1018static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1019{
1020 int i, disabled = pci_irq_disabled(d);
1021 if (disabled == was_irq_disabled)
1022 return;
1023 for (i = 0; i < PCI_NUM_PINS4; ++i) {
1024 int state = pci_irq_state(d, i);
1025 pci_change_irq_level(d, i, disabled ? -state : state);
1026 }
1027}
1028
1029uint32_t pci_default_read_config(PCIDevice *d,
1030 uint32_t address, int len)
1031{
1032 uint32_t val = 0;
1033
1034 memcpy(&val, d->config + address, len);
1035 return le32_to_cpu(val);
1036}
1037
1038void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1039{
1040 int i, was_irq_disabled = pci_irq_disabled(d);
1041
1042 for (i = 0; i < l; val >>= 8, ++i) {
1043 uint8_t wmask = d->wmask[addr + i];
1044 uint8_t w1cmask = d->w1cmask[addr + i];
1045 assert(!(wmask & w1cmask))((!(wmask & w1cmask)) ? (void) (0) : __assert_fail ("!(wmask & w1cmask)"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c", 1045, __PRETTY_FUNCTION__
));
1046 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1047 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1048 }
1049 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_00x10, 24) ||
1050 ranges_overlap(addr, l, PCI_ROM_ADDRESS0x30, 4) ||
1051 ranges_overlap(addr, l, PCI_ROM_ADDRESS10x38, 4) ||
1052 range_covers_byte(addr, l, PCI_COMMAND0x04))
1053 pci_update_mappings(d);
1054
1055 if (range_covers_byte(addr, l, PCI_COMMAND0x04))
1056 pci_update_irq_disabled(d, was_irq_disabled);
1057
1058 msi_write_config(d, addr, val, l);
1059 msix_write_config(d, addr, val, l);
1060}
1061
1062/***********************************************************/
1063/* generic PCI irq support */
1064
1065/* 0 <= irq_num <= 3. level must be 0 or 1 */
1066static void pci_set_irq(void *opaque, int irq_num, int level)
1067{
1068 PCIDevice *pci_dev = opaque;
1069 int change;
1070
1071 change = level - pci_irq_state(pci_dev, irq_num);
1072 if (!change)
1073 return;
1074
1075 pci_set_irq_state(pci_dev, irq_num, level);
1076 pci_update_irq_status(pci_dev);
1077 if (pci_irq_disabled(pci_dev))
1078 return;
1079 pci_change_irq_level(pci_dev, irq_num, change);
1080}
1081
1082/***********************************************************/
1083/* monitor info on PCI */
1084
1085typedef struct {
1086 uint16_t class;
1087 const char *desc;
1088 const char *fw_name;
1089 uint16_t fw_ign_bits;
1090} pci_class_desc;
1091
1092static const pci_class_desc pci_class_descriptions[] =
1093{
1094 { 0x0001, "VGA controller", "display"},
1095 { 0x0100, "SCSI controller", "scsi"},
1096 { 0x0101, "IDE controller", "ide"},
1097 { 0x0102, "Floppy controller", "fdc"},
1098 { 0x0103, "IPI controller", "ipi"},
1099 { 0x0104, "RAID controller", "raid"},
1100 { 0x0106, "SATA controller"},
1101 { 0x0107, "SAS controller"},
1102 { 0x0180, "Storage controller"},
1103 { 0x0200, "Ethernet controller", "ethernet"},
1104 { 0x0201, "Token Ring controller", "token-ring"},
1105 { 0x0202, "FDDI controller", "fddi"},
1106 { 0x0203, "ATM controller", "atm"},
1107 { 0x0280, "Network controller"},
1108 { 0x0300, "VGA controller", "display", 0x00ff},
1109 { 0x0301, "XGA controller"},
1110 { 0x0302, "3D controller"},
1111 { 0x0380, "Display controller"},
1112 { 0x0400, "Video controller", "video"},
1113 { 0x0401, "Audio controller", "sound"},
1114 { 0x0402, "Phone"},
1115 { 0x0403, "Audio controller", "sound"},
1116 { 0x0480, "Multimedia controller"},
1117 { 0x0500, "RAM controller", "memory"},
1118 { 0x0501, "Flash controller", "flash"},
1119 { 0x0580, "Memory controller"},
1120 { 0x0600, "Host bridge", "host"},
1121 { 0x0601, "ISA bridge", "isa"},
1122 { 0x0602, "EISA bridge", "eisa"},
1123 { 0x0603, "MC bridge", "mca"},
1124 { 0x0604, "PCI bridge", "pci"},
1125 { 0x0605, "PCMCIA bridge", "pcmcia"},
1126 { 0x0606, "NUBUS bridge", "nubus"},
1127 { 0x0607, "CARDBUS bridge", "cardbus"},
1128 { 0x0608, "RACEWAY bridge"},
1129 { 0x0680, "Bridge"},
1130 { 0x0700, "Serial port", "serial"},
1131 { 0x0701, "Parallel port", "parallel"},
1132 { 0x0800, "Interrupt controller", "interrupt-controller"},
1133 { 0x0801, "DMA controller", "dma-controller"},
1134 { 0x0802, "Timer", "timer"},
1135 { 0x0803, "RTC", "rtc"},
1136 { 0x0900, "Keyboard", "keyboard"},
1137 { 0x0901, "Pen", "pen"},
1138 { 0x0902, "Mouse", "mouse"},
1139 { 0x0A00, "Dock station", "dock", 0x00ff},
1140 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1141 { 0x0c00, "Fireware contorller", "fireware"},
1142 { 0x0c01, "Access bus controller", "access-bus"},
1143 { 0x0c02, "SSA controller", "ssa"},
1144 { 0x0c03, "USB controller", "usb"},
1145 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1146 { 0, NULL((void*)0)}
1147};
1148
1149static void pci_for_each_device_under_bus(PCIBus *bus,
1150 void (*fn)(PCIBus *b, PCIDevice *d,
1151 void *opaque),
1152 void *opaque)
1153{
1154 PCIDevice *d;
1155 int devfn;
1156
1157 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices)(sizeof(bus->devices) / sizeof((bus->devices)[0])); devfn++) {
1158 d = bus->devices[devfn];
1159 if (d) {
1160 fn(bus, d, opaque);
1161 }
1162 }
1163}
1164
1165void pci_for_each_device(PCIBus *bus, int bus_num,
1166 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1167 void *opaque)
1168{
1169 bus = pci_find_bus_nr(bus, bus_num);
1170
1171 if (bus) {
1172 pci_for_each_device_under_bus(bus, fn, opaque);
1173 }
1174}
1175
1176static const pci_class_desc *get_class_desc(int class)
1177{
1178 const pci_class_desc *desc;
1179
1180 desc = pci_class_descriptions;
1181 while (desc->desc && class != desc->class) {
1182 desc++;
1183 }
1184
1185 return desc;
1186}
1187
1188static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1189
1190static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1191{
1192 PciMemoryRegionList *head = NULL((void*)0), *cur_item = NULL((void*)0);
1193 int i;
1194
1195 for (i = 0; i < PCI_NUM_REGIONS7; i++) {
1196 const PCIIORegion *r = &dev->io_regions[i];
1197 PciMemoryRegionList *region;
1198
1199 if (!r->size) {
1200 continue;
1201 }
1202
1203 region = g_malloc0(sizeof(*region));
1204 region->value = g_malloc0(sizeof(*region->value));
1205
1206 if (r->type & PCI_BASE_ADDRESS_SPACE_IO0x01) {
1207 region->value->type = g_strdup("io");
1208 } else {
1209 region->value->type = g_strdup("memory");
1210 region->value->has_prefetch = true1;
1211 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH0x08);
1212 region->value->has_mem_type_64 = true1;
1213 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_640x04);
1214 }
1215
1216 region->value->bar = i;
1217 region->value->address = r->addr;
1218 region->value->size = r->size;
1219
1220 /* XXX: waiting for the qapi to support GSList */
1221 if (!cur_item) {
1222 head = cur_item = region;
1223 } else {
1224 cur_item->next = region;
1225 cur_item = region;
1226 }
1227 }
1228
1229 return head;
1230}
1231
1232static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1233 int bus_num)
1234{
1235 PciBridgeInfo *info;
1236
1237 info = g_malloc0(sizeof(*info));
1238
1239 info->bus.number = dev->config[PCI_PRIMARY_BUS0x18];
1240 info->bus.secondary = dev->config[PCI_SECONDARY_BUS0x19];
1241 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS0x1a];
1242
1243 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
1244 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO0x01);
1245 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO0x01);
1246
1247 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
1248 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY0x00);
1249 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY0x00);
1250
1251 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
1252 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH0x08);
1253 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH0x08);
1254
1255 if (dev->config[PCI_SECONDARY_BUS0x19] != 0) {
1256 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS0x19]);
1257 if (child_bus) {
1258 info->has_devices = true1;
1259 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS0x19]);
1260 }
1261 }
1262
1263 return info;
1264}
1265
1266static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1267 int bus_num)
1268{
1269 const pci_class_desc *desc;
1270 PciDeviceInfo *info;
1271 uint8_t type;
1272 int class;
1273
1274 info = g_malloc0(sizeof(*info));
1275 info->bus = bus_num;
1276 info->slot = PCI_SLOT(dev->devfn)(((dev->devfn) >> 3) & 0x1f);
1277 info->function = PCI_FUNC(dev->devfn)((dev->devfn) & 0x07);
1278
1279 class = pci_get_word(dev->config + PCI_CLASS_DEVICE0x0a);
1280 info->class_info.class = class;
1281 desc = get_class_desc(class);
1282 if (desc->desc) {
1283 info->class_info.has_desc = true1;
1284 info->class_info.desc = g_strdup(desc->desc);
1285 }
1286
1287 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID0x00);
1288 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID0x02);
1289 info->regions = qmp_query_pci_regions(dev);
1290 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1291
1292 if (dev->config[PCI_INTERRUPT_PIN0x3d] != 0) {
1293 info->has_irq = true1;
1294 info->irq = dev->config[PCI_INTERRUPT_LINE0x3c];
1295 }
1296
1297 type = dev->config[PCI_HEADER_TYPE0x0e] & ~PCI_HEADER_TYPE_MULTI_FUNCTION0x80;
1298 if (type == PCI_HEADER_TYPE_BRIDGE1) {
1299 info->has_pci_bridge = true1;
1300 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1301 }
1302
1303 return info;
1304}
1305
1306static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1307{
1308 PciDeviceInfoList *info, *head = NULL((void*)0), *cur_item = NULL((void*)0);
1309 PCIDevice *dev;
1310 int devfn;
1311
1312 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices)(sizeof(bus->devices) / sizeof((bus->devices)[0])); devfn++) {
1313 dev = bus->devices[devfn];
1314 if (dev) {
1315 info = g_malloc0(sizeof(*info));
1316 info->value = qmp_query_pci_device(dev, bus, bus_num);
1317
1318 /* XXX: waiting for the qapi to support GSList */
1319 if (!cur_item) {
1320 head = cur_item = info;
1321 } else {
1322 cur_item->next = info;
1323 cur_item = info;
1324 }
1325 }
1326 }
1327
1328 return head;
1329}
1330
1331static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1332{
1333 PciInfo *info = NULL((void*)0);
1334
1335 bus = pci_find_bus_nr(bus, bus_num);
1336 if (bus) {
1337 info = g_malloc0(sizeof(*info));
1338 info->bus = bus_num;
1339 info->devices = qmp_query_pci_devices(bus, bus_num);
1340 }
1341
1342 return info;
1343}
1344
1345PciInfoList *qmp_query_pci(Error **errp)
1346{
1347 PciInfoList *info, *head = NULL((void*)0), *cur_item = NULL((void*)0);
1348 struct PCIHostBus *host;
1349
1350 QLIST_FOREACH(host, &host_buses, next)for ((host) = ((&host_buses)->lh_first); (host); (host
) = ((host)->next.le_next)) {
1351 info = g_malloc0(sizeof(*info));
1352 info->value = qmp_query_pci_bus(host->bus, 0);
1353
1354 /* XXX: waiting for the qapi to support GSList */
1355 if (!cur_item) {
1356 head = cur_item = info;
1357 } else {
1358 cur_item->next = info;
1359 cur_item = info;
1360 }
1361 }
1362
1363 return head;
1364}
1365
1366static const char * const pci_nic_models[] = {
1367 "ne2k_pci",
1368 "i82551",
1369 "i82557b",
1370 "i82559er",
1371 "rtl8139",
1372 "e1000",
1373 "pcnet",
1374 "virtio",
1375 NULL((void*)0)
1376};
1377
1378static const char * const pci_nic_names[] = {
1379 "ne2k_pci",
1380 "i82551",
1381 "i82557b",
1382 "i82559er",
1383 "rtl8139",
1384 "e1000",
1385 "pcnet",
1386 "virtio-net-pci",
1387 NULL((void*)0)
1388};
1389
1390/* Initialize a PCI NIC. */
1391/* FIXME callers should check for failure, but don't */
1392PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1393 const char *default_devaddr)
1394{
1395 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1396 PCIBus *bus;
1397 int devfn;
1398 PCIDevice *pci_dev;
1399 DeviceState *dev;
1400 int i;
1401
1402 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1403 if (i < 0)
1404 return NULL((void*)0);
1405
1406 bus = pci_get_bus_devfn(&devfn, devaddr);
1407 if (!bus) {
1408 error_report("Invalid PCI device address %s for device %s",
1409 devaddr, pci_nic_names[i]);
1410 return NULL((void*)0);
1411 }
1412
1413 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1414 dev = &pci_dev->qdev;
1415 qdev_set_nic_properties(dev, nd);
1416 if (qdev_init(dev) < 0)
1417 return NULL((void*)0);
1418 return pci_dev;
1419}
1420
1421PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1422 const char *default_devaddr)
1423{
1424 PCIDevice *res;
1425
1426 if (qemu_show_nic_models(nd->model, pci_nic_models))
1427 exit(0);
1428
1429 res = pci_nic_init(nd, default_model, default_devaddr);
1430 if (!res)
1431 exit(1);
1432 return res;
1433}
1434
1435/* Whether a given bus number is in range of the secondary
1436 * bus of the given bridge device. */
1437static bool_Bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1438{
1439 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL0x3e) &
1440 PCI_BRIDGE_CTL_BUS_RESET0x40) /* Don't walk the bus if it's reset. */ &&
1441 dev->config[PCI_SECONDARY_BUS0x19] < bus_num &&
1442 bus_num <= dev->config[PCI_SUBORDINATE_BUS0x1a];
1443}
1444
1445static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1446{
1447 PCIBus *sec;
1448
1449 if (!bus) {
1450 return NULL((void*)0);
1451 }
1452
1453 if (pci_bus_num(bus) == bus_num) {
1454 return bus;
1455 }
1456
1457 /* Consider all bus numbers in range for the host pci bridge. */
1458 if (bus->parent_dev &&
1459 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1460 return NULL((void*)0);
1461 }
1462
1463 /* try child bus */
1464 for (; bus; bus = sec) {
1465 QLIST_FOREACH(sec, &bus->child, sibling)for ((sec) = ((&bus->child)->lh_first); (sec); (sec
) = ((sec)->sibling.le_next)) {
1466 assert(sec->parent_dev)((sec->parent_dev) ? (void) (0) : __assert_fail ("sec->parent_dev"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c", 1466, __PRETTY_FUNCTION__
));
1467 if (sec->parent_dev->config[PCI_SECONDARY_BUS0x19] == bus_num) {
1468 return sec;
1469 }
1470 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1471 break;
1472 }
1473 }
1474 }
1475
1476 return NULL((void*)0);
1477}
1478
1479PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1480{
1481 bus = pci_find_bus_nr(bus, bus_num);
1482
1483 if (!bus)
1484 return NULL((void*)0);
1485
1486 return bus->devices[devfn];
1487}
1488
1489static int pci_qdev_init(DeviceState *qdev)
1490{
1491 PCIDevice *pci_dev = (PCIDevice *)qdev;
1492 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev)((PCIDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)(object_get_class(((Object *)((pci_dev)))))), ("pci-device"
)));
1493 PCIBus *bus;
1494 int rc;
1495 bool_Bool is_default_rom;
1496
1497 /* initialize cap_present for pci_is_express() and pci_config_size() */
1498 if (pc->is_express) {
1499 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1500 }
1501
1502 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev))( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(PCIBus, qbus)]; ({ const typeof(((PCIBus
*) 0)->qbus) *__mptr = (qdev_get_parent_bus(qdev)); (PCIBus
*) ((char *) __mptr - __builtin_offsetof(PCIBus, qbus));});}
));
1503 pci_dev = do_pci_register_device(pci_dev, bus,
1504 object_get_typename(OBJECT(qdev)((Object *)(qdev))),
1505 pci_dev->devfn);
1506 if (pci_dev == NULL((void*)0))
1507 return -1;
1508 if (qdev->hotplugged && pc->no_hotplug) {
1509 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev)))qerror_report_internal("/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c"
, 1509, __func__, "{ 'class': 'DeviceNoHotplug', 'data': { 'device': %s } }"
, object_get_typename(((Object *)(pci_dev))));
1510 do_pci_unregister_device(pci_dev);
1511 return -1;
1512 }
1513 if (pc->init) {
1514 rc = pc->init(pci_dev);
1515 if (rc != 0) {
1516 do_pci_unregister_device(pci_dev);
1517 return rc;
1518 }
1519 }
1520
1521 /* rom loading */
1522 is_default_rom = false0;
1523 if (pci_dev->romfile == NULL((void*)0) && pc->romfile != NULL((void*)0)) {
1524 pci_dev->romfile = g_strdup(pc->romfile);
1525 is_default_rom = true1;
1526 }
1527 pci_add_option_rom(pci_dev, is_default_rom);
1528
1529 if (bus->hotplug) {
1530 /* Let buses differentiate between hotplug and when device is
1531 * enabled during qemu machine creation. */
1532 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1533 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1534 PCI_COLDPLUG_ENABLED);
1535 if (rc != 0) {
1536 int r = pci_unregister_device(&pci_dev->qdev);
1537 assert(!r)((!r) ? (void) (0) : __assert_fail ("!r", "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c"
, 1537, __PRETTY_FUNCTION__));
1538 return rc;
1539 }
1540 }
1541 return 0;
1542}
1543
1544static int pci_unplug_device(DeviceState *qdev)
1545{
1546 PCIDevice *dev = PCI_DEVICE(qdev)((PCIDevice *)object_dynamic_cast_assert(((Object *)((qdev)))
, ("pci-device")));
1547 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev)((PCIDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)(object_get_class(((Object *)((dev)))))), ("pci-device")));
1548
1549 if (pc->no_hotplug) {
1550 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev)))qerror_report_internal("/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c"
, 1550, __func__, "{ 'class': 'DeviceNoHotplug', 'data': { 'device': %s } }"
, object_get_typename(((Object *)(dev))));
1551 return -1;
1552 }
1553 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1554 PCI_HOTPLUG_DISABLED);
1555}
1556
1557PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool_Bool multifunction,
1558 const char *name)
1559{
1560 DeviceState *dev;
1561
1562 dev = qdev_create(&bus->qbus, name);
1563 qdev_prop_set_int32(dev, "addr", devfn);
1564 qdev_prop_set_bit(dev, "multifunction", multifunction);
1565 return PCI_DEVICE(dev)((PCIDevice *)object_dynamic_cast_assert(((Object *)((dev))),
("pci-device")));
1566}
1567
1568PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1569 bool_Bool multifunction,
1570 const char *name)
1571{
1572 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1573 qdev_init_nofail(&dev->qdev);
1574 return dev;
1575}
1576
1577PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1578{
1579 return pci_create_multifunction(bus, devfn, false0, name);
1580}
1581
1582PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1583{
1584 return pci_create_simple_multifunction(bus, devfn, false0, name);
1585}
1586
1587static int pci_find_space(PCIDevice *pdev, uint8_t size)
1588{
1589 int config_size = pci_config_size(pdev);
1590 int offset = PCI_CONFIG_HEADER_SIZE0x40;
1591 int i;
1592 for (i = PCI_CONFIG_HEADER_SIZE0x40; i < config_size; ++i)
1593 if (pdev->used[i])
1594 offset = i + 1;
1595 else if (i - offset + 1 == size)
1596 return offset;
1597 return 0;
1598}
1599
1600static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1601 uint8_t *prev_p)
1602{
1603 uint8_t next, prev;
1604
1605 if (!(pdev->config[PCI_STATUS0x06] & PCI_STATUS_CAP_LIST0x10))
1606 return 0;
1607
1608 for (prev = PCI_CAPABILITY_LIST0x34; (next = pdev->config[prev]);
1609 prev = next + PCI_CAP_LIST_NEXT1)
1610 if (pdev->config[next + PCI_CAP_LIST_ID0] == cap_id)
1611 break;
1612
1613 if (prev_p)
1614 *prev_p = prev;
1615 return next;
1616}
1617
1618static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1619{
1620 uint8_t next, prev, found = 0;
1621
1622 if (!(pdev->used[offset])) {
1623 return 0;
1624 }
1625
1626 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)((pdev->config[0x06] & 0x10) ? (void) (0) : __assert_fail
("pdev->config[0x06] & 0x10", "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c"
, 1626, __PRETTY_FUNCTION__));
1627
1628 for (prev = PCI_CAPABILITY_LIST0x34; (next = pdev->config[prev]);
1629 prev = next + PCI_CAP_LIST_NEXT1) {
1630 if (next <= offset && next > found) {
1631 found = next;
1632 }
1633 }
1634 return found;
1635}
1636
1637/* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1638 This is needed for an option rom which is used for more than one device. */
1639static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1640{
1641 uint16_t vendor_id;
1642 uint16_t device_id;
1643 uint16_t rom_vendor_id;
1644 uint16_t rom_device_id;
1645 uint16_t rom_magic;
1646 uint16_t pcir_offset;
1647 uint8_t checksum;
1648
1649 /* Words in rom data are little endian (like in PCI configuration),
1650 so they can be read / written with pci_get_word / pci_set_word. */
1651
1652 /* Only a valid rom will be patched. */
1653 rom_magic = pci_get_word(ptr);
1654 if (rom_magic != 0xaa55) {
1655 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic)do { } while (0);
1656 return;
1657 }
1658 pcir_offset = pci_get_word(ptr + 0x18);
1659 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1660 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset)do { } while (0);
1661 return;
1662 }
1663
1664 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID0x00);
1665 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID0x02);
1666 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1667 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1668
1669 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,do { } while (0)
1670 vendor_id, device_id, rom_vendor_id, rom_device_id)do { } while (0);
1671
1672 checksum = ptr[6];
1673
1674 if (vendor_id != rom_vendor_id) {
1675 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1676 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1677 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1678 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum)do { } while (0);
1679 ptr[6] = checksum;
1680 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1681 }
1682
1683 if (device_id != rom_device_id) {
1684 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1685 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1686 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1687 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum)do { } while (0);
1688 ptr[6] = checksum;
1689 pci_set_word(ptr + pcir_offset + 6, device_id);
1690 }
1691}
1692
1693/* Add an option rom for the device */
1694static int pci_add_option_rom(PCIDevice *pdev, bool_Bool is_default_rom)
1695{
1696 int size;
1697 char *path;
1698 void *ptr;
1699 char name[32];
1700 const VMStateDescription *vmsd;
1701
1702 if (!pdev->romfile)
1703 return 0;
1704 if (strlen(pdev->romfile) == 0)
1705 return 0;
1706
1707 if (!pdev->rom_bar) {
1708 /*
1709 * Load rom via fw_cfg instead of creating a rom bar,
1710 * for 0.11 compatibility.
1711 */
1712 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE0x0a);
1713 if (class == 0x0300) {
1714 rom_add_vga(pdev->romfile);
1715 } else {
1716 rom_add_option(pdev->romfile, -1);
1717 }
1718 return 0;
1719 }
1720
1721 path = qemu_find_file(QEMU_FILE_TYPE_BIOS0, pdev->romfile);
1722 if (path == NULL((void*)0)) {
1723 path = g_strdup(pdev->romfile);
1724 }
1725
1726 size = get_image_size(path);
1727 if (size < 0) {
1728 error_report("%s: failed to find romfile \"%s\"",
1729 __FUNCTION__, pdev->romfile);
1730 g_free(path);
1731 return -1;
1732 }
1733 if (size & (size - 1)) {
1734 size = 1 << qemu_fls(size);
1735 }
1736
1737 vmsd = qdev_get_vmsd(DEVICE(pdev)((DeviceState *)object_dynamic_cast_assert(((Object *)((pdev)
)), ("device"))));
1738
1739 if (vmsd) {
1740 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
1741 } else {
1742 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)((Object *)(pdev))));
1743 }
1744 pdev->has_rom = true1;
1745 memory_region_init_ram(&pdev->rom, name, size);
1746 vmstate_register_ram(&pdev->rom, &pdev->qdev);
1747 ptr = memory_region_get_ram_ptr(&pdev->rom);
1748 load_image(path, ptr);
1749 g_free(path);
1750
1751 if (is_default_rom) {
1752 /* Only the default rom images will be patched (if needed). */
1753 pci_patch_ids(pdev, ptr, size);
1754 }
1755
1756 qemu_put_ram_ptr(ptr);
1757
1758 pci_register_bar(pdev, PCI_ROM_SLOT6, 0, &pdev->rom);
1759
1760 return 0;
1761}
1762
1763static void pci_del_option_rom(PCIDevice *pdev)
1764{
1765 if (!pdev->has_rom)
1766 return;
1767
1768 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
1769 memory_region_destroy(&pdev->rom);
1770 pdev->has_rom = false0;
1771}
1772
1773/*
1774 * if !offset
1775 * Reserve space and add capability to the linked list in pci config space
1776 *
1777 * if offset = 0,
1778 * Find and reserve space and add capability to the linked list
1779 * in pci config space */
1780int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1781 uint8_t offset, uint8_t size)
1782{
1783 uint8_t *config;
1784 int i, overlapping_cap;
1785
1786 if (!offset) {
1787 offset = pci_find_space(pdev, size);
1788 if (!offset) {
1789 return -ENOSPC28;
1790 }
1791 } else {
1792 /* Verify that capabilities don't overlap. Note: device assignment
1793 * depends on this check to verify that the device is not broken.
1794 * Should never trigger for emulated devices, but it's helpful
1795 * for debugging these. */
1796 for (i = offset; i < offset + size; i++) {
1797 overlapping_cap = pci_find_capability_at_offset(pdev, i);
1798 if (overlapping_cap) {
1799 fprintf(stderrstderr, "ERROR: %04x:%02x:%02x.%x "
1800 "Attempt to add PCI capability %x at offset "
1801 "%x overlaps existing capability %x at offset %x\n",
1802 pci_find_domain(pdev->bus), pci_bus_num(pdev->bus),
1803 PCI_SLOT(pdev->devfn)(((pdev->devfn) >> 3) & 0x1f), PCI_FUNC(pdev->devfn)((pdev->devfn) & 0x07),
1804 cap_id, offset, overlapping_cap, i);
1805 return -EINVAL22;
1806 }
1807 }
1808 }
1809
1810 config = pdev->config + offset;
1811 config[PCI_CAP_LIST_ID0] = cap_id;
1812 config[PCI_CAP_LIST_NEXT1] = pdev->config[PCI_CAPABILITY_LIST0x34];
1813 pdev->config[PCI_CAPABILITY_LIST0x34] = offset;
1814 pdev->config[PCI_STATUS0x06] |= PCI_STATUS_CAP_LIST0x10;
1815 memset(pdev->used + offset, 0xFF, size);
1816 /* Make capability read-only by default */
1817 memset(pdev->wmask + offset, 0, size);
1818 /* Check capability by default */
1819 memset(pdev->cmask + offset, 0xFF, size);
1820 return offset;
1821}
1822
1823/* Unlink capability from the pci config space. */
1824void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1825{
1826 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1827 if (!offset)
1828 return;
1829 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT1];
1830 /* Make capability writable again */
1831 memset(pdev->wmask + offset, 0xff, size);
1832 memset(pdev->w1cmask + offset, 0, size);
1833 /* Clear cmask as device-specific registers can't be checked */
1834 memset(pdev->cmask + offset, 0, size);
1835 memset(pdev->used + offset, 0, size);
1836
1837 if (!pdev->config[PCI_CAPABILITY_LIST0x34])
1838 pdev->config[PCI_STATUS0x06] &= ~PCI_STATUS_CAP_LIST0x10;
1839}
1840
1841uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1842{
1843 return pci_find_capability_list(pdev, cap_id, NULL((void*)0));
1844}
1845
1846static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1847{
1848 PCIDevice *d = (PCIDevice *)dev;
1849 const pci_class_desc *desc;
1850 char ctxt[64];
1851 PCIIORegion *r;
1852 int i, class;
1853
1854 class = pci_get_word(d->config + PCI_CLASS_DEVICE0x0a);
1855 desc = pci_class_descriptions;
1856 while (desc->desc && class != desc->class)
1857 desc++;
1858 if (desc->desc) {
1859 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1860 } else {
1861 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1862 }
1863
1864 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1865 "pci id %04x:%04x (sub %04x:%04x)\n",
1866 indent, "", ctxt, pci_bus_num(d->bus),
1867 PCI_SLOT(d->devfn)(((d->devfn) >> 3) & 0x1f), PCI_FUNC(d->devfn)((d->devfn) & 0x07),
1868 pci_get_word(d->config + PCI_VENDOR_ID0x00),
1869 pci_get_word(d->config + PCI_DEVICE_ID0x02),
1870 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID0x2c),
1871 pci_get_word(d->config + PCI_SUBSYSTEM_ID0x2e));
1872 for (i = 0; i < PCI_NUM_REGIONS7; i++) {
1873 r = &d->io_regions[i];
1874 if (!r->size)
1875 continue;
1876 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS"l" "x"
1877 " [0x%"FMT_PCIBUS"l" "x""]\n",
1878 indent, "",
1879 i, r->type & PCI_BASE_ADDRESS_SPACE_IO0x01 ? "i/o" : "mem",
1880 r->addr, r->addr + r->size - 1);
1881 }
1882}
1883
1884static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
1885{
1886 PCIDevice *d = (PCIDevice *)dev;
1887 const char *name = NULL((void*)0);
1888 const pci_class_desc *desc = pci_class_descriptions;
1889 int class = pci_get_word(d->config + PCI_CLASS_DEVICE0x0a);
1890
1891 while (desc->desc &&
1892 (class & ~desc->fw_ign_bits) !=
1893 (desc->class & ~desc->fw_ign_bits)) {
1894 desc++;
1895 }
1896
1897 if (desc->desc) {
1898 name = desc->fw_name;
1899 }
1900
1901 if (name) {
1902 pstrcpy(buf, len, name);
1903 } else {
1904 snprintf(buf, len, "pci%04x,%04x",
1905 pci_get_word(d->config + PCI_VENDOR_ID0x00),
1906 pci_get_word(d->config + PCI_DEVICE_ID0x02));
1907 }
1908
1909 return buf;
1910}
1911
1912static char *pcibus_get_fw_dev_path(DeviceState *dev)
1913{
1914 PCIDevice *d = (PCIDevice *)dev;
1915 char path[50], name[33];
1916 int off;
1917
1918 off = snprintf(path, sizeof(path), "%s@%x",
1919 pci_dev_fw_name(dev, name, sizeof name),
1920 PCI_SLOT(d->devfn)(((d->devfn) >> 3) & 0x1f));
1921 if (PCI_FUNC(d->devfn)((d->devfn) & 0x07))
1922 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)((d->devfn) & 0x07));
1923 return strdup(path);
1924}
1925
1926static char *pcibus_get_dev_path(DeviceState *dev)
1927{
1928 PCIDevice *d = container_of(dev, PCIDevice, qdev)({ const typeof(((PCIDevice *) 0)->qdev) *__mptr = (dev); (
PCIDevice *) ((char *) __mptr - __builtin_offsetof(PCIDevice,
qdev));});
1929 PCIDevice *t;
1930 int slot_depth;
1931 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
1932 * 00 is added here to make this format compatible with
1933 * domain:Bus:Slot.Func for systems without nested PCI bridges.
1934 * Slot.Function list specifies the slot and function numbers for all
1935 * devices on the path from root to the specific device. */
1936 char domain[] = "DDDD:00";
1937 char slot[] = ":SS.F";
1938 int domain_len = sizeof domain - 1 /* For '\0' */;
1939 int slot_len = sizeof slot - 1 /* For '\0' */;
1940 int path_len;
1941 char *path, *p;
1942 int s;
1943
1944 /* Calculate # of slots on path between device and root. */;
1945 slot_depth = 0;
1946 for (t = d; t; t = t->bus->parent_dev) {
1
Assuming pointer value is null
2
Loop condition is false. Execution continues on line 1950
1947 ++slot_depth;
1948 }
1949
1950 path_len = domain_len + slot_len * slot_depth;
1951
1952 /* Allocate memory, fill in the terminating null byte. */
1953 path = g_malloc(path_len + 1 /* For '\0' */);
1954 path[path_len] = '\0';
1955
1956 /* First field is the domain. */
1957 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
3
Dereference of null pointer
1958 assert(s == domain_len)((s == domain_len) ? (void) (0) : __assert_fail ("s == domain_len"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c", 1958, __PRETTY_FUNCTION__
));
1959 memcpy(path, domain, domain_len);
1960
1961 /* Fill in slot numbers. We walk up from device to root, so need to print
1962 * them in the reverse order, last to first. */
1963 p = path + path_len;
1964 for (t = d; t; t = t->bus->parent_dev) {
1965 p -= slot_len;
1966 s = snprintf(slot, sizeof slot, ":%02x.%x",
1967 PCI_SLOT(t->devfn)(((t->devfn) >> 3) & 0x1f), PCI_FUNC(t->devfn)((t->devfn) & 0x07));
1968 assert(s == slot_len)((s == slot_len) ? (void) (0) : __assert_fail ("s == slot_len"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/pci.c", 1968, __PRETTY_FUNCTION__
));
1969 memcpy(p, slot, slot_len);
1970 }
1971
1972 return path;
1973}
1974
1975static int pci_qdev_find_recursive(PCIBus *bus,
1976 const char *id, PCIDevice **pdev)
1977{
1978 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
1979 if (!qdev) {
1980 return -ENODEV19;
1981 }
1982
1983 /* roughly check if given qdev is pci device */
1984 if (object_dynamic_cast(OBJECT(qdev)((Object *)(qdev)), TYPE_PCI_DEVICE"pci-device")) {
1985 *pdev = PCI_DEVICE(qdev)((PCIDevice *)object_dynamic_cast_assert(((Object *)((qdev)))
, ("pci-device")));
1986 return 0;
1987 }
1988 return -EINVAL22;
1989}
1990
1991int pci_qdev_find_device(const char *id, PCIDevice **pdev)
1992{
1993 struct PCIHostBus *host;
1994 int rc = -ENODEV19;
1995
1996 QLIST_FOREACH(host, &host_buses, next)for ((host) = ((&host_buses)->lh_first); (host); (host
) = ((host)->next.le_next)) {
1997 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
1998 if (!tmp) {
1999 rc = 0;
2000 break;
2001 }
2002 if (tmp != -ENODEV19) {
2003 rc = tmp;
2004 }
2005 }
2006
2007 return rc;
2008}
2009
2010MemoryRegion *pci_address_space(PCIDevice *dev)
2011{
2012 return dev->bus->address_space_mem;
2013}
2014
2015MemoryRegion *pci_address_space_io(PCIDevice *dev)
2016{
2017 return dev->bus->address_space_io;
2018}
2019
2020static void pci_device_class_init(ObjectClass *klass, void *data)
2021{
2022 DeviceClass *k = DEVICE_CLASS(klass)((DeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("device")));
2023 k->init = pci_qdev_init;
2024 k->unplug = pci_unplug_device;
2025 k->exit = pci_unregister_device;
2026 k->bus_type = TYPE_PCI_BUS"PCI";
2027 k->props = pci_props;
2028}
2029
2030void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque)
2031{
2032 bus->dma_context_fn = fn;
2033 bus->dma_context_opaque = opaque;
2034}
2035
2036static TypeInfo pci_device_type_info = {
2037 .name = TYPE_PCI_DEVICE"pci-device",
2038 .parent = TYPE_DEVICE"device",
2039 .instance_size = sizeof(PCIDevice),
2040 .abstract = true1,
2041 .class_size = sizeof(PCIDeviceClass),
2042 .class_init = pci_device_class_init,
2043};
2044
2045static void pci_register_types(void)
2046{
2047 type_register_static(&pci_bus_info);
2048 type_register_static(&pci_device_type_info);
2049}
2050
2051type_init(pci_register_types)static void __attribute__((constructor)) do_qemu_init_pci_register_types
(void) { register_module_init(pci_register_types, MODULE_INIT_QOM
); }