Bug Summary

File:hw/i386/../apic.c
Location:line 530, column 13
Description:Assigned value is garbage or undefined

Annotated Source Code

1/*
2 * APIC support
3 *
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>
18 */
19#include "apic_internal.h"
20#include "apic.h"
21#include "ioapic.h"
22#include "msi.h"
23#include "host-utils.h"
24#include "trace.h"
25#include "pc.h"
26#include "apic-msidef.h"
27
28#define MAX_APIC_WORDS8 8
29
30#define SYNC_FROM_VAPIC0x1 0x1
31#define SYNC_TO_VAPIC0x2 0x2
32#define SYNC_ISR_IRR_TO_VAPIC0x4 0x4
33
34static APICCommonState *local_apics[MAX_APICS255 + 1];
35
36static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode);
37static void apic_update_irq(APICCommonState *s);
38static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
39 uint8_t dest, uint8_t dest_mode);
40
41/* Find first bit starting from msb */
42static int fls_bit(uint32_t value)
43{
44 return 31 - clz32(value);
45}
46
47/* Find first bit starting from lsb */
48static int ffs_bit(uint32_t value)
49{
50 return ctz32(value);
51}
52
53static inline void set_bit(uint32_t *tab, int index)
54{
55 int i, mask;
56 i = index >> 5;
57 mask = 1 << (index & 0x1f);
58 tab[i] |= mask;
59}
60
61static inline void reset_bit(uint32_t *tab, int index)
62{
63 int i, mask;
64 i = index >> 5;
65 mask = 1 << (index & 0x1f);
66 tab[i] &= ~mask;
67}
68
69static inline int get_bit(uint32_t *tab, int index)
70{
71 int i, mask;
72 i = index >> 5;
73 mask = 1 << (index & 0x1f);
74 return !!(tab[i] & mask);
75}
76
77/* return -1 if no bit is set */
78static int get_highest_priority_int(uint32_t *tab)
79{
80 int i;
81 for (i = 7; i >= 0; i--) {
82 if (tab[i] != 0) {
83 return i * 32 + fls_bit(tab[i]);
84 }
85 }
86 return -1;
87}
88
89static void apic_sync_vapic(APICCommonState *s, int sync_type)
90{
91 VAPICState vapic_state;
92 size_t length;
93 off_t start;
94 int vector;
95
96 if (!s->vapic_paddr) {
97 return;
98 }
99 if (sync_type & SYNC_FROM_VAPIC0x1) {
100 cpu_physical_memory_rw(s->vapic_paddr, (void *)&vapic_state,
101 sizeof(vapic_state), 0);
102 s->tpr = vapic_state.tpr;
103 }
104 if (sync_type & (SYNC_TO_VAPIC0x2 | SYNC_ISR_IRR_TO_VAPIC0x4)) {
105 start = offsetof(VAPICState, isr)__builtin_offsetof(VAPICState, isr);
106 length = offsetof(VAPICState, enabled)__builtin_offsetof(VAPICState, enabled) - offsetof(VAPICState, isr)__builtin_offsetof(VAPICState, isr);
107
108 if (sync_type & SYNC_TO_VAPIC0x2) {
109 assert(qemu_cpu_is_self(s->cpu_env))((qemu_cpu_is_self(s->cpu_env)) ? (void) (0) : __assert_fail
("qemu_cpu_is_self(s->cpu_env)", "/home/stefan/src/qemu/qemu.org/qemu/hw/i386/../apic.c"
, 109, __PRETTY_FUNCTION__));
110
111 vapic_state.tpr = s->tpr;
112 vapic_state.enabled = 1;
113 start = 0;
114 length = sizeof(VAPICState);
115 }
116
117 vector = get_highest_priority_int(s->isr);
118 if (vector < 0) {
119 vector = 0;
120 }
121 vapic_state.isr = vector & 0xf0;
122
123 vapic_state.zero = 0;
124
125 vector = get_highest_priority_int(s->irr);
126 if (vector < 0) {
127 vector = 0;
128 }
129 vapic_state.irr = vector & 0xff;
130
131 cpu_physical_memory_write_rom(s->vapic_paddr + start,
132 ((void *)&vapic_state) + start, length);
133 }
134}
135
136static void apic_vapic_base_update(APICCommonState *s)
137{
138 apic_sync_vapic(s, SYNC_TO_VAPIC0x2);
139}
140
141static void apic_local_deliver(APICCommonState *s, int vector)
142{
143 uint32_t lvt = s->lvt[vector];
144 int trigger_mode;
145
146 trace_apic_local_deliver(vector, (lvt >> 8) & 7);
147
148 if (lvt & APIC_LVT_MASKED(1<<16))
149 return;
150
151 switch ((lvt >> 8) & 7) {
152 case APIC_DM_SMI2:
153 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI0x0040);
154 break;
155
156 case APIC_DM_NMI4:
157 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI0x0200);
158 break;
159
160 case APIC_DM_EXTINT7:
161 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD0x0002);
162 break;
163
164 case APIC_DM_FIXED0:
165 trigger_mode = APIC_TRIGGER_EDGE0;
166 if ((vector == APIC_LVT_LINT03 || vector == APIC_LVT_LINT14) &&
167 (lvt & APIC_LVT_LEVEL_TRIGGER(1<<15)))
168 trigger_mode = APIC_TRIGGER_LEVEL1;
169 apic_set_irq(s, lvt & 0xff, trigger_mode);
170 }
171}
172
173void apic_deliver_pic_intr(DeviceState *d, int level)
174{
175 APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(APICCommonState, busdev.qdev)]; ({ const
typeof(((APICCommonState *) 0)->busdev.qdev) *__mptr = (d
); (APICCommonState *) ((char *) __mptr - __builtin_offsetof(
APICCommonState, busdev.qdev));});}));
176
177 if (level) {
178 apic_local_deliver(s, APIC_LVT_LINT03);
179 } else {
180 uint32_t lvt = s->lvt[APIC_LVT_LINT03];
181
182 switch ((lvt >> 8) & 7) {
183 case APIC_DM_FIXED0:
184 if (!(lvt & APIC_LVT_LEVEL_TRIGGER(1<<15)))
185 break;
186 reset_bit(s->irr, lvt & 0xff);
187 /* fall through */
188 case APIC_DM_EXTINT7:
189 cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD0x0002);
190 break;
191 }
192 }
193}
194
195static void apic_external_nmi(APICCommonState *s)
196{
197 apic_local_deliver(s, APIC_LVT_LINT14);
198}
199
200#define foreach_apic(apic, deliver_bitmask, code){ int __i, __j, __mask; for(__i = 0; __i < 8; __i++) { __mask
= deliver_bitmask[__i]; if (__mask) { for(__j = 0; __j < 32
; __j++) { if (__mask & (1 << __j)) { apic = local_apics
[__i * 32 + __j]; if (apic) { code; } } } } }} \
201{\
202 int __i, __j, __mask;\
203 for(__i = 0; __i < MAX_APIC_WORDS8; __i++) {\
204 __mask = deliver_bitmask[__i];\
205 if (__mask) {\
206 for(__j = 0; __j < 32; __j++) {\
207 if (__mask & (1 << __j)) {\
208 apic = local_apics[__i * 32 + __j];\
209 if (apic) {\
210 code;\
211 }\
212 }\
213 }\
214 }\
215 }\
216}
217
218static void apic_bus_deliver(const uint32_t *deliver_bitmask,
219 uint8_t delivery_mode, uint8_t vector_num,
220 uint8_t trigger_mode)
221{
222 APICCommonState *apic_iter;
223
224 switch (delivery_mode) {
225 case APIC_DM_LOWPRI1:
226 /* XXX: search for focus processor, arbitration */
227 {
228 int i, d;
229 d = -1;
230 for(i = 0; i < MAX_APIC_WORDS8; i++) {
231 if (deliver_bitmask[i]) {
232 d = i * 32 + ffs_bit(deliver_bitmask[i]);
233 break;
234 }
235 }
236 if (d >= 0) {
237 apic_iter = local_apics[d];
238 if (apic_iter) {
239 apic_set_irq(apic_iter, vector_num, trigger_mode);
240 }
241 }
242 }
243 return;
244
245 case APIC_DM_FIXED0:
246 break;
247
248 case APIC_DM_SMI2:
249 foreach_apic(apic_iter, deliver_bitmask,{ int __i, __j, __mask; for(__i = 0; __i < 8; __i++) { __mask
= deliver_bitmask[__i]; if (__mask) { for(__j = 0; __j < 32
; __j++) { if (__mask & (1 << __j)) { apic_iter = local_apics
[__i * 32 + __j]; if (apic_iter) { cpu_interrupt(apic_iter->
cpu_env, 0x0040); } } } } }}
250 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ){ int __i, __j, __mask; for(__i = 0; __i < 8; __i++) { __mask
= deliver_bitmask[__i]; if (__mask) { for(__j = 0; __j < 32
; __j++) { if (__mask & (1 << __j)) { apic_iter = local_apics
[__i * 32 + __j]; if (apic_iter) { cpu_interrupt(apic_iter->
cpu_env, 0x0040); } } } } }};
251 return;
252
253 case APIC_DM_NMI4:
254 foreach_apic(apic_iter, deliver_bitmask,{ int __i, __j, __mask; for(__i = 0; __i < 8; __i++) { __mask
= deliver_bitmask[__i]; if (__mask) { for(__j = 0; __j < 32
; __j++) { if (__mask & (1 << __j)) { apic_iter = local_apics
[__i * 32 + __j]; if (apic_iter) { cpu_interrupt(apic_iter->
cpu_env, 0x0200); } } } } }}
255 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ){ int __i, __j, __mask; for(__i = 0; __i < 8; __i++) { __mask
= deliver_bitmask[__i]; if (__mask) { for(__j = 0; __j < 32
; __j++) { if (__mask & (1 << __j)) { apic_iter = local_apics
[__i * 32 + __j]; if (apic_iter) { cpu_interrupt(apic_iter->
cpu_env, 0x0200); } } } } }};
256 return;
257
258 case APIC_DM_INIT5:
259 /* normal INIT IPI sent to processors */
260 foreach_apic(apic_iter, deliver_bitmask,{ int __i, __j, __mask; for(__i = 0; __i < 8; __i++) { __mask
= deliver_bitmask[__i]; if (__mask) { for(__j = 0; __j < 32
; __j++) { if (__mask & (1 << __j)) { apic_iter = local_apics
[__i * 32 + __j]; if (apic_iter) { cpu_interrupt(apic_iter->
cpu_env, 0x0400); } } } } }}
261 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ){ int __i, __j, __mask; for(__i = 0; __i < 8; __i++) { __mask
= deliver_bitmask[__i]; if (__mask) { for(__j = 0; __j < 32
; __j++) { if (__mask & (1 << __j)) { apic_iter = local_apics
[__i * 32 + __j]; if (apic_iter) { cpu_interrupt(apic_iter->
cpu_env, 0x0400); } } } } }};
262 return;
263
264 case APIC_DM_EXTINT7:
265 /* handled in I/O APIC code */
266 break;
267
268 default:
269 return;
270 }
271
272 foreach_apic(apic_iter, deliver_bitmask,{ int __i, __j, __mask; for(__i = 0; __i < 8; __i++) { __mask
= deliver_bitmask[__i]; if (__mask) { for(__j = 0; __j < 32
; __j++) { if (__mask & (1 << __j)) { apic_iter = local_apics
[__i * 32 + __j]; if (apic_iter) { apic_set_irq(apic_iter, vector_num
, trigger_mode); } } } } }}
273 apic_set_irq(apic_iter, vector_num, trigger_mode) ){ int __i, __j, __mask; for(__i = 0; __i < 8; __i++) { __mask
= deliver_bitmask[__i]; if (__mask) { for(__j = 0; __j < 32
; __j++) { if (__mask & (1 << __j)) { apic_iter = local_apics
[__i * 32 + __j]; if (apic_iter) { apic_set_irq(apic_iter, vector_num
, trigger_mode); } } } } }};
274}
275
276void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
277 uint8_t vector_num, uint8_t trigger_mode)
278{
279 uint32_t deliver_bitmask[MAX_APIC_WORDS8];
280
281 trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
282 trigger_mode);
283
284 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
285 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
286}
287
288static void apic_set_base(APICCommonState *s, uint64_t val)
289{
290 s->apicbase = (val & 0xfffff000) |
291 (s->apicbase & (MSR_IA32_APICBASE_BSP(1<<8) | MSR_IA32_APICBASE_ENABLE(1<<11)));
292 /* if disabled, cannot be enabled again */
293 if (!(val & MSR_IA32_APICBASE_ENABLE(1<<11))) {
294 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE(1<<11);
295 cpu_clear_apic_feature(s->cpu_env);
296 s->spurious_vec &= ~APIC_SV_ENABLE(1<<8);
297 }
298}
299
300static void apic_set_tpr(APICCommonState *s, uint8_t val)
301{
302 /* Updates from cr8 are ignored while the VAPIC is active */
303 if (!s->vapic_paddr) {
304 s->tpr = val << 4;
305 apic_update_irq(s);
306 }
307}
308
309static uint8_t apic_get_tpr(APICCommonState *s)
310{
311 apic_sync_vapic(s, SYNC_FROM_VAPIC0x1);
312 return s->tpr >> 4;
313}
314
315static int apic_get_ppr(APICCommonState *s)
316{
317 int tpr, isrv, ppr;
318
319 tpr = (s->tpr >> 4);
320 isrv = get_highest_priority_int(s->isr);
321 if (isrv < 0)
322 isrv = 0;
323 isrv >>= 4;
324 if (tpr >= isrv)
325 ppr = s->tpr;
326 else
327 ppr = isrv << 4;
328 return ppr;
329}
330
331static int apic_get_arb_pri(APICCommonState *s)
332{
333 /* XXX: arbitration */
334 return 0;
335}
336
337
338/*
339 * <0 - low prio interrupt,
340 * 0 - no interrupt,
341 * >0 - interrupt number
342 */
343static int apic_irq_pending(APICCommonState *s)
344{
345 int irrv, ppr;
346 irrv = get_highest_priority_int(s->irr);
347 if (irrv < 0) {
348 return 0;
349 }
350 ppr = apic_get_ppr(s);
351 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
352 return -1;
353 }
354
355 return irrv;
356}
357
358/* signal the CPU if an irq is pending */
359static void apic_update_irq(APICCommonState *s)
360{
361 if (!(s->spurious_vec & APIC_SV_ENABLE(1<<8))) {
362 return;
363 }
364 if (apic_irq_pending(s) > 0) {
365 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD0x0002);
366 } else if (apic_accept_pic_intr(&s->busdev.qdev) &&
367 pic_get_output(isa_pic)) {
368 apic_deliver_pic_intr(&s->busdev.qdev, 1);
369 }
370}
371
372void apic_poll_irq(DeviceState *d)
373{
374 APICCommonState *s = APIC_COMMON(d)((APICCommonState *)object_dynamic_cast_assert(((Object *)((d
))), ("apic-common")));
375
376 apic_sync_vapic(s, SYNC_FROM_VAPIC0x1);
377 apic_update_irq(s);
378}
379
380static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode)
381{
382 apic_report_irq_delivered(!get_bit(s->irr, vector_num));
383
384 set_bit(s->irr, vector_num);
385 if (trigger_mode)
386 set_bit(s->tmr, vector_num);
387 else
388 reset_bit(s->tmr, vector_num);
389 if (s->vapic_paddr) {
390 apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC0x4);
391 /*
392 * The vcpu thread needs to see the new IRR before we pull its current
393 * TPR value. That way, if we miss a lowering of the TRP, the guest
394 * has the chance to notice the new IRR and poll for IRQs on its own.
395 */
396 smp_wmb()asm volatile("" ::: "memory");
397 apic_sync_vapic(s, SYNC_FROM_VAPIC0x1);
398 }
399 apic_update_irq(s);
400}
401
402static void apic_eoi(APICCommonState *s)
403{
404 int isrv;
405 isrv = get_highest_priority_int(s->isr);
406 if (isrv < 0)
407 return;
408 reset_bit(s->isr, isrv);
409 if (!(s->spurious_vec & APIC_SV_DIRECTED_IO(1<<12)) && get_bit(s->tmr, isrv)) {
410 ioapic_eoi_broadcast(isrv);
411 }
412 apic_sync_vapic(s, SYNC_FROM_VAPIC0x1 | SYNC_TO_VAPIC0x2);
413 apic_update_irq(s);
414}
415
416static int apic_find_dest(uint8_t dest)
417{
418 APICCommonState *apic = local_apics[dest];
419 int i;
420
421 if (apic && apic->id == dest)
422 return dest; /* shortcut in case apic->id == apic->idx */
423
424 for (i = 0; i < MAX_APICS255; i++) {
425 apic = local_apics[i];
426 if (apic && apic->id == dest)
427 return i;
428 if (!apic)
429 break;
430 }
431
432 return -1;
433}
434
435static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
436 uint8_t dest, uint8_t dest_mode)
437{
438 APICCommonState *apic_iter;
439 int i;
440
441 if (dest_mode == 0) {
442 if (dest == 0xff) {
443 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS8 * sizeof(uint32_t));
444 } else {
445 int idx = apic_find_dest(dest);
446 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS8 * sizeof(uint32_t));
447 if (idx >= 0)
448 set_bit(deliver_bitmask, idx);
449 }
450 } else {
451 /* XXX: cluster mode */
452 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS8 * sizeof(uint32_t));
453 for(i = 0; i < MAX_APICS255; i++) {
454 apic_iter = local_apics[i];
455 if (apic_iter) {
456 if (apic_iter->dest_mode == 0xf) {
457 if (dest & apic_iter->log_dest)
458 set_bit(deliver_bitmask, i);
459 } else if (apic_iter->dest_mode == 0x0) {
460 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
461 (dest & apic_iter->log_dest & 0x0f)) {
462 set_bit(deliver_bitmask, i);
463 }
464 }
465 } else {
466 break;
467 }
468 }
469 }
470}
471
472static void apic_startup(APICCommonState *s, int vector_num)
473{
474 s->sipi_vector = vector_num;
475 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI0x0800);
476}
477
478void apic_sipi(DeviceState *d)
479{
480 APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(APICCommonState, busdev.qdev)]; ({ const
typeof(((APICCommonState *) 0)->busdev.qdev) *__mptr = (d
); (APICCommonState *) ((char *) __mptr - __builtin_offsetof(
APICCommonState, busdev.qdev));});}));
481
482 cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI0x0800);
483
484 if (!s->wait_for_sipi)
485 return;
486 cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
487 s->wait_for_sipi = 0;
488}
489
490static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
491 uint8_t delivery_mode, uint8_t vector_num,
492 uint8_t trigger_mode)
493{
494 APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(APICCommonState, busdev.qdev)]; ({ const
typeof(((APICCommonState *) 0)->busdev.qdev) *__mptr = (d
); (APICCommonState *) ((char *) __mptr - __builtin_offsetof(
APICCommonState, busdev.qdev));});}));
495 uint32_t deliver_bitmask[MAX_APIC_WORDS8];
496 int dest_shorthand = (s->icr[0] >> 18) & 3;
497 APICCommonState *apic_iter;
498
499 switch (dest_shorthand) {
1
'Default' branch taken. Execution continues on line 516
500 case 0:
501 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
502 break;
503 case 1:
504 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
505 set_bit(deliver_bitmask, s->idx);
506 break;
507 case 2:
508 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
509 break;
510 case 3:
511 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
512 reset_bit(deliver_bitmask, s->idx);
513 break;
514 }
515
516 switch (delivery_mode) {
2
Control jumps to 'case 6:' at line 529
517 case APIC_DM_INIT5:
518 {
519 int trig_mode = (s->icr[0] >> 15) & 1;
520 int level = (s->icr[0] >> 14) & 1;
521 if (level == 0 && trig_mode == 1) {
522 foreach_apic(apic_iter, deliver_bitmask,{ int __i, __j, __mask; for(__i = 0; __i < 8; __i++) { __mask
= deliver_bitmask[__i]; if (__mask) { for(__j = 0; __j < 32
; __j++) { if (__mask & (1 << __j)) { apic_iter = local_apics
[__i * 32 + __j]; if (apic_iter) { apic_iter->arb_id = apic_iter
->id; } } } } }}
523 apic_iter->arb_id = apic_iter->id ){ int __i, __j, __mask; for(__i = 0; __i < 8; __i++) { __mask
= deliver_bitmask[__i]; if (__mask) { for(__j = 0; __j < 32
; __j++) { if (__mask & (1 << __j)) { apic_iter = local_apics
[__i * 32 + __j]; if (apic_iter) { apic_iter->arb_id = apic_iter
->id; } } } } }};
524 return;
525 }
526 }
527 break;
528
529 case APIC_DM_SIPI6:
530 foreach_apic(apic_iter, deliver_bitmask,{ int __i, __j, __mask; for(__i = 0; __i < 8; __i++) { __mask
= deliver_bitmask[__i]; if (__mask) { for(__j = 0; __j < 32
; __j++) { if (__mask & (1 << __j)) { apic_iter = local_apics
[__i * 32 + __j]; if (apic_iter) { apic_startup(apic_iter, vector_num
); } } } } }}
3
Within the expansion of the macro 'foreach_apic':
a
Assigned value is garbage or undefined
531 apic_startup(apic_iter, vector_num) ){ int __i, __j, __mask; for(__i = 0; __i < 8; __i++) { __mask
= deliver_bitmask[__i]; if (__mask) { for(__j = 0; __j < 32
; __j++) { if (__mask & (1 << __j)) { apic_iter = local_apics
[__i * 32 + __j]; if (apic_iter) { apic_startup(apic_iter, vector_num
); } } } } }};
532 return;
533 }
534
535 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
536}
537
538int apic_get_interrupt(DeviceState *d)
539{
540 APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(APICCommonState, busdev.qdev)]; ({ const
typeof(((APICCommonState *) 0)->busdev.qdev) *__mptr = (d
); (APICCommonState *) ((char *) __mptr - __builtin_offsetof(
APICCommonState, busdev.qdev));});}));
541 int intno;
542
543 /* if the APIC is installed or enabled, we let the 8259 handle the
544 IRQs */
545 if (!s)
546 return -1;
547 if (!(s->spurious_vec & APIC_SV_ENABLE(1<<8)))
548 return -1;
549
550 apic_sync_vapic(s, SYNC_FROM_VAPIC0x1);
551 intno = apic_irq_pending(s);
552
553 if (intno == 0) {
554 apic_sync_vapic(s, SYNC_TO_VAPIC0x2);
555 return -1;
556 } else if (intno < 0) {
557 apic_sync_vapic(s, SYNC_TO_VAPIC0x2);
558 return s->spurious_vec & 0xff;
559 }
560 reset_bit(s->irr, intno);
561 set_bit(s->isr, intno);
562 apic_sync_vapic(s, SYNC_TO_VAPIC0x2);
563 apic_update_irq(s);
564 return intno;
565}
566
567int apic_accept_pic_intr(DeviceState *d)
568{
569 APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(APICCommonState, busdev.qdev)]; ({ const
typeof(((APICCommonState *) 0)->busdev.qdev) *__mptr = (d
); (APICCommonState *) ((char *) __mptr - __builtin_offsetof(
APICCommonState, busdev.qdev));});}));
570 uint32_t lvt0;
571
572 if (!s)
573 return -1;
574
575 lvt0 = s->lvt[APIC_LVT_LINT03];
576
577 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE(1<<11)) == 0 ||
578 (lvt0 & APIC_LVT_MASKED(1<<16)) == 0)
579 return 1;
580
581 return 0;
582}
583
584static uint32_t apic_get_current_count(APICCommonState *s)
585{
586 int64_t d;
587 uint32_t val;
588 d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >>
589 s->count_shift;
590 if (s->lvt[APIC_LVT_TIMER0] & APIC_LVT_TIMER_PERIODIC(1<<17)) {
591 /* periodic */
592 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
593 } else {
594 if (d >= s->initial_count)
595 val = 0;
596 else
597 val = s->initial_count - d;
598 }
599 return val;
600}
601
602static void apic_timer_update(APICCommonState *s, int64_t current_time)
603{
604 if (apic_next_timer(s, current_time)) {
605 qemu_mod_timer(s->timer, s->next_time);
606 } else {
607 qemu_del_timer(s->timer);
608 }
609}
610
611static void apic_timer(void *opaque)
612{
613 APICCommonState *s = opaque;
614
615 apic_local_deliver(s, APIC_LVT_TIMER0);
616 apic_timer_update(s, s->next_time);
617}
618
619static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
620{
621 return 0;
622}
623
624static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
625{
626 return 0;
627}
628
629static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
630{
631}
632
633static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
634{
635}
636
637static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
638{
639 DeviceState *d;
640 APICCommonState *s;
641 uint32_t val;
642 int index;
643
644 d = cpu_get_current_apic();
645 if (!d) {
646 return 0;
647 }
648 s = DO_UPCAST(APICCommonState, busdev.qdev, d)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(APICCommonState, busdev.qdev)]; ({ const
typeof(((APICCommonState *) 0)->busdev.qdev) *__mptr = (d
); (APICCommonState *) ((char *) __mptr - __builtin_offsetof(
APICCommonState, busdev.qdev));});}));
649
650 index = (addr >> 4) & 0xff;
651 switch(index) {
652 case 0x02: /* id */
653 val = s->id << 24;
654 break;
655 case 0x03: /* version */
656 val = 0x11 | ((APIC_LVT_NB6 - 1) << 16); /* version 0x11 */
657 break;
658 case 0x08:
659 apic_sync_vapic(s, SYNC_FROM_VAPIC0x1);
660 if (apic_report_tpr_access) {
661 cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_READ);
662 }
663 val = s->tpr;
664 break;
665 case 0x09:
666 val = apic_get_arb_pri(s);
667 break;
668 case 0x0a:
669 /* ppr */
670 val = apic_get_ppr(s);
671 break;
672 case 0x0b:
673 val = 0;
674 break;
675 case 0x0d:
676 val = s->log_dest << 24;
677 break;
678 case 0x0e:
679 val = s->dest_mode << 28;
680 break;
681 case 0x0f:
682 val = s->spurious_vec;
683 break;
684 case 0x10 ... 0x17:
685 val = s->isr[index & 7];
686 break;
687 case 0x18 ... 0x1f:
688 val = s->tmr[index & 7];
689 break;
690 case 0x20 ... 0x27:
691 val = s->irr[index & 7];
692 break;
693 case 0x28:
694 val = s->esr;
695 break;
696 case 0x30:
697 case 0x31:
698 val = s->icr[index & 1];
699 break;
700 case 0x32 ... 0x37:
701 val = s->lvt[index - 0x32];
702 break;
703 case 0x38:
704 val = s->initial_count;
705 break;
706 case 0x39:
707 val = apic_get_current_count(s);
708 break;
709 case 0x3e:
710 val = s->divide_conf;
711 break;
712 default:
713 s->esr |= ESR_ILLEGAL_ADDRESS(1 << 7);
714 val = 0;
715 break;
716 }
717 trace_apic_mem_readl(addr, val);
718 return val;
719}
720
721static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
722{
723 uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK0x00ffff0) >> MSI_ADDR_DEST_ID_SHIFT12;
724 uint8_t vector = (data & MSI_DATA_VECTOR_MASK0x000000ff) >> MSI_DATA_VECTOR_SHIFT0;
725 uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT2) & 0x1;
726 uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT15) & 0x1;
727 uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT8) & 0x7;
728 /* XXX: Ignore redirection hint. */
729 apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
730}
731
732static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
733{
734 DeviceState *d;
735 APICCommonState *s;
736 int index = (addr >> 4) & 0xff;
737 if (addr > 0xfff || !index) {
738 /* MSI and MMIO APIC are at the same memory location,
739 * but actually not on the global bus: MSI is on PCI bus
740 * APIC is connected directly to the CPU.
741 * Mapping them on the global bus happens to work because
742 * MSI registers are reserved in APIC MMIO and vice versa. */
743 apic_send_msi(addr, val);
744 return;
745 }
746
747 d = cpu_get_current_apic();
748 if (!d) {
749 return;
750 }
751 s = DO_UPCAST(APICCommonState, busdev.qdev, d)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(APICCommonState, busdev.qdev)]; ({ const
typeof(((APICCommonState *) 0)->busdev.qdev) *__mptr = (d
); (APICCommonState *) ((char *) __mptr - __builtin_offsetof(
APICCommonState, busdev.qdev));});}));
752
753 trace_apic_mem_writel(addr, val);
754
755 switch(index) {
756 case 0x02:
757 s->id = (val >> 24);
758 break;
759 case 0x03:
760 break;
761 case 0x08:
762 if (apic_report_tpr_access) {
763 cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_WRITE);
764 }
765 s->tpr = val;
766 apic_sync_vapic(s, SYNC_TO_VAPIC0x2);
767 apic_update_irq(s);
768 break;
769 case 0x09:
770 case 0x0a:
771 break;
772 case 0x0b: /* EOI */
773 apic_eoi(s);
774 break;
775 case 0x0d:
776 s->log_dest = val >> 24;
777 break;
778 case 0x0e:
779 s->dest_mode = val >> 28;
780 break;
781 case 0x0f:
782 s->spurious_vec = val & 0x1ff;
783 apic_update_irq(s);
784 break;
785 case 0x10 ... 0x17:
786 case 0x18 ... 0x1f:
787 case 0x20 ... 0x27:
788 case 0x28:
789 break;
790 case 0x30:
791 s->icr[0] = val;
792 apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
793 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
794 (s->icr[0] >> 15) & 1);
795 break;
796 case 0x31:
797 s->icr[1] = val;
798 break;
799 case 0x32 ... 0x37:
800 {
801 int n = index - 0x32;
802 s->lvt[n] = val;
803 if (n == APIC_LVT_TIMER0)
804 apic_timer_update(s, qemu_get_clock_ns(vm_clock));
805 }
806 break;
807 case 0x38:
808 s->initial_count = val;
809 s->initial_count_load_time = qemu_get_clock_ns(vm_clock);
810 apic_timer_update(s, s->initial_count_load_time);
811 break;
812 case 0x39:
813 break;
814 case 0x3e:
815 {
816 int v;
817 s->divide_conf = val & 0xb;
818 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
819 s->count_shift = (v + 1) & 7;
820 }
821 break;
822 default:
823 s->esr |= ESR_ILLEGAL_ADDRESS(1 << 7);
824 break;
825 }
826}
827
828static void apic_pre_save(APICCommonState *s)
829{
830 apic_sync_vapic(s, SYNC_FROM_VAPIC0x1);
831}
832
833static void apic_post_load(APICCommonState *s)
834{
835 if (s->timer_expiry != -1) {
836 qemu_mod_timer(s->timer, s->timer_expiry);
837 } else {
838 qemu_del_timer(s->timer);
839 }
840}
841
842static const MemoryRegionOps apic_io_ops = {
843 .old_mmio = {
844 .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
845 .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
846 },
847 .endianness = DEVICE_NATIVE_ENDIAN,
848};
849
850static void apic_init(APICCommonState *s)
851{
852 memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic-msi",
853 MSI_SPACE_SIZE0x100000);
854
855 s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
856 local_apics[s->idx] = s;
857
858 msi_supported = true1;
859}
860
861static void apic_class_init(ObjectClass *klass, void *data)
862{
863 APICCommonClass *k = APIC_COMMON_CLASS(klass)((APICCommonClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("apic-common")));
864
865 k->init = apic_init;
866 k->set_base = apic_set_base;
867 k->set_tpr = apic_set_tpr;
868 k->get_tpr = apic_get_tpr;
869 k->vapic_base_update = apic_vapic_base_update;
870 k->external_nmi = apic_external_nmi;
871 k->pre_save = apic_pre_save;
872 k->post_load = apic_post_load;
873}
874
875static TypeInfo apic_info = {
876 .name = "apic",
877 .instance_size = sizeof(APICCommonState),
878 .parent = TYPE_APIC_COMMON"apic-common",
879 .class_init = apic_class_init,
880};
881
882static void apic_register_types(void)
883{
884 type_register_static(&apic_info);
885}
886
887type_init(apic_register_types)static void __attribute__((constructor)) do_qemu_init_apic_register_types
(void) { register_module_init(apic_register_types, MODULE_INIT_QOM
); }