Bug Summary

File:target-i386/translate.c
Location:line 4144, column 5
Description:Value stored to 'rex_w' is never read

Annotated Source Code

1/*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdarg.h>
20#include <stdlib.h>
21#include <stdio.h>
22#include <string.h>
23#include <inttypes.h>
24#include <signal.h>
25
26#include "cpu.h"
27#include "disas.h"
28#include "tcg-op.h"
29
30#include "helper.h"
31#define GEN_HELPER 1
32#include "helper.h"
33
34#define PREFIX_REPZ0x01 0x01
35#define PREFIX_REPNZ0x02 0x02
36#define PREFIX_LOCK0x04 0x04
37#define PREFIX_DATA0x08 0x08
38#define PREFIX_ADR0x10 0x10
39
40#ifdef TARGET_X86_64
41#define X86_64_ONLY(x)((void*)0) x
42#define X86_64_DEF(...) __VA_ARGS__
43#define CODE64(s)0 ((s)->code64)
44#define REX_X(s)0 ((s)->rex_x)
45#define REX_B(s)0 ((s)->rex_b)
46/* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
47#if 1
48#define BUGGY_64(x) NULL((void*)0)
49#endif
50#else
51#define X86_64_ONLY(x)((void*)0) NULL((void*)0)
52#define X86_64_DEF(...)
53#define CODE64(s)0 0
54#define REX_X(s)0 0
55#define REX_B(s)0 0
56#endif
57
58//#define MACRO_TEST 1
59
60/* global register indexes */
61static TCGv_ptr cpu_env;
62static TCGvTCGv_i32 cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
63static TCGv_i32 cpu_cc_op;
64static TCGvTCGv_i32 cpu_regs[CPU_NB_REGS8];
65/* local temps */
66static TCGvTCGv_i32 cpu_T[2], cpu_T3;
67/* local register indexes (only used inside old micro ops) */
68static TCGvTCGv_i32 cpu_tmp0, cpu_tmp4;
69static TCGv_ptr cpu_ptr0, cpu_ptr1;
70static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
71static TCGv_i64 cpu_tmp1_i64;
72static TCGvTCGv_i32 cpu_tmp5;
73
74static uint8_t gen_opc_cc_op[OPC_BUF_SIZE640];
75
76#include "gen-icount.h"
77
78#ifdef TARGET_X86_64
79static int x86_64_hregs;
80#endif
81
82typedef struct DisasContext {
83 /* current insn context */
84 int override; /* -1 if no override */
85 int prefix;
86 int aflag, dflag;
87 target_ulong pc; /* pc = eip + cs_base */
88 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
89 static state change (stop translation) */
90 /* current block context */
91 target_ulong cs_base; /* base of CS segment */
92 int pe; /* protected mode */
93 int code32; /* 32 bit code segment */
94#ifdef TARGET_X86_64
95 int lma; /* long mode active */
96 int code64; /* 64 bit code segment */
97 int rex_x, rex_b;
98#endif
99 int ss32; /* 32 bit stack segment */
100 int cc_op; /* current CC operation */
101 int addseg; /* non zero if either DS/ES/SS have a non zero base */
102 int f_st; /* currently unused */
103 int vm86; /* vm86 mode */
104 int cpl;
105 int iopl;
106 int tf; /* TF cpu flag */
107 int singlestep_enabled; /* "hardware" single step enabled */
108 int jmp_opt; /* use direct block chaining for direct jumps */
109 int mem_index; /* select memory access functions */
110 uint64_t flags; /* all execution flags */
111 struct TranslationBlock *tb;
112 int popl_esp_hack; /* for correct popl with esp base handling */
113 int rip_offset; /* only used in x86_64, but left for simplicity */
114 int cpuid_features;
115 int cpuid_ext_features;
116 int cpuid_ext2_features;
117 int cpuid_ext3_features;
118} DisasContext;
119
120static void gen_eob(DisasContext *s);
121static void gen_jmp(DisasContext *s, target_ulong eip);
122static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
123
124/* i386 arith/logic operations */
125enum {
126 OP_ADDL,
127 OP_ORL,
128 OP_ADCL,
129 OP_SBBL,
130 OP_ANDL,
131 OP_SUBL,
132 OP_XORL,
133 OP_CMPL,
134};
135
136/* i386 shift ops */
137enum {
138 OP_ROL,
139 OP_ROR,
140 OP_RCL,
141 OP_RCR,
142 OP_SHL,
143 OP_SHR,
144 OP_SHL1, /* undocumented */
145 OP_SAR = 7,
146};
147
148enum {
149 JCC_O,
150 JCC_B,
151 JCC_Z,
152 JCC_BE,
153 JCC_S,
154 JCC_P,
155 JCC_L,
156 JCC_LE,
157};
158
159/* operand size */
160enum {
161 OT_BYTE = 0,
162 OT_WORD,
163 OT_LONG,
164 OT_QUAD,
165};
166
167enum {
168 /* I386 int registers */
169 OR_EAX, /* MUST be even numbered */
170 OR_ECX,
171 OR_EDX,
172 OR_EBX,
173 OR_ESP,
174 OR_EBP,
175 OR_ESI,
176 OR_EDI,
177
178 OR_TMP0 = 16, /* temporary operand register */
179 OR_TMP1,
180 OR_A0, /* temporary register used when doing address evaluation */
181};
182
183static inline void gen_op_movl_T0_0(void)
184{
185 tcg_gen_movi_tltcg_gen_movi_i32(cpu_T[0], 0);
186}
187
188static inline void gen_op_movl_T0_im(int32_t val)
189{
190 tcg_gen_movi_tltcg_gen_movi_i32(cpu_T[0], val);
191}
192
193static inline void gen_op_movl_T0_imu(uint32_t val)
194{
195 tcg_gen_movi_tltcg_gen_movi_i32(cpu_T[0], val);
196}
197
198static inline void gen_op_movl_T1_im(int32_t val)
199{
200 tcg_gen_movi_tltcg_gen_movi_i32(cpu_T[1], val);
201}
202
203static inline void gen_op_movl_T1_imu(uint32_t val)
204{
205 tcg_gen_movi_tltcg_gen_movi_i32(cpu_T[1], val);
206}
207
208static inline void gen_op_movl_A0_im(uint32_t val)
209{
210 tcg_gen_movi_tltcg_gen_movi_i32(cpu_A0, val);
211}
212
213#ifdef TARGET_X86_64
214static inline void gen_op_movq_A0_im(int64_t val)
215{
216 tcg_gen_movi_tltcg_gen_movi_i32(cpu_A0, val);
217}
218#endif
219
220static inline void gen_movtl_T0_im(target_ulong val)
221{
222 tcg_gen_movi_tltcg_gen_movi_i32(cpu_T[0], val);
223}
224
225static inline void gen_movtl_T1_im(target_ulong val)
226{
227 tcg_gen_movi_tltcg_gen_movi_i32(cpu_T[1], val);
228}
229
230static inline void gen_op_andl_T0_ffff(void)
231{
232 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
233}
234
235static inline void gen_op_andl_T0_im(uint32_t val)
236{
237 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[0], cpu_T[0], val);
238}
239
240static inline void gen_op_movl_T0_T1(void)
241{
242 tcg_gen_mov_tltcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
243}
244
245static inline void gen_op_andl_A0_ffff(void)
246{
247 tcg_gen_andi_tltcg_gen_andi_i32(cpu_A0, cpu_A0, 0xffff);
248}
249
250#ifdef TARGET_X86_64
251
252#define NB_OP_SIZES3 4
253
254#else /* !TARGET_X86_64 */
255
256#define NB_OP_SIZES3 3
257
258#endif /* !TARGET_X86_64 */
259
260#if defined(HOST_WORDS_BIGENDIAN)
261#define REG_B_OFFSET0 (sizeof(target_ulong) - 1)
262#define REG_H_OFFSET1 (sizeof(target_ulong) - 2)
263#define REG_W_OFFSET0 (sizeof(target_ulong) - 2)
264#define REG_L_OFFSET0 (sizeof(target_ulong) - 4)
265#define REG_LH_OFFSET4 (sizeof(target_ulong) - 8)
266#else
267#define REG_B_OFFSET0 0
268#define REG_H_OFFSET1 1
269#define REG_W_OFFSET0 0
270#define REG_L_OFFSET0 0
271#define REG_LH_OFFSET4 4
272#endif
273
274static inline void gen_op_mov_reg_v(int ot, int reg, TCGvTCGv_i32 t0)
275{
276 switch(ot) {
277 case OT_BYTE:
278 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
279 tcg_gen_deposit_tltcg_gen_deposit_i32(cpu_regs[reg], cpu_regs[reg], t0, 0, 8);
280 } else {
281 tcg_gen_deposit_tltcg_gen_deposit_i32(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8);
282 }
283 break;
284 case OT_WORD:
285 tcg_gen_deposit_tltcg_gen_deposit_i32(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);
286 break;
287 default: /* XXX this shouldn't be reached; abort? */
288 case OT_LONG:
289 /* For x86_64, this sets the higher half of register to zero.
290 For i386, this is equivalent to a mov. */
291 tcg_gen_ext32u_tltcg_gen_mov_i32(cpu_regs[reg], t0);
292 break;
293#ifdef TARGET_X86_64
294 case OT_QUAD:
295 tcg_gen_mov_tltcg_gen_mov_i32(cpu_regs[reg], t0);
296 break;
297#endif
298 }
299}
300
301static inline void gen_op_mov_reg_T0(int ot, int reg)
302{
303 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
304}
305
306static inline void gen_op_mov_reg_T1(int ot, int reg)
307{
308 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
309}
310
311static inline void gen_op_mov_reg_A0(int size, int reg)
312{
313 switch(size) {
314 case 0:
315 tcg_gen_deposit_tltcg_gen_deposit_i32(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
316 break;
317 default: /* XXX this shouldn't be reached; abort? */
318 case 1:
319 /* For x86_64, this sets the higher half of register to zero.
320 For i386, this is equivalent to a mov. */
321 tcg_gen_ext32u_tltcg_gen_mov_i32(cpu_regs[reg], cpu_A0);
322 break;
323#ifdef TARGET_X86_64
324 case 2:
325 tcg_gen_mov_tltcg_gen_mov_i32(cpu_regs[reg], cpu_A0);
326 break;
327#endif
328 }
329}
330
331static inline void gen_op_mov_v_reg(int ot, TCGvTCGv_i32 t0, int reg)
332{
333 switch(ot) {
334 case OT_BYTE:
335 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
336 goto std_case;
337 } else {
338 tcg_gen_shri_tltcg_gen_shri_i32(t0, cpu_regs[reg - 4], 8);
339 tcg_gen_ext8u_tltcg_gen_ext8u_i32(t0, t0);
340 }
341 break;
342 default:
343 std_case:
344 tcg_gen_mov_tltcg_gen_mov_i32(t0, cpu_regs[reg]);
345 break;
346 }
347}
348
349static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
350{
351 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
352}
353
354static inline void gen_op_movl_A0_reg(int reg)
355{
356 tcg_gen_mov_tltcg_gen_mov_i32(cpu_A0, cpu_regs[reg]);
357}
358
359static inline void gen_op_addl_A0_im(int32_t val)
360{
361 tcg_gen_addi_tltcg_gen_addi_i32(cpu_A0, cpu_A0, val);
362#ifdef TARGET_X86_64
363 tcg_gen_andi_tltcg_gen_andi_i32(cpu_A0, cpu_A0, 0xffffffff);
364#endif
365}
366
367#ifdef TARGET_X86_64
368static inline void gen_op_addq_A0_im(int64_t val)
369{
370 tcg_gen_addi_tltcg_gen_addi_i32(cpu_A0, cpu_A0, val);
371}
372#endif
373
374static void gen_add_A0_im(DisasContext *s, int val)
375{
376#ifdef TARGET_X86_64
377 if (CODE64(s)0)
378 gen_op_addq_A0_im(val);
379 else
380#endif
381 gen_op_addl_A0_im(val);
382}
383
384static inline void gen_op_addl_T0_T1(void)
385{
386 tcg_gen_add_tltcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
387}
388
389static inline void gen_op_jmp_T0(void)
390{
391 tcg_gen_st_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State, eip)__builtin_offsetof(CPUX86State, eip));
392}
393
394static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
395{
396 switch(size) {
397 case 0:
398 tcg_gen_addi_tltcg_gen_addi_i32(cpu_tmp0, cpu_regs[reg], val);
399 tcg_gen_deposit_tltcg_gen_deposit_i32(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
400 break;
401 case 1:
402 tcg_gen_addi_tltcg_gen_addi_i32(cpu_tmp0, cpu_regs[reg], val);
403 /* For x86_64, this sets the higher half of register to zero.
404 For i386, this is equivalent to a nop. */
405 tcg_gen_ext32u_tltcg_gen_mov_i32(cpu_tmp0, cpu_tmp0);
406 tcg_gen_mov_tltcg_gen_mov_i32(cpu_regs[reg], cpu_tmp0);
407 break;
408#ifdef TARGET_X86_64
409 case 2:
410 tcg_gen_addi_tltcg_gen_addi_i32(cpu_regs[reg], cpu_regs[reg], val);
411 break;
412#endif
413 }
414}
415
416static inline void gen_op_add_reg_T0(int size, int reg)
417{
418 switch(size) {
419 case 0:
420 tcg_gen_add_tltcg_gen_add_i32(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
421 tcg_gen_deposit_tltcg_gen_deposit_i32(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
422 break;
423 case 1:
424 tcg_gen_add_tltcg_gen_add_i32(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
425 /* For x86_64, this sets the higher half of register to zero.
426 For i386, this is equivalent to a nop. */
427 tcg_gen_ext32u_tltcg_gen_mov_i32(cpu_tmp0, cpu_tmp0);
428 tcg_gen_mov_tltcg_gen_mov_i32(cpu_regs[reg], cpu_tmp0);
429 break;
430#ifdef TARGET_X86_64
431 case 2:
432 tcg_gen_add_tltcg_gen_add_i32(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
433 break;
434#endif
435 }
436}
437
438static inline void gen_op_set_cc_op(int32_t val)
439{
440 tcg_gen_movi_i32(cpu_cc_op, val);
441}
442
443static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
444{
445 tcg_gen_mov_tltcg_gen_mov_i32(cpu_tmp0, cpu_regs[reg]);
446 if (shift != 0)
447 tcg_gen_shli_tltcg_gen_shli_i32(cpu_tmp0, cpu_tmp0, shift);
448 tcg_gen_add_tltcg_gen_add_i32(cpu_A0, cpu_A0, cpu_tmp0);
449 /* For x86_64, this sets the higher half of register to zero.
450 For i386, this is equivalent to a nop. */
451 tcg_gen_ext32u_tltcg_gen_mov_i32(cpu_A0, cpu_A0);
452}
453
454static inline void gen_op_movl_A0_seg(int reg)
455{
456 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base)__builtin_offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET0);
457}
458
459static inline void gen_op_addl_A0_seg(int reg)
460{
461 tcg_gen_ld_tltcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)__builtin_offsetof(CPUX86State, segs[reg].base));
462 tcg_gen_add_tltcg_gen_add_i32(cpu_A0, cpu_A0, cpu_tmp0);
463#ifdef TARGET_X86_64
464 tcg_gen_andi_tltcg_gen_andi_i32(cpu_A0, cpu_A0, 0xffffffff);
465#endif
466}
467
468#ifdef TARGET_X86_64
469static inline void gen_op_movq_A0_seg(int reg)
470{
471 tcg_gen_ld_tltcg_gen_ld_i32(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base)__builtin_offsetof(CPUX86State, segs[reg].base));
472}
473
474static inline void gen_op_addq_A0_seg(int reg)
475{
476 tcg_gen_ld_tltcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)__builtin_offsetof(CPUX86State, segs[reg].base));
477 tcg_gen_add_tltcg_gen_add_i32(cpu_A0, cpu_A0, cpu_tmp0);
478}
479
480static inline void gen_op_movq_A0_reg(int reg)
481{
482 tcg_gen_mov_tltcg_gen_mov_i32(cpu_A0, cpu_regs[reg]);
483}
484
485static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
486{
487 tcg_gen_mov_tltcg_gen_mov_i32(cpu_tmp0, cpu_regs[reg]);
488 if (shift != 0)
489 tcg_gen_shli_tltcg_gen_shli_i32(cpu_tmp0, cpu_tmp0, shift);
490 tcg_gen_add_tltcg_gen_add_i32(cpu_A0, cpu_A0, cpu_tmp0);
491}
492#endif
493
494static inline void gen_op_lds_T0_A0(int idx)
495{
496 int mem_index = (idx >> 2) - 1;
497 switch(idx & 3) {
498 case 0:
499 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
500 break;
501 case 1:
502 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
503 break;
504 default:
505 case 2:
506 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
507 break;
508 }
509}
510
511static inline void gen_op_ld_v(int idx, TCGvTCGv_i32 t0, TCGvTCGv_i32 a0)
512{
513 int mem_index = (idx >> 2) - 1;
514 switch(idx & 3) {
515 case 0:
516 tcg_gen_qemu_ld8u(t0, a0, mem_index);
517 break;
518 case 1:
519 tcg_gen_qemu_ld16u(t0, a0, mem_index);
520 break;
521 case 2:
522 tcg_gen_qemu_ld32u(t0, a0, mem_index);
523 break;
524 default:
525 case 3:
526 /* Should never happen on 32-bit targets. */
527#ifdef TARGET_X86_64
528 tcg_gen_qemu_ld64(t0, a0, mem_index);
529#endif
530 break;
531 }
532}
533
534/* XXX: always use ldu or lds */
535static inline void gen_op_ld_T0_A0(int idx)
536{
537 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
538}
539
540static inline void gen_op_ldu_T0_A0(int idx)
541{
542 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
543}
544
545static inline void gen_op_ld_T1_A0(int idx)
546{
547 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
548}
549
550static inline void gen_op_st_v(int idx, TCGvTCGv_i32 t0, TCGvTCGv_i32 a0)
551{
552 int mem_index = (idx >> 2) - 1;
553 switch(idx & 3) {
554 case 0:
555 tcg_gen_qemu_st8(t0, a0, mem_index);
556 break;
557 case 1:
558 tcg_gen_qemu_st16(t0, a0, mem_index);
559 break;
560 case 2:
561 tcg_gen_qemu_st32(t0, a0, mem_index);
562 break;
563 default:
564 case 3:
565 /* Should never happen on 32-bit targets. */
566#ifdef TARGET_X86_64
567 tcg_gen_qemu_st64(t0, a0, mem_index);
568#endif
569 break;
570 }
571}
572
573static inline void gen_op_st_T0_A0(int idx)
574{
575 gen_op_st_v(idx, cpu_T[0], cpu_A0);
576}
577
578static inline void gen_op_st_T1_A0(int idx)
579{
580 gen_op_st_v(idx, cpu_T[1], cpu_A0);
581}
582
583static inline void gen_jmp_im(target_ulong pc)
584{
585 tcg_gen_movi_tltcg_gen_movi_i32(cpu_tmp0, pc);
586 tcg_gen_st_tltcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip)__builtin_offsetof(CPUX86State, eip));
587}
588
589static inline void gen_string_movl_A0_ESI(DisasContext *s)
590{
591 int override;
592
593 override = s->override;
594#ifdef TARGET_X86_64
595 if (s->aflag == 2) {
596 if (override >= 0) {
597 gen_op_movq_A0_seg(override);
598 gen_op_addq_A0_reg_sN(0, R_ESI6);
599 } else {
600 gen_op_movq_A0_reg(R_ESI6);
601 }
602 } else
603#endif
604 if (s->aflag) {
605 /* 32 bit address */
606 if (s->addseg && override < 0)
607 override = R_DS3;
608 if (override >= 0) {
609 gen_op_movl_A0_seg(override);
610 gen_op_addl_A0_reg_sN(0, R_ESI6);
611 } else {
612 gen_op_movl_A0_reg(R_ESI6);
613 }
614 } else {
615 /* 16 address, always override */
616 if (override < 0)
617 override = R_DS3;
618 gen_op_movl_A0_reg(R_ESI6);
619 gen_op_andl_A0_ffff();
620 gen_op_addl_A0_seg(override);
621 }
622}
623
624static inline void gen_string_movl_A0_EDI(DisasContext *s)
625{
626#ifdef TARGET_X86_64
627 if (s->aflag == 2) {
628 gen_op_movq_A0_reg(R_EDI7);
629 } else
630#endif
631 if (s->aflag) {
632 if (s->addseg) {
633 gen_op_movl_A0_seg(R_ES0);
634 gen_op_addl_A0_reg_sN(0, R_EDI7);
635 } else {
636 gen_op_movl_A0_reg(R_EDI7);
637 }
638 } else {
639 gen_op_movl_A0_reg(R_EDI7);
640 gen_op_andl_A0_ffff();
641 gen_op_addl_A0_seg(R_ES0);
642 }
643}
644
645static inline void gen_op_movl_T0_Dshift(int ot)
646{
647 tcg_gen_ld32s_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State, df)__builtin_offsetof(CPUX86State, df));
648 tcg_gen_shli_tltcg_gen_shli_i32(cpu_T[0], cpu_T[0], ot);
649};
650
651static void gen_extu(int ot, TCGvTCGv_i32 reg)
652{
653 switch(ot) {
654 case OT_BYTE:
655 tcg_gen_ext8u_tltcg_gen_ext8u_i32(reg, reg);
656 break;
657 case OT_WORD:
658 tcg_gen_ext16u_tltcg_gen_ext16u_i32(reg, reg);
659 break;
660 case OT_LONG:
661 tcg_gen_ext32u_tltcg_gen_mov_i32(reg, reg);
662 break;
663 default:
664 break;
665 }
666}
667
668static void gen_exts(int ot, TCGvTCGv_i32 reg)
669{
670 switch(ot) {
671 case OT_BYTE:
672 tcg_gen_ext8s_tltcg_gen_ext8s_i32(reg, reg);
673 break;
674 case OT_WORD:
675 tcg_gen_ext16s_tltcg_gen_ext16s_i32(reg, reg);
676 break;
677 case OT_LONG:
678 tcg_gen_ext32s_tltcg_gen_mov_i32(reg, reg);
679 break;
680 default:
681 break;
682 }
683}
684
685static inline void gen_op_jnz_ecx(int size, int label1)
686{
687 tcg_gen_mov_tltcg_gen_mov_i32(cpu_tmp0, cpu_regs[R_ECX1]);
688 gen_extu(size + 1, cpu_tmp0);
689 tcg_gen_brcondi_tltcg_gen_brcondi_i32(TCG_COND_NE, cpu_tmp0, 0, label1);
690}
691
692static inline void gen_op_jz_ecx(int size, int label1)
693{
694 tcg_gen_mov_tltcg_gen_mov_i32(cpu_tmp0, cpu_regs[R_ECX1]);
695 gen_extu(size + 1, cpu_tmp0);
696 tcg_gen_brcondi_tltcg_gen_brcondi_i32(TCG_COND_EQ, cpu_tmp0, 0, label1);
697}
698
699static void gen_helper_in_func(int ot, TCGvTCGv_i32 v, TCGv_i32 n)
700{
701 switch (ot) {
702 case 0: gen_helper_inb(v, n); break;
703 case 1: gen_helper_inw(v, n); break;
704 case 2: gen_helper_inl(v, n); break;
705 }
706
707}
708
709static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
710{
711 switch (ot) {
712 case 0: gen_helper_outb(v, n); break;
713 case 1: gen_helper_outw(v, n); break;
714 case 2: gen_helper_outl(v, n); break;
715 }
716
717}
718
719static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
720 uint32_t svm_flags)
721{
722 int state_saved;
723 target_ulong next_eip;
724
725 state_saved = 0;
726 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
727 if (s->cc_op != CC_OP_DYNAMIC)
728 gen_op_set_cc_op(s->cc_op);
729 gen_jmp_im(cur_eip);
730 state_saved = 1;
731 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
732 switch (ot) {
733 case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
734 case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
735 case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
736 }
737 }
738 if(s->flags & HF_SVMI_MASK(1 << 21)) {
739 if (!state_saved) {
740 if (s->cc_op != CC_OP_DYNAMIC)
741 gen_op_set_cc_op(s->cc_op);
742 gen_jmp_im(cur_eip);
743 }
744 svm_flags |= (1 << (4 + ot));
745 next_eip = s->pc - s->cs_base;
746 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
747 gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),
748 tcg_const_i32(next_eip - cur_eip));
749 }
750}
751
752static inline void gen_movs(DisasContext *s, int ot)
753{
754 gen_string_movl_A0_ESI(s);
755 gen_op_ld_T0_A0(ot + s->mem_index);
756 gen_string_movl_A0_EDI(s);
757 gen_op_st_T0_A0(ot + s->mem_index);
758 gen_op_movl_T0_Dshift(ot);
759 gen_op_add_reg_T0(s->aflag, R_ESI6);
760 gen_op_add_reg_T0(s->aflag, R_EDI7);
761}
762
763static inline void gen_update_cc_op(DisasContext *s)
764{
765 if (s->cc_op != CC_OP_DYNAMIC) {
766 gen_op_set_cc_op(s->cc_op);
767 s->cc_op = CC_OP_DYNAMIC;
768 }
769}
770
771static void gen_op_update1_cc(void)
772{
773 tcg_gen_discard_tltcg_gen_discard_i32(cpu_cc_src);
774 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
775}
776
777static void gen_op_update2_cc(void)
778{
779 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_src, cpu_T[1]);
780 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
781}
782
783static inline void gen_op_cmpl_T0_T1_cc(void)
784{
785 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_src, cpu_T[1]);
786 tcg_gen_sub_tltcg_gen_sub_i32(cpu_cc_dst, cpu_T[0], cpu_T[1]);
787}
788
789static inline void gen_op_testl_T0_T1_cc(void)
790{
791 tcg_gen_discard_tltcg_gen_discard_i32(cpu_cc_src);
792 tcg_gen_and_tltcg_gen_and_i32(cpu_cc_dst, cpu_T[0], cpu_T[1]);
793}
794
795static void gen_op_update_neg_cc(void)
796{
797 tcg_gen_neg_tltcg_gen_neg_i32(cpu_cc_src, cpu_T[0]);
798 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
799}
800
801/* compute eflags.C to reg */
802static void gen_compute_eflags_c(TCGvTCGv_i32 reg)
803{
804 gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);
805 tcg_gen_extu_i32_tltcg_gen_mov_i32(reg, cpu_tmp2_i32);
806}
807
808/* compute all eflags to cc_src */
809static void gen_compute_eflags(TCGvTCGv_i32 reg)
810{
811 gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);
812 tcg_gen_extu_i32_tltcg_gen_mov_i32(reg, cpu_tmp2_i32);
813}
814
815static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
816{
817 if (s->cc_op != CC_OP_DYNAMIC)
818 gen_op_set_cc_op(s->cc_op);
819 switch(jcc_op) {
820 case JCC_O:
821 gen_compute_eflags(cpu_T[0]);
822 tcg_gen_shri_tltcg_gen_shri_i32(cpu_T[0], cpu_T[0], 11);
823 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[0], cpu_T[0], 1);
824 break;
825 case JCC_B:
826 gen_compute_eflags_c(cpu_T[0]);
827 break;
828 case JCC_Z:
829 gen_compute_eflags(cpu_T[0]);
830 tcg_gen_shri_tltcg_gen_shri_i32(cpu_T[0], cpu_T[0], 6);
831 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[0], cpu_T[0], 1);
832 break;
833 case JCC_BE:
834 gen_compute_eflags(cpu_tmp0);
835 tcg_gen_shri_tltcg_gen_shri_i32(cpu_T[0], cpu_tmp0, 6);
836 tcg_gen_or_tltcg_gen_or_i32(cpu_T[0], cpu_T[0], cpu_tmp0);
837 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[0], cpu_T[0], 1);
838 break;
839 case JCC_S:
840 gen_compute_eflags(cpu_T[0]);
841 tcg_gen_shri_tltcg_gen_shri_i32(cpu_T[0], cpu_T[0], 7);
842 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[0], cpu_T[0], 1);
843 break;
844 case JCC_P:
845 gen_compute_eflags(cpu_T[0]);
846 tcg_gen_shri_tltcg_gen_shri_i32(cpu_T[0], cpu_T[0], 2);
847 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[0], cpu_T[0], 1);
848 break;
849 case JCC_L:
850 gen_compute_eflags(cpu_tmp0);
851 tcg_gen_shri_tltcg_gen_shri_i32(cpu_T[0], cpu_tmp0, 11); /* CC_O */
852 tcg_gen_shri_tltcg_gen_shri_i32(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
853 tcg_gen_xor_tltcg_gen_xor_i32(cpu_T[0], cpu_T[0], cpu_tmp0);
854 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[0], cpu_T[0], 1);
855 break;
856 default:
857 case JCC_LE:
858 gen_compute_eflags(cpu_tmp0);
859 tcg_gen_shri_tltcg_gen_shri_i32(cpu_T[0], cpu_tmp0, 11); /* CC_O */
860 tcg_gen_shri_tltcg_gen_shri_i32(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
861 tcg_gen_shri_tltcg_gen_shri_i32(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
862 tcg_gen_xor_tltcg_gen_xor_i32(cpu_T[0], cpu_T[0], cpu_tmp4);
863 tcg_gen_or_tltcg_gen_or_i32(cpu_T[0], cpu_T[0], cpu_tmp0);
864 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[0], cpu_T[0], 1);
865 break;
866 }
867}
868
869/* return true if setcc_slow is not needed (WARNING: must be kept in
870 sync with gen_jcc1) */
871static int is_fast_jcc_case(DisasContext *s, int b)
872{
873 int jcc_op;
874 jcc_op = (b >> 1) & 7;
875 switch(s->cc_op) {
876 /* we optimize the cmp/jcc case */
877 case CC_OP_SUBB:
878 case CC_OP_SUBW:
879 case CC_OP_SUBL:
880 case CC_OP_SUBQ:
881 if (jcc_op == JCC_O || jcc_op == JCC_P)
882 goto slow_jcc;
883 break;
884
885 /* some jumps are easy to compute */
886 case CC_OP_ADDB:
887 case CC_OP_ADDW:
888 case CC_OP_ADDL:
889 case CC_OP_ADDQ:
890
891 case CC_OP_LOGICB:
892 case CC_OP_LOGICW:
893 case CC_OP_LOGICL:
894 case CC_OP_LOGICQ:
895
896 case CC_OP_INCB:
897 case CC_OP_INCW:
898 case CC_OP_INCL:
899 case CC_OP_INCQ:
900
901 case CC_OP_DECB:
902 case CC_OP_DECW:
903 case CC_OP_DECL:
904 case CC_OP_DECQ:
905
906 case CC_OP_SHLB:
907 case CC_OP_SHLW:
908 case CC_OP_SHLL:
909 case CC_OP_SHLQ:
910 if (jcc_op != JCC_Z && jcc_op != JCC_S)
911 goto slow_jcc;
912 break;
913 default:
914 slow_jcc:
915 return 0;
916 }
917 return 1;
918}
919
920/* generate a conditional jump to label 'l1' according to jump opcode
921 value 'b'. In the fast case, T0 is guaranted not to be used. */
922static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
923{
924 int inv, jcc_op, size, cond;
925 TCGvTCGv_i32 t0;
926
927 inv = b & 1;
928 jcc_op = (b >> 1) & 7;
929
930 switch(cc_op) {
931 /* we optimize the cmp/jcc case */
932 case CC_OP_SUBB:
933 case CC_OP_SUBW:
934 case CC_OP_SUBL:
935 case CC_OP_SUBQ:
936
937 size = cc_op - CC_OP_SUBB;
938 switch(jcc_op) {
939 case JCC_Z:
940 fast_jcc_z:
941 switch(size) {
942 case 0:
943 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp0, cpu_cc_dst, 0xff);
944 t0 = cpu_tmp0;
945 break;
946 case 1:
947 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp0, cpu_cc_dst, 0xffff);
948 t0 = cpu_tmp0;
949 break;
950#ifdef TARGET_X86_64
951 case 2:
952 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp0, cpu_cc_dst, 0xffffffff);
953 t0 = cpu_tmp0;
954 break;
955#endif
956 default:
957 t0 = cpu_cc_dst;
958 break;
959 }
960 tcg_gen_brcondi_tltcg_gen_brcondi_i32(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
961 break;
962 case JCC_S:
963 fast_jcc_s:
964 switch(size) {
965 case 0:
966 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp0, cpu_cc_dst, 0x80);
967 tcg_gen_brcondi_tltcg_gen_brcondi_i32(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
968 0, l1);
969 break;
970 case 1:
971 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp0, cpu_cc_dst, 0x8000);
972 tcg_gen_brcondi_tltcg_gen_brcondi_i32(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
973 0, l1);
974 break;
975#ifdef TARGET_X86_64
976 case 2:
977 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp0, cpu_cc_dst, 0x80000000);
978 tcg_gen_brcondi_tltcg_gen_brcondi_i32(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
979 0, l1);
980 break;
981#endif
982 default:
983 tcg_gen_brcondi_tltcg_gen_brcondi_i32(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
984 0, l1);
985 break;
986 }
987 break;
988
989 case JCC_B:
990 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
991 goto fast_jcc_b;
992 case JCC_BE:
993 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
994 fast_jcc_b:
995 tcg_gen_add_tltcg_gen_add_i32(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
996 switch(size) {
997 case 0:
998 t0 = cpu_tmp0;
999 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp4, cpu_tmp4, 0xff);
1000 tcg_gen_andi_tltcg_gen_andi_i32(t0, cpu_cc_src, 0xff);
1001 break;
1002 case 1:
1003 t0 = cpu_tmp0;
1004 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp4, cpu_tmp4, 0xffff);
1005 tcg_gen_andi_tltcg_gen_andi_i32(t0, cpu_cc_src, 0xffff);
1006 break;
1007#ifdef TARGET_X86_64
1008 case 2:
1009 t0 = cpu_tmp0;
1010 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp4, cpu_tmp4, 0xffffffff);
1011 tcg_gen_andi_tltcg_gen_andi_i32(t0, cpu_cc_src, 0xffffffff);
1012 break;
1013#endif
1014 default:
1015 t0 = cpu_cc_src;
1016 break;
1017 }
1018 tcg_gen_brcond_tltcg_gen_brcond_i32(cond, cpu_tmp4, t0, l1);
1019 break;
1020
1021 case JCC_L:
1022 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1023 goto fast_jcc_l;
1024 case JCC_LE:
1025 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1026 fast_jcc_l:
1027 tcg_gen_add_tltcg_gen_add_i32(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1028 switch(size) {
1029 case 0:
1030 t0 = cpu_tmp0;
1031 tcg_gen_ext8s_tltcg_gen_ext8s_i32(cpu_tmp4, cpu_tmp4);
1032 tcg_gen_ext8s_tltcg_gen_ext8s_i32(t0, cpu_cc_src);
1033 break;
1034 case 1:
1035 t0 = cpu_tmp0;
1036 tcg_gen_ext16s_tltcg_gen_ext16s_i32(cpu_tmp4, cpu_tmp4);
1037 tcg_gen_ext16s_tltcg_gen_ext16s_i32(t0, cpu_cc_src);
1038 break;
1039#ifdef TARGET_X86_64
1040 case 2:
1041 t0 = cpu_tmp0;
1042 tcg_gen_ext32s_tltcg_gen_mov_i32(cpu_tmp4, cpu_tmp4);
1043 tcg_gen_ext32s_tltcg_gen_mov_i32(t0, cpu_cc_src);
1044 break;
1045#endif
1046 default:
1047 t0 = cpu_cc_src;
1048 break;
1049 }
1050 tcg_gen_brcond_tltcg_gen_brcond_i32(cond, cpu_tmp4, t0, l1);
1051 break;
1052
1053 default:
1054 goto slow_jcc;
1055 }
1056 break;
1057
1058 /* some jumps are easy to compute */
1059 case CC_OP_ADDB:
1060 case CC_OP_ADDW:
1061 case CC_OP_ADDL:
1062 case CC_OP_ADDQ:
1063
1064 case CC_OP_ADCB:
1065 case CC_OP_ADCW:
1066 case CC_OP_ADCL:
1067 case CC_OP_ADCQ:
1068
1069 case CC_OP_SBBB:
1070 case CC_OP_SBBW:
1071 case CC_OP_SBBL:
1072 case CC_OP_SBBQ:
1073
1074 case CC_OP_LOGICB:
1075 case CC_OP_LOGICW:
1076 case CC_OP_LOGICL:
1077 case CC_OP_LOGICQ:
1078
1079 case CC_OP_INCB:
1080 case CC_OP_INCW:
1081 case CC_OP_INCL:
1082 case CC_OP_INCQ:
1083
1084 case CC_OP_DECB:
1085 case CC_OP_DECW:
1086 case CC_OP_DECL:
1087 case CC_OP_DECQ:
1088
1089 case CC_OP_SHLB:
1090 case CC_OP_SHLW:
1091 case CC_OP_SHLL:
1092 case CC_OP_SHLQ:
1093
1094 case CC_OP_SARB:
1095 case CC_OP_SARW:
1096 case CC_OP_SARL:
1097 case CC_OP_SARQ:
1098 switch(jcc_op) {
1099 case JCC_Z:
1100 size = (cc_op - CC_OP_ADDB) & 3;
1101 goto fast_jcc_z;
1102 case JCC_S:
1103 size = (cc_op - CC_OP_ADDB) & 3;
1104 goto fast_jcc_s;
1105 default:
1106 goto slow_jcc;
1107 }
1108 break;
1109 default:
1110 slow_jcc:
1111 gen_setcc_slow_T0(s, jcc_op);
1112 tcg_gen_brcondi_tltcg_gen_brcondi_i32(inv ? TCG_COND_EQ : TCG_COND_NE,
1113 cpu_T[0], 0, l1);
1114 break;
1115 }
1116}
1117
1118/* XXX: does not work with gdbstub "ice" single step - not a
1119 serious problem */
1120static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1121{
1122 int l1, l2;
1123
1124 l1 = gen_new_label();
1125 l2 = gen_new_label();
1126 gen_op_jnz_ecx(s->aflag, l1);
1127 gen_set_label(l2);
1128 gen_jmp_tb(s, next_eip, 1);
1129 gen_set_label(l1);
1130 return l2;
1131}
1132
1133static inline void gen_stos(DisasContext *s, int ot)
1134{
1135 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX0);
1136 gen_string_movl_A0_EDI(s);
1137 gen_op_st_T0_A0(ot + s->mem_index);
1138 gen_op_movl_T0_Dshift(ot);
1139 gen_op_add_reg_T0(s->aflag, R_EDI7);
1140}
1141
1142static inline void gen_lods(DisasContext *s, int ot)
1143{
1144 gen_string_movl_A0_ESI(s);
1145 gen_op_ld_T0_A0(ot + s->mem_index);
1146 gen_op_mov_reg_T0(ot, R_EAX0);
1147 gen_op_movl_T0_Dshift(ot);
1148 gen_op_add_reg_T0(s->aflag, R_ESI6);
1149}
1150
1151static inline void gen_scas(DisasContext *s, int ot)
1152{
1153 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX0);
1154 gen_string_movl_A0_EDI(s);
1155 gen_op_ld_T1_A0(ot + s->mem_index);
1156 gen_op_cmpl_T0_T1_cc();
1157 gen_op_movl_T0_Dshift(ot);
1158 gen_op_add_reg_T0(s->aflag, R_EDI7);
1159}
1160
1161static inline void gen_cmps(DisasContext *s, int ot)
1162{
1163 gen_string_movl_A0_ESI(s);
1164 gen_op_ld_T0_A0(ot + s->mem_index);
1165 gen_string_movl_A0_EDI(s);
1166 gen_op_ld_T1_A0(ot + s->mem_index);
1167 gen_op_cmpl_T0_T1_cc();
1168 gen_op_movl_T0_Dshift(ot);
1169 gen_op_add_reg_T0(s->aflag, R_ESI6);
1170 gen_op_add_reg_T0(s->aflag, R_EDI7);
1171}
1172
1173static inline void gen_ins(DisasContext *s, int ot)
1174{
1175 if (use_icount)
1176 gen_io_start();
1177 gen_string_movl_A0_EDI(s);
1178 /* Note: we must do this dummy write first to be restartable in
1179 case of page fault. */
1180 gen_op_movl_T0_0();
1181 gen_op_st_T0_A0(ot + s->mem_index);
1182 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX2);
1183 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[1]);
1184 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1185 gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1186 gen_op_st_T0_A0(ot + s->mem_index);
1187 gen_op_movl_T0_Dshift(ot);
1188 gen_op_add_reg_T0(s->aflag, R_EDI7);
1189 if (use_icount)
1190 gen_io_end();
1191}
1192
1193static inline void gen_outs(DisasContext *s, int ot)
1194{
1195 if (use_icount)
1196 gen_io_start();
1197 gen_string_movl_A0_ESI(s);
1198 gen_op_ld_T0_A0(ot + s->mem_index);
1199
1200 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX2);
1201 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[1]);
1202 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1203 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp3_i32, cpu_T[0]);
1204 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1205
1206 gen_op_movl_T0_Dshift(ot);
1207 gen_op_add_reg_T0(s->aflag, R_ESI6);
1208 if (use_icount)
1209 gen_io_end();
1210}
1211
1212/* same method as Valgrind : we generate jumps to current or next
1213 instruction */
1214#define GEN_REPZ(op)static inline void gen_repz_op(DisasContext *s, int ot, target_ulong
cur_eip, target_ulong next_eip) { int l2; gen_update_cc_op(s
); l2 = gen_jz_ecx_string(s, next_eip); gen_op(s, ot); gen_op_add_reg_im
(s->aflag, 1, -1); if (!s->jmp_opt) gen_op_jz_ecx(s->
aflag, l2); gen_jmp(s, cur_eip); } \
1215static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1216 target_ulong cur_eip, target_ulong next_eip) \
1217{ \
1218 int l2;\
1219 gen_update_cc_op(s); \
1220 l2 = gen_jz_ecx_string(s, next_eip); \
1221 gen_ ## op(s, ot); \
1222 gen_op_add_reg_im(s->aflag, R_ECX1, -1); \
1223 /* a loop would cause two single step exceptions if ECX = 1 \
1224 before rep string_insn */ \
1225 if (!s->jmp_opt) \
1226 gen_op_jz_ecx(s->aflag, l2); \
1227 gen_jmp(s, cur_eip); \
1228}
1229
1230#define GEN_REPZ2(op)static inline void gen_repz_op(DisasContext *s, int ot, target_ulong
cur_eip, target_ulong next_eip, int nz) { int l2; gen_update_cc_op
(s); l2 = gen_jz_ecx_string(s, next_eip); gen_op(s, ot); gen_op_add_reg_im
(s->aflag, 1, -1); gen_op_set_cc_op(CC_OP_SUBB + ot); gen_jcc1
(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); if (
!s->jmp_opt) gen_op_jz_ecx(s->aflag, l2); gen_jmp(s, cur_eip
); } \
1231static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1232 target_ulong cur_eip, \
1233 target_ulong next_eip, \
1234 int nz) \
1235{ \
1236 int l2;\
1237 gen_update_cc_op(s); \
1238 l2 = gen_jz_ecx_string(s, next_eip); \
1239 gen_ ## op(s, ot); \
1240 gen_op_add_reg_im(s->aflag, R_ECX1, -1); \
1241 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1242 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1243 if (!s->jmp_opt) \
1244 gen_op_jz_ecx(s->aflag, l2); \
1245 gen_jmp(s, cur_eip); \
1246}
1247
1248GEN_REPZ(movs)static inline void gen_repz_movs(DisasContext *s, int ot, target_ulong
cur_eip, target_ulong next_eip) { int l2; gen_update_cc_op(s
); l2 = gen_jz_ecx_string(s, next_eip); gen_movs(s, ot); gen_op_add_reg_im
(s->aflag, 1, -1); if (!s->jmp_opt) gen_op_jz_ecx(s->
aflag, l2); gen_jmp(s, cur_eip); }
1249GEN_REPZ(stos)static inline void gen_repz_stos(DisasContext *s, int ot, target_ulong
cur_eip, target_ulong next_eip) { int l2; gen_update_cc_op(s
); l2 = gen_jz_ecx_string(s, next_eip); gen_stos(s, ot); gen_op_add_reg_im
(s->aflag, 1, -1); if (!s->jmp_opt) gen_op_jz_ecx(s->
aflag, l2); gen_jmp(s, cur_eip); }
1250GEN_REPZ(lods)static inline void gen_repz_lods(DisasContext *s, int ot, target_ulong
cur_eip, target_ulong next_eip) { int l2; gen_update_cc_op(s
); l2 = gen_jz_ecx_string(s, next_eip); gen_lods(s, ot); gen_op_add_reg_im
(s->aflag, 1, -1); if (!s->jmp_opt) gen_op_jz_ecx(s->
aflag, l2); gen_jmp(s, cur_eip); }
1251GEN_REPZ(ins)static inline void gen_repz_ins(DisasContext *s, int ot, target_ulong
cur_eip, target_ulong next_eip) { int l2; gen_update_cc_op(s
); l2 = gen_jz_ecx_string(s, next_eip); gen_ins(s, ot); gen_op_add_reg_im
(s->aflag, 1, -1); if (!s->jmp_opt) gen_op_jz_ecx(s->
aflag, l2); gen_jmp(s, cur_eip); }
1252GEN_REPZ(outs)static inline void gen_repz_outs(DisasContext *s, int ot, target_ulong
cur_eip, target_ulong next_eip) { int l2; gen_update_cc_op(s
); l2 = gen_jz_ecx_string(s, next_eip); gen_outs(s, ot); gen_op_add_reg_im
(s->aflag, 1, -1); if (!s->jmp_opt) gen_op_jz_ecx(s->
aflag, l2); gen_jmp(s, cur_eip); }
1253GEN_REPZ2(scas)static inline void gen_repz_scas(DisasContext *s, int ot, target_ulong
cur_eip, target_ulong next_eip, int nz) { int l2; gen_update_cc_op
(s); l2 = gen_jz_ecx_string(s, next_eip); gen_scas(s, ot); gen_op_add_reg_im
(s->aflag, 1, -1); gen_op_set_cc_op(CC_OP_SUBB + ot); gen_jcc1
(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); if (
!s->jmp_opt) gen_op_jz_ecx(s->aflag, l2); gen_jmp(s, cur_eip
); }
1254GEN_REPZ2(cmps)static inline void gen_repz_cmps(DisasContext *s, int ot, target_ulong
cur_eip, target_ulong next_eip, int nz) { int l2; gen_update_cc_op
(s); l2 = gen_jz_ecx_string(s, next_eip); gen_cmps(s, ot); gen_op_add_reg_im
(s->aflag, 1, -1); gen_op_set_cc_op(CC_OP_SUBB + ot); gen_jcc1
(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); if (
!s->jmp_opt) gen_op_jz_ecx(s->aflag, l2); gen_jmp(s, cur_eip
); }
1255
1256static void gen_helper_fp_arith_ST0_FT0(int op)
1257{
1258 switch (op) {
1259 case 0: gen_helper_fadd_ST0_FT0(); break;
1260 case 1: gen_helper_fmul_ST0_FT0(); break;
1261 case 2: gen_helper_fcom_ST0_FT0(); break;
1262 case 3: gen_helper_fcom_ST0_FT0(); break;
1263 case 4: gen_helper_fsub_ST0_FT0(); break;
1264 case 5: gen_helper_fsubr_ST0_FT0(); break;
1265 case 6: gen_helper_fdiv_ST0_FT0(); break;
1266 case 7: gen_helper_fdivr_ST0_FT0(); break;
1267 }
1268}
1269
1270/* NOTE the exception in "r" op ordering */
1271static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1272{
1273 TCGv_i32 tmp = tcg_const_i32(opreg);
1274 switch (op) {
1275 case 0: gen_helper_fadd_STN_ST0(tmp); break;
1276 case 1: gen_helper_fmul_STN_ST0(tmp); break;
1277 case 4: gen_helper_fsubr_STN_ST0(tmp); break;
1278 case 5: gen_helper_fsub_STN_ST0(tmp); break;
1279 case 6: gen_helper_fdivr_STN_ST0(tmp); break;
1280 case 7: gen_helper_fdiv_STN_ST0(tmp); break;
1281 }
1282}
1283
1284/* if d == OR_TMP0, it means memory operand (address in A0) */
1285static void gen_op(DisasContext *s1, int op, int ot, int d)
1286{
1287 if (d != OR_TMP0) {
1288 gen_op_mov_TN_reg(ot, 0, d);
1289 } else {
1290 gen_op_ld_T0_A0(ot + s1->mem_index);
1291 }
1292 switch(op) {
1293 case OP_ADCL:
1294 if (s1->cc_op != CC_OP_DYNAMIC)
1295 gen_op_set_cc_op(s1->cc_op);
1296 gen_compute_eflags_c(cpu_tmp4);
1297 tcg_gen_add_tltcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
1298 tcg_gen_add_tltcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_tmp4);
1299 if (d != OR_TMP0)
1300 gen_op_mov_reg_T0(ot, d);
1301 else
1302 gen_op_st_T0_A0(ot + s1->mem_index);
1303 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_src, cpu_T[1]);
1304 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
1305 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_tmp4);
1306 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1307 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1308 s1->cc_op = CC_OP_DYNAMIC;
1309 break;
1310 case OP_SBBL:
1311 if (s1->cc_op != CC_OP_DYNAMIC)
1312 gen_op_set_cc_op(s1->cc_op);
1313 gen_compute_eflags_c(cpu_tmp4);
1314 tcg_gen_sub_tltcg_gen_sub_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
1315 tcg_gen_sub_tltcg_gen_sub_i32(cpu_T[0], cpu_T[0], cpu_tmp4);
1316 if (d != OR_TMP0)
1317 gen_op_mov_reg_T0(ot, d);
1318 else
1319 gen_op_st_T0_A0(ot + s1->mem_index);
1320 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_src, cpu_T[1]);
1321 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
1322 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_tmp4);
1323 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1324 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1325 s1->cc_op = CC_OP_DYNAMIC;
1326 break;
1327 case OP_ADDL:
1328 gen_op_addl_T0_T1();
1329 if (d != OR_TMP0)
1330 gen_op_mov_reg_T0(ot, d);
1331 else
1332 gen_op_st_T0_A0(ot + s1->mem_index);
1333 gen_op_update2_cc();
1334 s1->cc_op = CC_OP_ADDB + ot;
1335 break;
1336 case OP_SUBL:
1337 tcg_gen_sub_tltcg_gen_sub_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
1338 if (d != OR_TMP0)
1339 gen_op_mov_reg_T0(ot, d);
1340 else
1341 gen_op_st_T0_A0(ot + s1->mem_index);
1342 gen_op_update2_cc();
1343 s1->cc_op = CC_OP_SUBB + ot;
1344 break;
1345 default:
1346 case OP_ANDL:
1347 tcg_gen_and_tltcg_gen_and_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
1348 if (d != OR_TMP0)
1349 gen_op_mov_reg_T0(ot, d);
1350 else
1351 gen_op_st_T0_A0(ot + s1->mem_index);
1352 gen_op_update1_cc();
1353 s1->cc_op = CC_OP_LOGICB + ot;
1354 break;
1355 case OP_ORL:
1356 tcg_gen_or_tltcg_gen_or_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
1357 if (d != OR_TMP0)
1358 gen_op_mov_reg_T0(ot, d);
1359 else
1360 gen_op_st_T0_A0(ot + s1->mem_index);
1361 gen_op_update1_cc();
1362 s1->cc_op = CC_OP_LOGICB + ot;
1363 break;
1364 case OP_XORL:
1365 tcg_gen_xor_tltcg_gen_xor_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
1366 if (d != OR_TMP0)
1367 gen_op_mov_reg_T0(ot, d);
1368 else
1369 gen_op_st_T0_A0(ot + s1->mem_index);
1370 gen_op_update1_cc();
1371 s1->cc_op = CC_OP_LOGICB + ot;
1372 break;
1373 case OP_CMPL:
1374 gen_op_cmpl_T0_T1_cc();
1375 s1->cc_op = CC_OP_SUBB + ot;
1376 break;
1377 }
1378}
1379
1380/* if d == OR_TMP0, it means memory operand (address in A0) */
1381static void gen_inc(DisasContext *s1, int ot, int d, int c)
1382{
1383 if (d != OR_TMP0)
1384 gen_op_mov_TN_reg(ot, 0, d);
1385 else
1386 gen_op_ld_T0_A0(ot + s1->mem_index);
1387 if (s1->cc_op != CC_OP_DYNAMIC)
1388 gen_op_set_cc_op(s1->cc_op);
1389 if (c > 0) {
1390 tcg_gen_addi_tltcg_gen_addi_i32(cpu_T[0], cpu_T[0], 1);
1391 s1->cc_op = CC_OP_INCB + ot;
1392 } else {
1393 tcg_gen_addi_tltcg_gen_addi_i32(cpu_T[0], cpu_T[0], -1);
1394 s1->cc_op = CC_OP_DECB + ot;
1395 }
1396 if (d != OR_TMP0)
1397 gen_op_mov_reg_T0(ot, d);
1398 else
1399 gen_op_st_T0_A0(ot + s1->mem_index);
1400 gen_compute_eflags_c(cpu_cc_src);
1401 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
1402}
1403
1404static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1405 int is_right, int is_arith)
1406{
1407 target_ulong mask;
1408 int shift_label;
1409 TCGvTCGv_i32 t0, t1, t2;
1410
1411 if (ot == OT_QUAD) {
1412 mask = 0x3f;
1413 } else {
1414 mask = 0x1f;
1415 }
1416
1417 /* load */
1418 if (op1 == OR_TMP0) {
1419 gen_op_ld_T0_A0(ot + s->mem_index);
1420 } else {
1421 gen_op_mov_TN_reg(ot, 0, op1);
1422 }
1423
1424 t0 = tcg_temp_local_new()tcg_temp_local_new_i32();
1425 t1 = tcg_temp_local_new()tcg_temp_local_new_i32();
1426 t2 = tcg_temp_local_new()tcg_temp_local_new_i32();
1427
1428 tcg_gen_andi_tltcg_gen_andi_i32(t2, cpu_T[1], mask);
1429
1430 if (is_right) {
1431 if (is_arith) {
1432 gen_exts(ot, cpu_T[0]);
1433 tcg_gen_mov_tltcg_gen_mov_i32(t0, cpu_T[0]);
1434 tcg_gen_sar_tltcg_gen_sar_i32(cpu_T[0], cpu_T[0], t2);
1435 } else {
1436 gen_extu(ot, cpu_T[0]);
1437 tcg_gen_mov_tltcg_gen_mov_i32(t0, cpu_T[0]);
1438 tcg_gen_shr_tltcg_gen_shr_i32(cpu_T[0], cpu_T[0], t2);
1439 }
1440 } else {
1441 tcg_gen_mov_tltcg_gen_mov_i32(t0, cpu_T[0]);
1442 tcg_gen_shl_tltcg_gen_shl_i32(cpu_T[0], cpu_T[0], t2);
1443 }
1444
1445 /* store */
1446 if (op1 == OR_TMP0) {
1447 gen_op_st_T0_A0(ot + s->mem_index);
1448 } else {
1449 gen_op_mov_reg_T0(ot, op1);
1450 }
1451
1452 /* update eflags if non zero shift */
1453 if (s->cc_op != CC_OP_DYNAMIC) {
1454 gen_op_set_cc_op(s->cc_op);
1455 }
1456
1457 tcg_gen_mov_tltcg_gen_mov_i32(t1, cpu_T[0]);
1458
1459 shift_label = gen_new_label();
1460 tcg_gen_brcondi_tltcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, shift_label);
1461
1462 tcg_gen_addi_tltcg_gen_addi_i32(t2, t2, -1);
1463 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, t1);
1464
1465 if (is_right) {
1466 if (is_arith) {
1467 tcg_gen_sar_tltcg_gen_sar_i32(cpu_cc_src, t0, t2);
1468 } else {
1469 tcg_gen_shr_tltcg_gen_shr_i32(cpu_cc_src, t0, t2);
1470 }
1471 } else {
1472 tcg_gen_shl_tltcg_gen_shl_i32(cpu_cc_src, t0, t2);
1473 }
1474
1475 if (is_right) {
1476 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1477 } else {
1478 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1479 }
1480
1481 gen_set_label(shift_label);
1482 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1483
1484 tcg_temp_freetcg_temp_free_i32(t0);
1485 tcg_temp_freetcg_temp_free_i32(t1);
1486 tcg_temp_freetcg_temp_free_i32(t2);
1487}
1488
1489static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1490 int is_right, int is_arith)
1491{
1492 int mask;
1493
1494 if (ot == OT_QUAD)
1495 mask = 0x3f;
1496 else
1497 mask = 0x1f;
1498
1499 /* load */
1500 if (op1 == OR_TMP0)
1501 gen_op_ld_T0_A0(ot + s->mem_index);
1502 else
1503 gen_op_mov_TN_reg(ot, 0, op1);
1504
1505 op2 &= mask;
1506 if (op2 != 0) {
1507 if (is_right) {
1508 if (is_arith) {
1509 gen_exts(ot, cpu_T[0]);
1510 tcg_gen_sari_tltcg_gen_sari_i32(cpu_tmp4, cpu_T[0], op2 - 1);
1511 tcg_gen_sari_tltcg_gen_sari_i32(cpu_T[0], cpu_T[0], op2);
1512 } else {
1513 gen_extu(ot, cpu_T[0]);
1514 tcg_gen_shri_tltcg_gen_shri_i32(cpu_tmp4, cpu_T[0], op2 - 1);
1515 tcg_gen_shri_tltcg_gen_shri_i32(cpu_T[0], cpu_T[0], op2);
1516 }
1517 } else {
1518 tcg_gen_shli_tltcg_gen_shli_i32(cpu_tmp4, cpu_T[0], op2 - 1);
1519 tcg_gen_shli_tltcg_gen_shli_i32(cpu_T[0], cpu_T[0], op2);
1520 }
1521 }
1522
1523 /* store */
1524 if (op1 == OR_TMP0)
1525 gen_op_st_T0_A0(ot + s->mem_index);
1526 else
1527 gen_op_mov_reg_T0(ot, op1);
1528
1529 /* update eflags if non zero shift */
1530 if (op2 != 0) {
1531 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_src, cpu_tmp4);
1532 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
1533 if (is_right)
1534 s->cc_op = CC_OP_SARB + ot;
1535 else
1536 s->cc_op = CC_OP_SHLB + ot;
1537 }
1538}
1539
1540static inline void tcg_gen_lshift(TCGvTCGv_i32 ret, TCGvTCGv_i32 arg1, target_long arg2)
1541{
1542 if (arg2 >= 0)
1543 tcg_gen_shli_tltcg_gen_shli_i32(ret, arg1, arg2);
1544 else
1545 tcg_gen_shri_tltcg_gen_shri_i32(ret, arg1, -arg2);
1546}
1547
1548static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1549 int is_right)
1550{
1551 target_ulong mask;
1552 int label1, label2, data_bits;
1553 TCGvTCGv_i32 t0, t1, t2, a0;
1554
1555 /* XXX: inefficient, but we must use local temps */
1556 t0 = tcg_temp_local_new()tcg_temp_local_new_i32();
1557 t1 = tcg_temp_local_new()tcg_temp_local_new_i32();
1558 t2 = tcg_temp_local_new()tcg_temp_local_new_i32();
1559 a0 = tcg_temp_local_new()tcg_temp_local_new_i32();
1560
1561 if (ot == OT_QUAD)
1562 mask = 0x3f;
1563 else
1564 mask = 0x1f;
1565
1566 /* load */
1567 if (op1 == OR_TMP0) {
1568 tcg_gen_mov_tltcg_gen_mov_i32(a0, cpu_A0);
1569 gen_op_ld_v(ot + s->mem_index, t0, a0);
1570 } else {
1571 gen_op_mov_v_reg(ot, t0, op1);
1572 }
1573
1574 tcg_gen_mov_tltcg_gen_mov_i32(t1, cpu_T[1]);
1575
1576 tcg_gen_andi_tltcg_gen_andi_i32(t1, t1, mask);
1577
1578 /* Must test zero case to avoid using undefined behaviour in TCG
1579 shifts. */
1580 label1 = gen_new_label();
1581 tcg_gen_brcondi_tltcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, label1);
1582
1583 if (ot <= OT_WORD)
1584 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1585 else
1586 tcg_gen_mov_tltcg_gen_mov_i32(cpu_tmp0, t1);
1587
1588 gen_extu(ot, t0);
1589 tcg_gen_mov_tltcg_gen_mov_i32(t2, t0);
1590
1591 data_bits = 8 << ot;
1592 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1593 fix TCG definition) */
1594 if (is_right) {
1595 tcg_gen_shr_tltcg_gen_shr_i32(cpu_tmp4, t0, cpu_tmp0);
1596 tcg_gen_subfi_tltcg_gen_subfi_i32(cpu_tmp0, data_bits, cpu_tmp0);
1597 tcg_gen_shl_tltcg_gen_shl_i32(t0, t0, cpu_tmp0);
1598 } else {
1599 tcg_gen_shl_tltcg_gen_shl_i32(cpu_tmp4, t0, cpu_tmp0);
1600 tcg_gen_subfi_tltcg_gen_subfi_i32(cpu_tmp0, data_bits, cpu_tmp0);
1601 tcg_gen_shr_tltcg_gen_shr_i32(t0, t0, cpu_tmp0);
1602 }
1603 tcg_gen_or_tltcg_gen_or_i32(t0, t0, cpu_tmp4);
1604
1605 gen_set_label(label1);
1606 /* store */
1607 if (op1 == OR_TMP0) {
1608 gen_op_st_v(ot + s->mem_index, t0, a0);
1609 } else {
1610 gen_op_mov_reg_v(ot, op1, t0);
1611 }
1612
1613 /* update eflags */
1614 if (s->cc_op != CC_OP_DYNAMIC)
1615 gen_op_set_cc_op(s->cc_op);
1616
1617 label2 = gen_new_label();
1618 tcg_gen_brcondi_tltcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, label2);
1619
1620 gen_compute_eflags(cpu_cc_src);
1621 tcg_gen_andi_tltcg_gen_andi_i32(cpu_cc_src, cpu_cc_src, ~(CC_O0x0800 | CC_C0x0001));
1622 tcg_gen_xor_tltcg_gen_xor_i32(cpu_tmp0, t2, t0);
1623 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1624 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp0, cpu_tmp0, CC_O0x0800);
1625 tcg_gen_or_tltcg_gen_or_i32(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1626 if (is_right) {
1627 tcg_gen_shri_tltcg_gen_shri_i32(t0, t0, data_bits - 1);
1628 }
1629 tcg_gen_andi_tltcg_gen_andi_i32(t0, t0, CC_C0x0001);
1630 tcg_gen_or_tltcg_gen_or_i32(cpu_cc_src, cpu_cc_src, t0);
1631
1632 tcg_gen_discard_tltcg_gen_discard_i32(cpu_cc_dst);
1633 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1634
1635 gen_set_label(label2);
1636 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1637
1638 tcg_temp_freetcg_temp_free_i32(t0);
1639 tcg_temp_freetcg_temp_free_i32(t1);
1640 tcg_temp_freetcg_temp_free_i32(t2);
1641 tcg_temp_freetcg_temp_free_i32(a0);
1642}
1643
1644static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1645 int is_right)
1646{
1647 int mask;
1648 int data_bits;
1649 TCGvTCGv_i32 t0, t1, a0;
1650
1651 /* XXX: inefficient, but we must use local temps */
1652 t0 = tcg_temp_local_new()tcg_temp_local_new_i32();
1653 t1 = tcg_temp_local_new()tcg_temp_local_new_i32();
1654 a0 = tcg_temp_local_new()tcg_temp_local_new_i32();
1655
1656 if (ot == OT_QUAD)
1657 mask = 0x3f;
1658 else
1659 mask = 0x1f;
1660
1661 /* load */
1662 if (op1 == OR_TMP0) {
1663 tcg_gen_mov_tltcg_gen_mov_i32(a0, cpu_A0);
1664 gen_op_ld_v(ot + s->mem_index, t0, a0);
1665 } else {
1666 gen_op_mov_v_reg(ot, t0, op1);
1667 }
1668
1669 gen_extu(ot, t0);
1670 tcg_gen_mov_tltcg_gen_mov_i32(t1, t0);
1671
1672 op2 &= mask;
1673 data_bits = 8 << ot;
1674 if (op2 != 0) {
1675 int shift = op2 & ((1 << (3 + ot)) - 1);
1676 if (is_right) {
1677 tcg_gen_shri_tltcg_gen_shri_i32(cpu_tmp4, t0, shift);
1678 tcg_gen_shli_tltcg_gen_shli_i32(t0, t0, data_bits - shift);
1679 }
1680 else {
1681 tcg_gen_shli_tltcg_gen_shli_i32(cpu_tmp4, t0, shift);
1682 tcg_gen_shri_tltcg_gen_shri_i32(t0, t0, data_bits - shift);
1683 }
1684 tcg_gen_or_tltcg_gen_or_i32(t0, t0, cpu_tmp4);
1685 }
1686
1687 /* store */
1688 if (op1 == OR_TMP0) {
1689 gen_op_st_v(ot + s->mem_index, t0, a0);
1690 } else {
1691 gen_op_mov_reg_v(ot, op1, t0);
1692 }
1693
1694 if (op2 != 0) {
1695 /* update eflags */
1696 if (s->cc_op != CC_OP_DYNAMIC)
1697 gen_op_set_cc_op(s->cc_op);
1698
1699 gen_compute_eflags(cpu_cc_src);
1700 tcg_gen_andi_tltcg_gen_andi_i32(cpu_cc_src, cpu_cc_src, ~(CC_O0x0800 | CC_C0x0001));
1701 tcg_gen_xor_tltcg_gen_xor_i32(cpu_tmp0, t1, t0);
1702 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1703 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp0, cpu_tmp0, CC_O0x0800);
1704 tcg_gen_or_tltcg_gen_or_i32(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1705 if (is_right) {
1706 tcg_gen_shri_tltcg_gen_shri_i32(t0, t0, data_bits - 1);
1707 }
1708 tcg_gen_andi_tltcg_gen_andi_i32(t0, t0, CC_C0x0001);
1709 tcg_gen_or_tltcg_gen_or_i32(cpu_cc_src, cpu_cc_src, t0);
1710
1711 tcg_gen_discard_tltcg_gen_discard_i32(cpu_cc_dst);
1712 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1713 s->cc_op = CC_OP_EFLAGS;
1714 }
1715
1716 tcg_temp_freetcg_temp_free_i32(t0);
1717 tcg_temp_freetcg_temp_free_i32(t1);
1718 tcg_temp_freetcg_temp_free_i32(a0);
1719}
1720
1721/* XXX: add faster immediate = 1 case */
1722static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1723 int is_right)
1724{
1725 int label1;
1726
1727 if (s->cc_op != CC_OP_DYNAMIC)
1728 gen_op_set_cc_op(s->cc_op);
1729
1730 /* load */
1731 if (op1 == OR_TMP0)
1732 gen_op_ld_T0_A0(ot + s->mem_index);
1733 else
1734 gen_op_mov_TN_reg(ot, 0, op1);
1735
1736 if (is_right) {
1737 switch (ot) {
1738 case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1739 case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1740 case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1741#ifdef TARGET_X86_64
1742 case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1743#endif
1744 }
1745 } else {
1746 switch (ot) {
1747 case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1748 case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1749 case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1750#ifdef TARGET_X86_64
1751 case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1752#endif
1753 }
1754 }
1755 /* store */
1756 if (op1 == OR_TMP0)
1757 gen_op_st_T0_A0(ot + s->mem_index);
1758 else
1759 gen_op_mov_reg_T0(ot, op1);
1760
1761 /* update eflags */
1762 label1 = gen_new_label();
1763 tcg_gen_brcondi_tltcg_gen_brcondi_i32(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1764
1765 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_src, cpu_cc_tmp);
1766 tcg_gen_discard_tltcg_gen_discard_i32(cpu_cc_dst);
1767 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1768
1769 gen_set_label(label1);
1770 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1771}
1772
1773/* XXX: add faster immediate case */
1774static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1775 int is_right)
1776{
1777 int label1, label2, data_bits;
1778 target_ulong mask;
1779 TCGvTCGv_i32 t0, t1, t2, a0;
1780
1781 t0 = tcg_temp_local_new()tcg_temp_local_new_i32();
1782 t1 = tcg_temp_local_new()tcg_temp_local_new_i32();
1783 t2 = tcg_temp_local_new()tcg_temp_local_new_i32();
1784 a0 = tcg_temp_local_new()tcg_temp_local_new_i32();
1785
1786 if (ot == OT_QUAD)
1787 mask = 0x3f;
1788 else
1789 mask = 0x1f;
1790
1791 /* load */
1792 if (op1 == OR_TMP0) {
1793 tcg_gen_mov_tltcg_gen_mov_i32(a0, cpu_A0);
1794 gen_op_ld_v(ot + s->mem_index, t0, a0);
1795 } else {
1796 gen_op_mov_v_reg(ot, t0, op1);
1797 }
1798
1799 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T3, cpu_T3, mask);
1800
1801 tcg_gen_mov_tltcg_gen_mov_i32(t1, cpu_T[1]);
1802 tcg_gen_mov_tltcg_gen_mov_i32(t2, cpu_T3);
1803
1804 /* Must test zero case to avoid using undefined behaviour in TCG
1805 shifts. */
1806 label1 = gen_new_label();
1807 tcg_gen_brcondi_tltcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, label1);
1808
1809 tcg_gen_addi_tltcg_gen_addi_i32(cpu_tmp5, t2, -1);
1810 if (ot == OT_WORD) {
1811 /* Note: we implement the Intel behaviour for shift count > 16 */
1812 if (is_right) {
1813 tcg_gen_andi_tltcg_gen_andi_i32(t0, t0, 0xffff);
1814 tcg_gen_shli_tltcg_gen_shli_i32(cpu_tmp0, t1, 16);
1815 tcg_gen_or_tltcg_gen_or_i32(t0, t0, cpu_tmp0);
1816 tcg_gen_ext32u_tltcg_gen_mov_i32(t0, t0);
1817
1818 tcg_gen_shr_tltcg_gen_shr_i32(cpu_tmp4, t0, cpu_tmp5);
1819
1820 /* only needed if count > 16, but a test would complicate */
1821 tcg_gen_subfi_tltcg_gen_subfi_i32(cpu_tmp5, 32, t2);
1822 tcg_gen_shl_tltcg_gen_shl_i32(cpu_tmp0, t0, cpu_tmp5);
1823
1824 tcg_gen_shr_tltcg_gen_shr_i32(t0, t0, t2);
1825
1826 tcg_gen_or_tltcg_gen_or_i32(t0, t0, cpu_tmp0);
1827 } else {
1828 /* XXX: not optimal */
1829 tcg_gen_andi_tltcg_gen_andi_i32(t0, t0, 0xffff);
1830 tcg_gen_shli_tltcg_gen_shli_i32(t1, t1, 16);
1831 tcg_gen_or_tltcg_gen_or_i32(t1, t1, t0);
1832 tcg_gen_ext32u_tltcg_gen_mov_i32(t1, t1);
1833
1834 tcg_gen_shl_tltcg_gen_shl_i32(cpu_tmp4, t0, cpu_tmp5);
1835 tcg_gen_subfi_tltcg_gen_subfi_i32(cpu_tmp0, 32, cpu_tmp5);
1836 tcg_gen_shr_tltcg_gen_shr_i32(cpu_tmp5, t1, cpu_tmp0);
1837 tcg_gen_or_tltcg_gen_or_i32(cpu_tmp4, cpu_tmp4, cpu_tmp5);
1838
1839 tcg_gen_shl_tltcg_gen_shl_i32(t0, t0, t2);
1840 tcg_gen_subfi_tltcg_gen_subfi_i32(cpu_tmp5, 32, t2);
1841 tcg_gen_shr_tltcg_gen_shr_i32(t1, t1, cpu_tmp5);
1842 tcg_gen_or_tltcg_gen_or_i32(t0, t0, t1);
1843 }
1844 } else {
1845 data_bits = 8 << ot;
1846 if (is_right) {
1847 if (ot == OT_LONG)
1848 tcg_gen_ext32u_tltcg_gen_mov_i32(t0, t0);
1849
1850 tcg_gen_shr_tltcg_gen_shr_i32(cpu_tmp4, t0, cpu_tmp5);
1851
1852 tcg_gen_shr_tltcg_gen_shr_i32(t0, t0, t2);
1853 tcg_gen_subfi_tltcg_gen_subfi_i32(cpu_tmp5, data_bits, t2);
1854 tcg_gen_shl_tltcg_gen_shl_i32(t1, t1, cpu_tmp5);
1855 tcg_gen_or_tltcg_gen_or_i32(t0, t0, t1);
1856
1857 } else {
1858 if (ot == OT_LONG)
1859 tcg_gen_ext32u_tltcg_gen_mov_i32(t1, t1);
1860
1861 tcg_gen_shl_tltcg_gen_shl_i32(cpu_tmp4, t0, cpu_tmp5);
1862
1863 tcg_gen_shl_tltcg_gen_shl_i32(t0, t0, t2);
1864 tcg_gen_subfi_tltcg_gen_subfi_i32(cpu_tmp5, data_bits, t2);
1865 tcg_gen_shr_tltcg_gen_shr_i32(t1, t1, cpu_tmp5);
1866 tcg_gen_or_tltcg_gen_or_i32(t0, t0, t1);
1867 }
1868 }
1869 tcg_gen_mov_tltcg_gen_mov_i32(t1, cpu_tmp4);
1870
1871 gen_set_label(label1);
1872 /* store */
1873 if (op1 == OR_TMP0) {
1874 gen_op_st_v(ot + s->mem_index, t0, a0);
1875 } else {
1876 gen_op_mov_reg_v(ot, op1, t0);
1877 }
1878
1879 /* update eflags */
1880 if (s->cc_op != CC_OP_DYNAMIC)
1881 gen_op_set_cc_op(s->cc_op);
1882
1883 label2 = gen_new_label();
1884 tcg_gen_brcondi_tltcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, label2);
1885
1886 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_src, t1);
1887 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, t0);
1888 if (is_right) {
1889 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1890 } else {
1891 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1892 }
1893 gen_set_label(label2);
1894 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1895
1896 tcg_temp_freetcg_temp_free_i32(t0);
1897 tcg_temp_freetcg_temp_free_i32(t1);
1898 tcg_temp_freetcg_temp_free_i32(t2);
1899 tcg_temp_freetcg_temp_free_i32(a0);
1900}
1901
1902static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1903{
1904 if (s != OR_TMP1)
1905 gen_op_mov_TN_reg(ot, 1, s);
1906 switch(op) {
1907 case OP_ROL:
1908 gen_rot_rm_T1(s1, ot, d, 0);
1909 break;
1910 case OP_ROR:
1911 gen_rot_rm_T1(s1, ot, d, 1);
1912 break;
1913 case OP_SHL:
1914 case OP_SHL1:
1915 gen_shift_rm_T1(s1, ot, d, 0, 0);
1916 break;
1917 case OP_SHR:
1918 gen_shift_rm_T1(s1, ot, d, 1, 0);
1919 break;
1920 case OP_SAR:
1921 gen_shift_rm_T1(s1, ot, d, 1, 1);
1922 break;
1923 case OP_RCL:
1924 gen_rotc_rm_T1(s1, ot, d, 0);
1925 break;
1926 case OP_RCR:
1927 gen_rotc_rm_T1(s1, ot, d, 1);
1928 break;
1929 }
1930}
1931
1932static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1933{
1934 switch(op) {
1935 case OP_ROL:
1936 gen_rot_rm_im(s1, ot, d, c, 0);
1937 break;
1938 case OP_ROR:
1939 gen_rot_rm_im(s1, ot, d, c, 1);
1940 break;
1941 case OP_SHL:
1942 case OP_SHL1:
1943 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1944 break;
1945 case OP_SHR:
1946 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1947 break;
1948 case OP_SAR:
1949 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1950 break;
1951 default:
1952 /* currently not optimized */
1953 gen_op_movl_T1_im(c);
1954 gen_shift(s1, op, ot, d, OR_TMP1);
1955 break;
1956 }
1957}
1958
1959static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1960{
1961 target_long disp;
1962 int havesib;
1963 int base;
1964 int index;
1965 int scale;
1966 int opreg;
1967 int mod, rm, code, override, must_add_seg;
1968
1969 override = s->override;
1970 must_add_seg = s->addseg;
1971 if (override >= 0)
1972 must_add_seg = 1;
1973 mod = (modrm >> 6) & 3;
1974 rm = modrm & 7;
1975
1976 if (s->aflag) {
1977
1978 havesib = 0;
1979 base = rm;
1980 index = 0;
1981 scale = 0;
1982
1983 if (base == 4) {
1984 havesib = 1;
1985 code = ldub_code(s->pc++);
1986 scale = (code >> 6) & 3;
1987 index = ((code >> 3) & 7) | REX_X(s)0;
1988 base = (code & 7);
1989 }
1990 base |= REX_B(s)0;
1991
1992 switch (mod) {
1993 case 0:
1994 if ((base & 7) == 5) {
1995 base = -1;
1996 disp = (int32_t)ldl_code(s->pc);
1997 s->pc += 4;
1998 if (CODE64(s)0 && !havesib) {
1999 disp += s->pc + s->rip_offset;
2000 }
2001 } else {
2002 disp = 0;
2003 }
2004 break;
2005 case 1:
2006 disp = (int8_t)ldub_code(s->pc++);
2007 break;
2008 default:
2009 case 2:
2010 disp = (int32_t)ldl_code(s->pc);
2011 s->pc += 4;
2012 break;
2013 }
2014
2015 if (base >= 0) {
2016 /* for correct popl handling with esp */
2017 if (base == 4 && s->popl_esp_hack)
2018 disp += s->popl_esp_hack;
2019#ifdef TARGET_X86_64
2020 if (s->aflag == 2) {
2021 gen_op_movq_A0_reg(base);
2022 if (disp != 0) {
2023 gen_op_addq_A0_im(disp);
2024 }
2025 } else
2026#endif
2027 {
2028 gen_op_movl_A0_reg(base);
2029 if (disp != 0)
2030 gen_op_addl_A0_im(disp);
2031 }
2032 } else {
2033#ifdef TARGET_X86_64
2034 if (s->aflag == 2) {
2035 gen_op_movq_A0_im(disp);
2036 } else
2037#endif
2038 {
2039 gen_op_movl_A0_im(disp);
2040 }
2041 }
2042 /* index == 4 means no index */
2043 if (havesib && (index != 4)) {
2044#ifdef TARGET_X86_64
2045 if (s->aflag == 2) {
2046 gen_op_addq_A0_reg_sN(scale, index);
2047 } else
2048#endif
2049 {
2050 gen_op_addl_A0_reg_sN(scale, index);
2051 }
2052 }
2053 if (must_add_seg) {
2054 if (override < 0) {
2055 if (base == R_EBP5 || base == R_ESP4)
2056 override = R_SS2;
2057 else
2058 override = R_DS3;
2059 }
2060#ifdef TARGET_X86_64
2061 if (s->aflag == 2) {
2062 gen_op_addq_A0_seg(override);
2063 } else
2064#endif
2065 {
2066 gen_op_addl_A0_seg(override);
2067 }
2068 }
2069 } else {
2070 switch (mod) {
2071 case 0:
2072 if (rm == 6) {
2073 disp = lduw_code(s->pc);
2074 s->pc += 2;
2075 gen_op_movl_A0_im(disp);
2076 rm = 0; /* avoid SS override */
2077 goto no_rm;
2078 } else {
2079 disp = 0;
2080 }
2081 break;
2082 case 1:
2083 disp = (int8_t)ldub_code(s->pc++);
2084 break;
2085 default:
2086 case 2:
2087 disp = lduw_code(s->pc);
2088 s->pc += 2;
2089 break;
2090 }
2091 switch(rm) {
2092 case 0:
2093 gen_op_movl_A0_reg(R_EBX3);
2094 gen_op_addl_A0_reg_sN(0, R_ESI6);
2095 break;
2096 case 1:
2097 gen_op_movl_A0_reg(R_EBX3);
2098 gen_op_addl_A0_reg_sN(0, R_EDI7);
2099 break;
2100 case 2:
2101 gen_op_movl_A0_reg(R_EBP5);
2102 gen_op_addl_A0_reg_sN(0, R_ESI6);
2103 break;
2104 case 3:
2105 gen_op_movl_A0_reg(R_EBP5);
2106 gen_op_addl_A0_reg_sN(0, R_EDI7);
2107 break;
2108 case 4:
2109 gen_op_movl_A0_reg(R_ESI6);
2110 break;
2111 case 5:
2112 gen_op_movl_A0_reg(R_EDI7);
2113 break;
2114 case 6:
2115 gen_op_movl_A0_reg(R_EBP5);
2116 break;
2117 default:
2118 case 7:
2119 gen_op_movl_A0_reg(R_EBX3);
2120 break;
2121 }
2122 if (disp != 0)
2123 gen_op_addl_A0_im(disp);
2124 gen_op_andl_A0_ffff();
2125 no_rm:
2126 if (must_add_seg) {
2127 if (override < 0) {
2128 if (rm == 2 || rm == 3 || rm == 6)
2129 override = R_SS2;
2130 else
2131 override = R_DS3;
2132 }
2133 gen_op_addl_A0_seg(override);
2134 }
2135 }
2136
2137 opreg = OR_A0;
2138 disp = 0;
2139 *reg_ptr = opreg;
2140 *offset_ptr = disp;
2141}
2142
2143static void gen_nop_modrm(DisasContext *s, int modrm)
2144{
2145 int mod, rm, base, code;
2146
2147 mod = (modrm >> 6) & 3;
2148 if (mod == 3)
2149 return;
2150 rm = modrm & 7;
2151
2152 if (s->aflag) {
2153
2154 base = rm;
2155
2156 if (base == 4) {
2157 code = ldub_code(s->pc++);
2158 base = (code & 7);
2159 }
2160
2161 switch (mod) {
2162 case 0:
2163 if (base == 5) {
2164 s->pc += 4;
2165 }
2166 break;
2167 case 1:
2168 s->pc++;
2169 break;
2170 default:
2171 case 2:
2172 s->pc += 4;
2173 break;
2174 }
2175 } else {
2176 switch (mod) {
2177 case 0:
2178 if (rm == 6) {
2179 s->pc += 2;
2180 }
2181 break;
2182 case 1:
2183 s->pc++;
2184 break;
2185 default:
2186 case 2:
2187 s->pc += 2;
2188 break;
2189 }
2190 }
2191}
2192
2193/* used for LEA and MOV AX, mem */
2194static void gen_add_A0_ds_seg(DisasContext *s)
2195{
2196 int override, must_add_seg;
2197 must_add_seg = s->addseg;
2198 override = R_DS3;
2199 if (s->override >= 0) {
2200 override = s->override;
2201 must_add_seg = 1;
2202 }
2203 if (must_add_seg) {
2204#ifdef TARGET_X86_64
2205 if (CODE64(s)0) {
2206 gen_op_addq_A0_seg(override);
2207 } else
2208#endif
2209 {
2210 gen_op_addl_A0_seg(override);
2211 }
2212 }
2213}
2214
2215/* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2216 OR_TMP0 */
2217static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2218{
2219 int mod, rm, opreg, disp;
2220
2221 mod = (modrm >> 6) & 3;
2222 rm = (modrm & 7) | REX_B(s)0;
2223 if (mod == 3) {
2224 if (is_store) {
2225 if (reg != OR_TMP0)
2226 gen_op_mov_TN_reg(ot, 0, reg);
2227 gen_op_mov_reg_T0(ot, rm);
2228 } else {
2229 gen_op_mov_TN_reg(ot, 0, rm);
2230 if (reg != OR_TMP0)
2231 gen_op_mov_reg_T0(ot, reg);
2232 }
2233 } else {
2234 gen_lea_modrm(s, modrm, &opreg, &disp);
2235 if (is_store) {
2236 if (reg != OR_TMP0)
2237 gen_op_mov_TN_reg(ot, 0, reg);
2238 gen_op_st_T0_A0(ot + s->mem_index);
2239 } else {
2240 gen_op_ld_T0_A0(ot + s->mem_index);
2241 if (reg != OR_TMP0)
2242 gen_op_mov_reg_T0(ot, reg);
2243 }
2244 }
2245}
2246
2247static inline uint32_t insn_get(DisasContext *s, int ot)
2248{
2249 uint32_t ret;
2250
2251 switch(ot) {
2252 case OT_BYTE:
2253 ret = ldub_code(s->pc);
2254 s->pc++;
2255 break;
2256 case OT_WORD:
2257 ret = lduw_code(s->pc);
2258 s->pc += 2;
2259 break;
2260 default:
2261 case OT_LONG:
2262 ret = ldl_code(s->pc);
2263 s->pc += 4;
2264 break;
2265 }
2266 return ret;
2267}
2268
2269static inline int insn_const_size(unsigned int ot)
2270{
2271 if (ot <= OT_LONG)
2272 return 1 << ot;
2273 else
2274 return 4;
2275}
2276
2277static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2278{
2279 TranslationBlock *tb;
2280 target_ulong pc;
2281
2282 pc = s->cs_base + eip;
2283 tb = s->tb;
2284 /* NOTE: we handle the case where the TB spans two pages here */
2285 if ((pc & TARGET_PAGE_MASK~((1 << 12) - 1)) == (tb->pc & TARGET_PAGE_MASK~((1 << 12) - 1)) ||
2286 (pc & TARGET_PAGE_MASK~((1 << 12) - 1)) == ((s->pc - 1) & TARGET_PAGE_MASK~((1 << 12) - 1))) {
2287 /* jump to same page: we can use a direct jump */
2288 tcg_gen_goto_tb(tb_num);
2289 gen_jmp_im(eip);
2290 tcg_gen_exit_tb((tcg_target_long)tb + tb_num);
2291 } else {
2292 /* jump to another page: currently not optimized */
2293 gen_jmp_im(eip);
2294 gen_eob(s);
2295 }
2296}
2297
2298static inline void gen_jcc(DisasContext *s, int b,
2299 target_ulong val, target_ulong next_eip)
2300{
2301 int l1, l2, cc_op;
2302
2303 cc_op = s->cc_op;
2304 gen_update_cc_op(s);
2305 if (s->jmp_opt) {
2306 l1 = gen_new_label();
2307 gen_jcc1(s, cc_op, b, l1);
2308
2309 gen_goto_tb(s, 0, next_eip);
2310
2311 gen_set_label(l1);
2312 gen_goto_tb(s, 1, val);
2313 s->is_jmp = DISAS_TB_JUMP3;
2314 } else {
2315
2316 l1 = gen_new_label();
2317 l2 = gen_new_label();
2318 gen_jcc1(s, cc_op, b, l1);
2319
2320 gen_jmp_im(next_eip);
2321 tcg_gen_br(l2);
2322
2323 gen_set_label(l1);
2324 gen_jmp_im(val);
2325 gen_set_label(l2);
2326 gen_eob(s);
2327 }
2328}
2329
2330static void gen_setcc(DisasContext *s, int b)
2331{
2332 int inv, jcc_op, l1;
2333 TCGvTCGv_i32 t0;
2334
2335 if (is_fast_jcc_case(s, b)) {
2336 /* nominal case: we use a jump */
2337 /* XXX: make it faster by adding new instructions in TCG */
2338 t0 = tcg_temp_local_new()tcg_temp_local_new_i32();
2339 tcg_gen_movi_tltcg_gen_movi_i32(t0, 0);
2340 l1 = gen_new_label();
2341 gen_jcc1(s, s->cc_op, b ^ 1, l1);
2342 tcg_gen_movi_tltcg_gen_movi_i32(t0, 1);
2343 gen_set_label(l1);
2344 tcg_gen_mov_tltcg_gen_mov_i32(cpu_T[0], t0);
2345 tcg_temp_freetcg_temp_free_i32(t0);
2346 } else {
2347 /* slow case: it is more efficient not to generate a jump,
2348 although it is questionnable whether this optimization is
2349 worth to */
2350 inv = b & 1;
2351 jcc_op = (b >> 1) & 7;
2352 gen_setcc_slow_T0(s, jcc_op);
2353 if (inv) {
2354 tcg_gen_xori_tltcg_gen_xori_i32(cpu_T[0], cpu_T[0], 1);
2355 }
2356 }
2357}
2358
2359static inline void gen_op_movl_T0_seg(int seg_reg)
2360{
2361 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_T[0], cpu_env,
2362 offsetof(CPUX86State,segs[seg_reg].selector)__builtin_offsetof(CPUX86State, segs[seg_reg].selector));
2363}
2364
2365static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2366{
2367 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
2368 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[0], cpu_env,
2369 offsetof(CPUX86State,segs[seg_reg].selector)__builtin_offsetof(CPUX86State, segs[seg_reg].selector));
2370 tcg_gen_shli_tltcg_gen_shli_i32(cpu_T[0], cpu_T[0], 4);
2371 tcg_gen_st_tltcg_gen_st_i32(cpu_T[0], cpu_env,
2372 offsetof(CPUX86State,segs[seg_reg].base)__builtin_offsetof(CPUX86State, segs[seg_reg].base));
2373}
2374
2375/* move T0 to seg_reg and compute if the CPU state may change. Never
2376 call this function with seg_reg == R_CS */
2377static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2378{
2379 if (s->pe && !s->vm86) {
2380 /* XXX: optimize by finding processor state dynamically */
2381 if (s->cc_op != CC_OP_DYNAMIC)
2382 gen_op_set_cc_op(s->cc_op);
2383 gen_jmp_im(cur_eip);
2384 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
2385 gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32);
2386 /* abort translation because the addseg value may change or
2387 because ss32 may change. For R_SS, translation must always
2388 stop as a special handling must be done to disable hardware
2389 interrupts for the next instruction */
2390 if (seg_reg == R_SS2 || (s->code32 && seg_reg < R_FS4))
2391 s->is_jmp = DISAS_TB_JUMP3;
2392 } else {
2393 gen_op_movl_seg_T0_vm(seg_reg);
2394 if (seg_reg == R_SS2)
2395 s->is_jmp = DISAS_TB_JUMP3;
2396 }
2397}
2398
2399static inline int svm_is_rep(int prefixes)
2400{
2401 return ((prefixes & (PREFIX_REPZ0x01 | PREFIX_REPNZ0x02)) ? 8 : 0);
2402}
2403
2404static inline void
2405gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2406 uint32_t type, uint64_t param)
2407{
2408 /* no SVM activated; fast case */
2409 if (likely(!(s->flags & HF_SVMI_MASK))__builtin_expect(!!(!(s->flags & (1 << 21))), 1))
2410 return;
2411 if (s->cc_op != CC_OP_DYNAMIC)
2412 gen_op_set_cc_op(s->cc_op);
2413 gen_jmp_im(pc_start - s->cs_base);
2414 gen_helper_svm_check_intercept_param(tcg_const_i32(type),
2415 tcg_const_i64(param));
2416}
2417
2418static inline void
2419gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2420{
2421 gen_svm_check_intercept_param(s, pc_start, type, 0);
2422}
2423
2424static inline void gen_stack_update(DisasContext *s, int addend)
2425{
2426#ifdef TARGET_X86_64
2427 if (CODE64(s)0) {
2428 gen_op_add_reg_im(2, R_ESP4, addend);
2429 } else
2430#endif
2431 if (s->ss32) {
2432 gen_op_add_reg_im(1, R_ESP4, addend);
2433 } else {
2434 gen_op_add_reg_im(0, R_ESP4, addend);
2435 }
2436}
2437
2438/* generate a push. It depends on ss32, addseg and dflag */
2439static void gen_push_T0(DisasContext *s)
2440{
2441#ifdef TARGET_X86_64
2442 if (CODE64(s)0) {
2443 gen_op_movq_A0_reg(R_ESP4);
2444 if (s->dflag) {
2445 gen_op_addq_A0_im(-8);
2446 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2447 } else {
2448 gen_op_addq_A0_im(-2);
2449 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2450 }
2451 gen_op_mov_reg_A0(2, R_ESP4);
2452 } else
2453#endif
2454 {
2455 gen_op_movl_A0_reg(R_ESP4);
2456 if (!s->dflag)
2457 gen_op_addl_A0_im(-2);
2458 else
2459 gen_op_addl_A0_im(-4);
2460 if (s->ss32) {
2461 if (s->addseg) {
2462 tcg_gen_mov_tltcg_gen_mov_i32(cpu_T[1], cpu_A0);
2463 gen_op_addl_A0_seg(R_SS2);
2464 }
2465 } else {
2466 gen_op_andl_A0_ffff();
2467 tcg_gen_mov_tltcg_gen_mov_i32(cpu_T[1], cpu_A0);
2468 gen_op_addl_A0_seg(R_SS2);
2469 }
2470 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2471 if (s->ss32 && !s->addseg)
2472 gen_op_mov_reg_A0(1, R_ESP4);
2473 else
2474 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP4);
2475 }
2476}
2477
2478/* generate a push. It depends on ss32, addseg and dflag */
2479/* slower version for T1, only used for call Ev */
2480static void gen_push_T1(DisasContext *s)
2481{
2482#ifdef TARGET_X86_64
2483 if (CODE64(s)0) {
2484 gen_op_movq_A0_reg(R_ESP4);
2485 if (s->dflag) {
2486 gen_op_addq_A0_im(-8);
2487 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2488 } else {
2489 gen_op_addq_A0_im(-2);
2490 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2491 }
2492 gen_op_mov_reg_A0(2, R_ESP4);
2493 } else
2494#endif
2495 {
2496 gen_op_movl_A0_reg(R_ESP4);
2497 if (!s->dflag)
2498 gen_op_addl_A0_im(-2);
2499 else
2500 gen_op_addl_A0_im(-4);
2501 if (s->ss32) {
2502 if (s->addseg) {
2503 gen_op_addl_A0_seg(R_SS2);
2504 }
2505 } else {
2506 gen_op_andl_A0_ffff();
2507 gen_op_addl_A0_seg(R_SS2);
2508 }
2509 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2510
2511 if (s->ss32 && !s->addseg)
2512 gen_op_mov_reg_A0(1, R_ESP4);
2513 else
2514 gen_stack_update(s, (-2) << s->dflag);
2515 }
2516}
2517
2518/* two step pop is necessary for precise exceptions */
2519static void gen_pop_T0(DisasContext *s)
2520{
2521#ifdef TARGET_X86_64
2522 if (CODE64(s)0) {
2523 gen_op_movq_A0_reg(R_ESP4);
2524 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2525 } else
2526#endif
2527 {
2528 gen_op_movl_A0_reg(R_ESP4);
2529 if (s->ss32) {
2530 if (s->addseg)
2531 gen_op_addl_A0_seg(R_SS2);
2532 } else {
2533 gen_op_andl_A0_ffff();
2534 gen_op_addl_A0_seg(R_SS2);
2535 }
2536 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2537 }
2538}
2539
2540static void gen_pop_update(DisasContext *s)
2541{
2542#ifdef TARGET_X86_64
2543 if (CODE64(s)0 && s->dflag) {
2544 gen_stack_update(s, 8);
2545 } else
2546#endif
2547 {
2548 gen_stack_update(s, 2 << s->dflag);
2549 }
2550}
2551
2552static void gen_stack_A0(DisasContext *s)
2553{
2554 gen_op_movl_A0_reg(R_ESP4);
2555 if (!s->ss32)
2556 gen_op_andl_A0_ffff();
2557 tcg_gen_mov_tltcg_gen_mov_i32(cpu_T[1], cpu_A0);
2558 if (s->addseg)
2559 gen_op_addl_A0_seg(R_SS2);
2560}
2561
2562/* NOTE: wrap around in 16 bit not fully handled */
2563static void gen_pusha(DisasContext *s)
2564{
2565 int i;
2566 gen_op_movl_A0_reg(R_ESP4);
2567 gen_op_addl_A0_im(-16 << s->dflag);
2568 if (!s->ss32)
2569 gen_op_andl_A0_ffff();
2570 tcg_gen_mov_tltcg_gen_mov_i32(cpu_T[1], cpu_A0);
2571 if (s->addseg)
2572 gen_op_addl_A0_seg(R_SS2);
2573 for(i = 0;i < 8; i++) {
2574 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2575 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2576 gen_op_addl_A0_im(2 << s->dflag);
2577 }
2578 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP4);
2579}
2580
2581/* NOTE: wrap around in 16 bit not fully handled */
2582static void gen_popa(DisasContext *s)
2583{
2584 int i;
2585 gen_op_movl_A0_reg(R_ESP4);
2586 if (!s->ss32)
2587 gen_op_andl_A0_ffff();
2588 tcg_gen_mov_tltcg_gen_mov_i32(cpu_T[1], cpu_A0);
2589 tcg_gen_addi_tltcg_gen_addi_i32(cpu_T[1], cpu_T[1], 16 << s->dflag);
2590 if (s->addseg)
2591 gen_op_addl_A0_seg(R_SS2);
2592 for(i = 0;i < 8; i++) {
2593 /* ESP is not reloaded */
2594 if (i != 3) {
2595 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2596 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2597 }
2598 gen_op_addl_A0_im(2 << s->dflag);
2599 }
2600 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP4);
2601}
2602
2603static void gen_enter(DisasContext *s, int esp_addend, int level)
2604{
2605 int ot, opsize;
2606
2607 level &= 0x1f;
2608#ifdef TARGET_X86_64
2609 if (CODE64(s)0) {
2610 ot = s->dflag ? OT_QUAD : OT_WORD;
2611 opsize = 1 << ot;
2612
2613 gen_op_movl_A0_reg(R_ESP4);
2614 gen_op_addq_A0_im(-opsize);
2615 tcg_gen_mov_tltcg_gen_mov_i32(cpu_T[1], cpu_A0);
2616
2617 /* push bp */
2618 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP5);
2619 gen_op_st_T0_A0(ot + s->mem_index);
2620 if (level) {
2621 /* XXX: must save state */
2622 gen_helper_enter64_level(tcg_const_i32(level),
2623 tcg_const_i32((ot == OT_QUAD)),
2624 cpu_T[1]);
2625 }
2626 gen_op_mov_reg_T1(ot, R_EBP5);
2627 tcg_gen_addi_tltcg_gen_addi_i32(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2628 gen_op_mov_reg_T1(OT_QUAD, R_ESP4);
2629 } else
2630#endif
2631 {
2632 ot = s->dflag + OT_WORD;
2633 opsize = 2 << s->dflag;
2634
2635 gen_op_movl_A0_reg(R_ESP4);
2636 gen_op_addl_A0_im(-opsize);
2637 if (!s->ss32)
2638 gen_op_andl_A0_ffff();
2639 tcg_gen_mov_tltcg_gen_mov_i32(cpu_T[1], cpu_A0);
2640 if (s->addseg)
2641 gen_op_addl_A0_seg(R_SS2);
2642 /* push bp */
2643 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP5);
2644 gen_op_st_T0_A0(ot + s->mem_index);
2645 if (level) {
2646 /* XXX: must save state */
2647 gen_helper_enter_level(tcg_const_i32(level),
2648 tcg_const_i32(s->dflag),
2649 cpu_T[1]);
2650 }
2651 gen_op_mov_reg_T1(ot, R_EBP5);
2652 tcg_gen_addi_tltcg_gen_addi_i32(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2653 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP4);
2654 }
2655}
2656
2657static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2658{
2659 if (s->cc_op != CC_OP_DYNAMIC)
2660 gen_op_set_cc_op(s->cc_op);
2661 gen_jmp_im(cur_eip);
2662 gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));
2663 s->is_jmp = DISAS_TB_JUMP3;
2664}
2665
2666/* an interrupt is different from an exception because of the
2667 privilege checks */
2668static void gen_interrupt(DisasContext *s, int intno,
2669 target_ulong cur_eip, target_ulong next_eip)
2670{
2671 if (s->cc_op != CC_OP_DYNAMIC)
2672 gen_op_set_cc_op(s->cc_op);
2673 gen_jmp_im(cur_eip);
2674 gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno),
2675 tcg_const_i32(next_eip - cur_eip));
2676 s->is_jmp = DISAS_TB_JUMP3;
2677}
2678
2679static void gen_debug(DisasContext *s, target_ulong cur_eip)
2680{
2681 if (s->cc_op != CC_OP_DYNAMIC)
2682 gen_op_set_cc_op(s->cc_op);
2683 gen_jmp_im(cur_eip);
2684 gen_helper_debug();
2685 s->is_jmp = DISAS_TB_JUMP3;
2686}
2687
2688/* generate a generic end of block. Trace exception is also generated
2689 if needed */
2690static void gen_eob(DisasContext *s)
2691{
2692 if (s->cc_op != CC_OP_DYNAMIC)
2693 gen_op_set_cc_op(s->cc_op);
2694 if (s->tb->flags & HF_INHIBIT_IRQ_MASK(1 << 3)) {
2695 gen_helper_reset_inhibit_irq();
2696 }
2697 if (s->tb->flags & HF_RF_MASK(1 << 16)) {
2698 gen_helper_reset_rf();
2699 }
2700 if (s->singlestep_enabled) {
2701 gen_helper_debug();
2702 } else if (s->tf) {
2703 gen_helper_single_step();
2704 } else {
2705 tcg_gen_exit_tb(0);
2706 }
2707 s->is_jmp = DISAS_TB_JUMP3;
2708}
2709
2710/* generate a jump to eip. No segment change must happen before as a
2711 direct call to the next block may occur */
2712static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2713{
2714 if (s->jmp_opt) {
2715 gen_update_cc_op(s);
2716 gen_goto_tb(s, tb_num, eip);
2717 s->is_jmp = DISAS_TB_JUMP3;
2718 } else {
2719 gen_jmp_im(eip);
2720 gen_eob(s);
2721 }
2722}
2723
2724static void gen_jmp(DisasContext *s, target_ulong eip)
2725{
2726 gen_jmp_tb(s, eip, 0);
2727}
2728
2729static inline void gen_ldq_env_A0(int idx, int offset)
2730{
2731 int mem_index = (idx >> 2) - 1;
2732 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2733 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2734}
2735
2736static inline void gen_stq_env_A0(int idx, int offset)
2737{
2738 int mem_index = (idx >> 2) - 1;
2739 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2740 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2741}
2742
2743static inline void gen_ldo_env_A0(int idx, int offset)
2744{
2745 int mem_index = (idx >> 2) - 1;
2746 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2747 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))__builtin_offsetof(XMMReg, _q[0]));
2748 tcg_gen_addi_tltcg_gen_addi_i32(cpu_tmp0, cpu_A0, 8);
2749 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2750 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))__builtin_offsetof(XMMReg, _q[1]));
2751}
2752
2753static inline void gen_sto_env_A0(int idx, int offset)
2754{
2755 int mem_index = (idx >> 2) - 1;
2756 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))__builtin_offsetof(XMMReg, _q[0]));
2757 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2758 tcg_gen_addi_tltcg_gen_addi_i32(cpu_tmp0, cpu_A0, 8);
2759 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))__builtin_offsetof(XMMReg, _q[1]));
2760 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2761}
2762
2763static inline void gen_op_movo(int d_offset, int s_offset)
2764{
2765 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2766 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2767 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2768 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2769}
2770
2771static inline void gen_op_movq(int d_offset, int s_offset)
2772{
2773 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2774 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2775}
2776
2777static inline void gen_op_movl(int d_offset, int s_offset)
2778{
2779 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2780 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2781}
2782
2783static inline void gen_op_movq_env_0(int d_offset)
2784{
2785 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2786 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2787}
2788
2789typedef void (*SSEFunc_i_p)(TCGv_i32 val, TCGv_ptr reg);
2790typedef void (*SSEFunc_l_p)(TCGv_i64 val, TCGv_ptr reg);
2791typedef void (*SSEFunc_0_pi)(TCGv_ptr reg, TCGv_i32 val);
2792typedef void (*SSEFunc_0_pl)(TCGv_ptr reg, TCGv_i64 val);
2793typedef void (*SSEFunc_0_pp)(TCGv_ptr reg_a, TCGv_ptr reg_b);
2794typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val);
2795typedef void (*SSEFunc_0_ppt)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGvTCGv_i32 val);
2796
2797#define SSE_SPECIAL((void *)1) ((void *)1)
2798#define SSE_DUMMY((void *)2) ((void *)2)
2799
2800#define MMX_OP2(x){ gen_helper_x_mmx, gen_helper_x_xmm } { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2801#define SSE_FOP(x){ gen_helper_xps, gen_helper_xpd, gen_helper_xss, gen_helper_xsd
, } { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2802 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2803
2804static const SSEFunc_0_pp sse_op_table1[256][4] = {
2805 /* 3DNow! extensions */
2806 [0x0e] = { SSE_DUMMY((void *)2) }, /* femms */
2807 [0x0f] = { SSE_DUMMY((void *)2) }, /* pf... */
2808 /* pure SSE operations */
2809 [0x10] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movups, movupd, movss, movsd */
2810 [0x11] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movups, movupd, movss, movsd */
2811 [0x12] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movlps, movlpd, movsldup, movddup */
2812 [0x13] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movlps, movlpd */
2813 [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2814 [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
2815 [0x16] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movhps, movhpd, movshdup */
2816 [0x17] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movhps, movhpd */
2817
2818 [0x28] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movaps, movapd */
2819 [0x29] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movaps, movapd */
2820 [0x2a] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2821 [0x2b] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movntps, movntpd, movntss, movntsd */
2822 [0x2c] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2823 [0x2d] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2824 [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2825 [0x2f] = { gen_helper_comiss, gen_helper_comisd },
2826 [0x50] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movmskps, movmskpd */
2827 [0x51] = SSE_FOP(sqrt){ gen_helper_sqrtps, gen_helper_sqrtpd, gen_helper_sqrtss, gen_helper_sqrtsd
, },
2828 [0x52] = { gen_helper_rsqrtps, NULL((void*)0), gen_helper_rsqrtss, NULL((void*)0) },
2829 [0x53] = { gen_helper_rcpps, NULL((void*)0), gen_helper_rcpss, NULL((void*)0) },
2830 [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2831 [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2832 [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2833 [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
2834 [0x58] = SSE_FOP(add){ gen_helper_addps, gen_helper_addpd, gen_helper_addss, gen_helper_addsd
, },
2835 [0x59] = SSE_FOP(mul){ gen_helper_mulps, gen_helper_mulpd, gen_helper_mulss, gen_helper_mulsd
, },
2836 [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2837 gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2838 [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
2839 [0x5c] = SSE_FOP(sub){ gen_helper_subps, gen_helper_subpd, gen_helper_subss, gen_helper_subsd
, },
2840 [0x5d] = SSE_FOP(min){ gen_helper_minps, gen_helper_minpd, gen_helper_minss, gen_helper_minsd
, },
2841 [0x5e] = SSE_FOP(div){ gen_helper_divps, gen_helper_divpd, gen_helper_divss, gen_helper_divsd
, },
2842 [0x5f] = SSE_FOP(max){ gen_helper_maxps, gen_helper_maxpd, gen_helper_maxss, gen_helper_maxsd
, },
2843
2844 [0xc2] = SSE_FOP(cmpeq){ gen_helper_cmpeqps, gen_helper_cmpeqpd, gen_helper_cmpeqss,
gen_helper_cmpeqsd, },
2845 [0xc6] = { (SSEFunc_0_pp)gen_helper_shufps,
2846 (SSEFunc_0_pp)gen_helper_shufpd }, /* XXX: casts */
2847
2848 [0x38] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), NULL((void*)0), SSE_SPECIAL((void *)1) }, /* SSSE3/SSE4 */
2849 [0x3a] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* SSSE3/SSE4 */
2850
2851 /* MMX ops and their SSE extensions */
2852 [0x60] = MMX_OP2(punpcklbw){ gen_helper_punpcklbw_mmx, gen_helper_punpcklbw_xmm },
2853 [0x61] = MMX_OP2(punpcklwd){ gen_helper_punpcklwd_mmx, gen_helper_punpcklwd_xmm },
2854 [0x62] = MMX_OP2(punpckldq){ gen_helper_punpckldq_mmx, gen_helper_punpckldq_xmm },
2855 [0x63] = MMX_OP2(packsswb){ gen_helper_packsswb_mmx, gen_helper_packsswb_xmm },
2856 [0x64] = MMX_OP2(pcmpgtb){ gen_helper_pcmpgtb_mmx, gen_helper_pcmpgtb_xmm },
2857 [0x65] = MMX_OP2(pcmpgtw){ gen_helper_pcmpgtw_mmx, gen_helper_pcmpgtw_xmm },
2858 [0x66] = MMX_OP2(pcmpgtl){ gen_helper_pcmpgtl_mmx, gen_helper_pcmpgtl_xmm },
2859 [0x67] = MMX_OP2(packuswb){ gen_helper_packuswb_mmx, gen_helper_packuswb_xmm },
2860 [0x68] = MMX_OP2(punpckhbw){ gen_helper_punpckhbw_mmx, gen_helper_punpckhbw_xmm },
2861 [0x69] = MMX_OP2(punpckhwd){ gen_helper_punpckhwd_mmx, gen_helper_punpckhwd_xmm },
2862 [0x6a] = MMX_OP2(punpckhdq){ gen_helper_punpckhdq_mmx, gen_helper_punpckhdq_xmm },
2863 [0x6b] = MMX_OP2(packssdw){ gen_helper_packssdw_mmx, gen_helper_packssdw_xmm },
2864 [0x6c] = { NULL((void*)0), gen_helper_punpcklqdq_xmm },
2865 [0x6d] = { NULL((void*)0), gen_helper_punpckhqdq_xmm },
2866 [0x6e] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movd mm, ea */
2867 [0x6f] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movq, movdqa, , movqdu */
2868 [0x70] = { (SSEFunc_0_pp)gen_helper_pshufw_mmx,
2869 (SSEFunc_0_pp)gen_helper_pshufd_xmm,
2870 (SSEFunc_0_pp)gen_helper_pshufhw_xmm,
2871 (SSEFunc_0_pp)gen_helper_pshuflw_xmm }, /* XXX: casts */
2872 [0x71] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* shiftw */
2873 [0x72] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* shiftd */
2874 [0x73] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* shiftq */
2875 [0x74] = MMX_OP2(pcmpeqb){ gen_helper_pcmpeqb_mmx, gen_helper_pcmpeqb_xmm },
2876 [0x75] = MMX_OP2(pcmpeqw){ gen_helper_pcmpeqw_mmx, gen_helper_pcmpeqw_xmm },
2877 [0x76] = MMX_OP2(pcmpeql){ gen_helper_pcmpeql_mmx, gen_helper_pcmpeql_xmm },
2878 [0x77] = { SSE_DUMMY((void *)2) }, /* emms */
2879 [0x78] = { NULL((void*)0), SSE_SPECIAL((void *)1), NULL((void*)0), SSE_SPECIAL((void *)1) }, /* extrq_i, insertq_i */
2880 [0x79] = { NULL((void*)0), gen_helper_extrq_r, NULL((void*)0), gen_helper_insertq_r },
2881 [0x7c] = { NULL((void*)0), gen_helper_haddpd, NULL((void*)0), gen_helper_haddps },
2882 [0x7d] = { NULL((void*)0), gen_helper_hsubpd, NULL((void*)0), gen_helper_hsubps },
2883 [0x7e] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movd, movd, , movq */
2884 [0x7f] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* movq, movdqa, movdqu */
2885 [0xc4] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* pinsrw */
2886 [0xc5] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* pextrw */
2887 [0xd0] = { NULL((void*)0), gen_helper_addsubpd, NULL((void*)0), gen_helper_addsubps },
2888 [0xd1] = MMX_OP2(psrlw){ gen_helper_psrlw_mmx, gen_helper_psrlw_xmm },
2889 [0xd2] = MMX_OP2(psrld){ gen_helper_psrld_mmx, gen_helper_psrld_xmm },
2890 [0xd3] = MMX_OP2(psrlq){ gen_helper_psrlq_mmx, gen_helper_psrlq_xmm },
2891 [0xd4] = MMX_OP2(paddq){ gen_helper_paddq_mmx, gen_helper_paddq_xmm },
2892 [0xd5] = MMX_OP2(pmullw){ gen_helper_pmullw_mmx, gen_helper_pmullw_xmm },
2893 [0xd6] = { NULL((void*)0), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) },
2894 [0xd7] = { SSE_SPECIAL((void *)1), SSE_SPECIAL((void *)1) }, /* pmovmskb */
2895 [0xd8] = MMX_OP2(psubusb){ gen_helper_psubusb_mmx, gen_helper_psubusb_xmm },
2896 [0xd9] = MMX_OP2(psubusw){ gen_helper_psubusw_mmx, gen_helper_psubusw_xmm },
2897 [0xda] = MMX_OP2(pminub){ gen_helper_pminub_mmx, gen_helper_pminub_xmm },
2898 [0xdb] = MMX_OP2(pand){ gen_helper_pand_mmx, gen_helper_pand_xmm },
2899 [0xdc] = MMX_OP2(paddusb){ gen_helper_paddusb_mmx, gen_helper_paddusb_xmm },
2900 [0xdd] = MMX_OP2(paddusw){ gen_helper_paddusw_mmx, gen_helper_paddusw_xmm },
2901 [0xde] = MMX_OP2(pmaxub){ gen_helper_pmaxub_mmx, gen_helper_pmaxub_xmm },
2902 [0xdf] = MMX_OP2(pandn){ gen_helper_pandn_mmx, gen_helper_pandn_xmm },
2903 [0xe0] = MMX_OP2(pavgb){ gen_helper_pavgb_mmx, gen_helper_pavgb_xmm },
2904 [0xe1] = MMX_OP2(psraw){ gen_helper_psraw_mmx, gen_helper_psraw_xmm },
2905 [0xe2] = MMX_OP2(psrad){ gen_helper_psrad_mmx, gen_helper_psrad_xmm },
2906 [0xe3] = MMX_OP2(pavgw){ gen_helper_pavgw_mmx, gen_helper_pavgw_xmm },
2907 [0xe4] = MMX_OP2(pmulhuw){ gen_helper_pmulhuw_mmx, gen_helper_pmulhuw_xmm },
2908 [0xe5] = MMX_OP2(pmulhw){ gen_helper_pmulhw_mmx, gen_helper_pmulhw_xmm },
2909 [0xe6] = { NULL((void*)0), gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
2910 [0xe7] = { SSE_SPECIAL((void *)1) , SSE_SPECIAL((void *)1) }, /* movntq, movntq */
2911 [0xe8] = MMX_OP2(psubsb){ gen_helper_psubsb_mmx, gen_helper_psubsb_xmm },
2912 [0xe9] = MMX_OP2(psubsw){ gen_helper_psubsw_mmx, gen_helper_psubsw_xmm },
2913 [0xea] = MMX_OP2(pminsw){ gen_helper_pminsw_mmx, gen_helper_pminsw_xmm },
2914 [0xeb] = MMX_OP2(por){ gen_helper_por_mmx, gen_helper_por_xmm },
2915 [0xec] = MMX_OP2(paddsb){ gen_helper_paddsb_mmx, gen_helper_paddsb_xmm },
2916 [0xed] = MMX_OP2(paddsw){ gen_helper_paddsw_mmx, gen_helper_paddsw_xmm },
2917 [0xee] = MMX_OP2(pmaxsw){ gen_helper_pmaxsw_mmx, gen_helper_pmaxsw_xmm },
2918 [0xef] = MMX_OP2(pxor){ gen_helper_pxor_mmx, gen_helper_pxor_xmm },
2919 [0xf0] = { NULL((void*)0), NULL((void*)0), NULL((void*)0), SSE_SPECIAL((void *)1) }, /* lddqu */
2920 [0xf1] = MMX_OP2(psllw){ gen_helper_psllw_mmx, gen_helper_psllw_xmm },
2921 [0xf2] = MMX_OP2(pslld){ gen_helper_pslld_mmx, gen_helper_pslld_xmm },
2922 [0xf3] = MMX_OP2(psllq){ gen_helper_psllq_mmx, gen_helper_psllq_xmm },
2923 [0xf4] = MMX_OP2(pmuludq){ gen_helper_pmuludq_mmx, gen_helper_pmuludq_xmm },
2924 [0xf5] = MMX_OP2(pmaddwd){ gen_helper_pmaddwd_mmx, gen_helper_pmaddwd_xmm },
2925 [0xf6] = MMX_OP2(psadbw){ gen_helper_psadbw_mmx, gen_helper_psadbw_xmm },
2926 [0xf7] = { (SSEFunc_0_pp)gen_helper_maskmov_mmx,
2927 (SSEFunc_0_pp)gen_helper_maskmov_xmm }, /* XXX: casts */
2928 [0xf8] = MMX_OP2(psubb){ gen_helper_psubb_mmx, gen_helper_psubb_xmm },
2929 [0xf9] = MMX_OP2(psubw){ gen_helper_psubw_mmx, gen_helper_psubw_xmm },
2930 [0xfa] = MMX_OP2(psubl){ gen_helper_psubl_mmx, gen_helper_psubl_xmm },
2931 [0xfb] = MMX_OP2(psubq){ gen_helper_psubq_mmx, gen_helper_psubq_xmm },
2932 [0xfc] = MMX_OP2(paddb){ gen_helper_paddb_mmx, gen_helper_paddb_xmm },
2933 [0xfd] = MMX_OP2(paddw){ gen_helper_paddw_mmx, gen_helper_paddw_xmm },
2934 [0xfe] = MMX_OP2(paddl){ gen_helper_paddl_mmx, gen_helper_paddl_xmm },
2935};
2936
2937static const SSEFunc_0_pp sse_op_table2[3 * 8][2] = {
2938 [0 + 2] = MMX_OP2(psrlw){ gen_helper_psrlw_mmx, gen_helper_psrlw_xmm },
2939 [0 + 4] = MMX_OP2(psraw){ gen_helper_psraw_mmx, gen_helper_psraw_xmm },
2940 [0 + 6] = MMX_OP2(psllw){ gen_helper_psllw_mmx, gen_helper_psllw_xmm },
2941 [8 + 2] = MMX_OP2(psrld){ gen_helper_psrld_mmx, gen_helper_psrld_xmm },
2942 [8 + 4] = MMX_OP2(psrad){ gen_helper_psrad_mmx, gen_helper_psrad_xmm },
2943 [8 + 6] = MMX_OP2(pslld){ gen_helper_pslld_mmx, gen_helper_pslld_xmm },
2944 [16 + 2] = MMX_OP2(psrlq){ gen_helper_psrlq_mmx, gen_helper_psrlq_xmm },
2945 [16 + 3] = { NULL((void*)0), gen_helper_psrldq_xmm },
2946 [16 + 6] = MMX_OP2(psllq){ gen_helper_psllq_mmx, gen_helper_psllq_xmm },
2947 [16 + 7] = { NULL((void*)0), gen_helper_pslldq_xmm },
2948};
2949
2950static const SSEFunc_0_pi sse_op_table3ai[] = {
2951 gen_helper_cvtsi2ss,
2952 gen_helper_cvtsi2sd
2953};
2954
2955#ifdef TARGET_X86_64
2956static const SSEFunc_0_pl sse_op_table3aq[] = {
2957 gen_helper_cvtsq2ss,
2958 gen_helper_cvtsq2sd
2959};
2960#endif
2961
2962static const SSEFunc_i_p sse_op_table3bi[] = {
2963 gen_helper_cvttss2si,
2964 gen_helper_cvttsd2si,
2965 gen_helper_cvtss2si,
2966 gen_helper_cvtsd2si
2967};
2968
2969#ifdef TARGET_X86_64
2970static const SSEFunc_l_p sse_op_table3bq[] = {
2971 gen_helper_cvttss2sq,
2972 gen_helper_cvttsd2sq,
2973 gen_helper_cvtss2sq,
2974 gen_helper_cvtsd2sq
2975};
2976#endif
2977
2978static const SSEFunc_0_pp sse_op_table4[8][4] = {
2979 SSE_FOP(cmpeq){ gen_helper_cmpeqps, gen_helper_cmpeqpd, gen_helper_cmpeqss,
gen_helper_cmpeqsd, },
2980 SSE_FOP(cmplt){ gen_helper_cmpltps, gen_helper_cmpltpd, gen_helper_cmpltss,
gen_helper_cmpltsd, },
2981 SSE_FOP(cmple){ gen_helper_cmpleps, gen_helper_cmplepd, gen_helper_cmpless,
gen_helper_cmplesd, },
2982 SSE_FOP(cmpunord){ gen_helper_cmpunordps, gen_helper_cmpunordpd, gen_helper_cmpunordss
, gen_helper_cmpunordsd, },
2983 SSE_FOP(cmpneq){ gen_helper_cmpneqps, gen_helper_cmpneqpd, gen_helper_cmpneqss
, gen_helper_cmpneqsd, },
2984 SSE_FOP(cmpnlt){ gen_helper_cmpnltps, gen_helper_cmpnltpd, gen_helper_cmpnltss
, gen_helper_cmpnltsd, },
2985 SSE_FOP(cmpnle){ gen_helper_cmpnleps, gen_helper_cmpnlepd, gen_helper_cmpnless
, gen_helper_cmpnlesd, },
2986 SSE_FOP(cmpord){ gen_helper_cmpordps, gen_helper_cmpordpd, gen_helper_cmpordss
, gen_helper_cmpordsd, },
2987};
2988
2989static const SSEFunc_0_pp sse_op_table5[256] = {
2990 [0x0c] = gen_helper_pi2fw,
2991 [0x0d] = gen_helper_pi2fd,
2992 [0x1c] = gen_helper_pf2iw,
2993 [0x1d] = gen_helper_pf2id,
2994 [0x8a] = gen_helper_pfnacc,
2995 [0x8e] = gen_helper_pfpnacc,
2996 [0x90] = gen_helper_pfcmpge,
2997 [0x94] = gen_helper_pfmin,
2998 [0x96] = gen_helper_pfrcp,
2999 [0x97] = gen_helper_pfrsqrt,
3000 [0x9a] = gen_helper_pfsub,
3001 [0x9e] = gen_helper_pfadd,
3002 [0xa0] = gen_helper_pfcmpgt,
3003 [0xa4] = gen_helper_pfmax,
3004 [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
3005 [0xa7] = gen_helper_movq, /* pfrsqit1 */
3006 [0xaa] = gen_helper_pfsubr,
3007 [0xae] = gen_helper_pfacc,
3008 [0xb0] = gen_helper_pfcmpeq,
3009 [0xb4] = gen_helper_pfmul,
3010 [0xb6] = gen_helper_movq, /* pfrcpit2 */
3011 [0xb7] = gen_helper_pmulhrw_mmx,
3012 [0xbb] = gen_helper_pswapd,
3013 [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
3014};
3015
3016struct SSEOpHelper_pp {
3017 SSEFunc_0_pp op[2];
3018 uint32_t ext_mask;
3019};
3020
3021struct SSEOpHelper_ppi {
3022 SSEFunc_0_ppi op[2];
3023 uint32_t ext_mask;
3024};
3025
3026#define SSSE3_OP(x){ { gen_helper_x_mmx, gen_helper_x_xmm }, (1 << 9) } { MMX_OP2(x){ gen_helper_x_mmx, gen_helper_x_xmm }, CPUID_EXT_SSSE3(1 << 9) }
3027#define SSE41_OP(x){ { ((void*)0), gen_helper_x_xmm }, (1 << 19) } { { NULL((void*)0), gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41(1 << 19) }
3028#define SSE42_OP(x){ { ((void*)0), gen_helper_x_xmm }, (1 << 20) } { { NULL((void*)0), gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42(1 << 20) }
3029#define SSE41_SPECIAL{ { ((void*)0), ((void *)1) }, (1 << 19) } { { NULL((void*)0), SSE_SPECIAL((void *)1) }, CPUID_EXT_SSE41(1 << 19) }
3030
3031static const struct SSEOpHelper_pp sse_op_table6[256] = {
3032 [0x00] = SSSE3_OP(pshufb){ { gen_helper_pshufb_mmx, gen_helper_pshufb_xmm }, (1 <<
9) },
3033 [0x01] = SSSE3_OP(phaddw){ { gen_helper_phaddw_mmx, gen_helper_phaddw_xmm }, (1 <<
9) },
3034 [0x02] = SSSE3_OP(phaddd){ { gen_helper_phaddd_mmx, gen_helper_phaddd_xmm }, (1 <<
9) },
3035 [0x03] = SSSE3_OP(phaddsw){ { gen_helper_phaddsw_mmx, gen_helper_phaddsw_xmm }, (1 <<
9) },
3036 [0x04] = SSSE3_OP(pmaddubsw){ { gen_helper_pmaddubsw_mmx, gen_helper_pmaddubsw_xmm }, (1 <<
9) },
3037 [0x05] = SSSE3_OP(phsubw){ { gen_helper_phsubw_mmx, gen_helper_phsubw_xmm }, (1 <<
9) },
3038 [0x06] = SSSE3_OP(phsubd){ { gen_helper_phsubd_mmx, gen_helper_phsubd_xmm }, (1 <<
9) },
3039 [0x07] = SSSE3_OP(phsubsw){ { gen_helper_phsubsw_mmx, gen_helper_phsubsw_xmm }, (1 <<
9) },
3040 [0x08] = SSSE3_OP(psignb){ { gen_helper_psignb_mmx, gen_helper_psignb_xmm }, (1 <<
9) },
3041 [0x09] = SSSE3_OP(psignw){ { gen_helper_psignw_mmx, gen_helper_psignw_xmm }, (1 <<
9) },
3042 [0x0a] = SSSE3_OP(psignd){ { gen_helper_psignd_mmx, gen_helper_psignd_xmm }, (1 <<
9) },
3043 [0x0b] = SSSE3_OP(pmulhrsw){ { gen_helper_pmulhrsw_mmx, gen_helper_pmulhrsw_xmm }, (1 <<
9) },
3044 [0x10] = SSE41_OP(pblendvb){ { ((void*)0), gen_helper_pblendvb_xmm }, (1 << 19) },
3045 [0x14] = SSE41_OP(blendvps){ { ((void*)0), gen_helper_blendvps_xmm }, (1 << 19) },
3046 [0x15] = SSE41_OP(blendvpd){ { ((void*)0), gen_helper_blendvpd_xmm }, (1 << 19) },
3047 [0x17] = SSE41_OP(ptest){ { ((void*)0), gen_helper_ptest_xmm }, (1 << 19) },
3048 [0x1c] = SSSE3_OP(pabsb){ { gen_helper_pabsb_mmx, gen_helper_pabsb_xmm }, (1 <<
9) },
3049 [0x1d] = SSSE3_OP(pabsw){ { gen_helper_pabsw_mmx, gen_helper_pabsw_xmm }, (1 <<
9) },
3050 [0x1e] = SSSE3_OP(pabsd){ { gen_helper_pabsd_mmx, gen_helper_pabsd_xmm }, (1 <<
9) },
3051 [0x20] = SSE41_OP(pmovsxbw){ { ((void*)0), gen_helper_pmovsxbw_xmm }, (1 << 19) },
3052 [0x21] = SSE41_OP(pmovsxbd){ { ((void*)0), gen_helper_pmovsxbd_xmm }, (1 << 19) },
3053 [0x22] = SSE41_OP(pmovsxbq){ { ((void*)0), gen_helper_pmovsxbq_xmm }, (1 << 19) },
3054 [0x23] = SSE41_OP(pmovsxwd){ { ((void*)0), gen_helper_pmovsxwd_xmm }, (1 << 19) },
3055 [0x24] = SSE41_OP(pmovsxwq){ { ((void*)0), gen_helper_pmovsxwq_xmm }, (1 << 19) },
3056 [0x25] = SSE41_OP(pmovsxdq){ { ((void*)0), gen_helper_pmovsxdq_xmm }, (1 << 19) },
3057 [0x28] = SSE41_OP(pmuldq){ { ((void*)0), gen_helper_pmuldq_xmm }, (1 << 19) },
3058 [0x29] = SSE41_OP(pcmpeqq){ { ((void*)0), gen_helper_pcmpeqq_xmm }, (1 << 19) },
3059 [0x2a] = SSE41_SPECIAL{ { ((void*)0), ((void *)1) }, (1 << 19) }, /* movntqda */
3060 [0x2b] = SSE41_OP(packusdw){ { ((void*)0), gen_helper_packusdw_xmm }, (1 << 19) },
3061 [0x30] = SSE41_OP(pmovzxbw){ { ((void*)0), gen_helper_pmovzxbw_xmm }, (1 << 19) },
3062 [0x31] = SSE41_OP(pmovzxbd){ { ((void*)0), gen_helper_pmovzxbd_xmm }, (1 << 19) },
3063 [0x32] = SSE41_OP(pmovzxbq){ { ((void*)0), gen_helper_pmovzxbq_xmm }, (1 << 19) },
3064 [0x33] = SSE41_OP(pmovzxwd){ { ((void*)0), gen_helper_pmovzxwd_xmm }, (1 << 19) },
3065 [0x34] = SSE41_OP(pmovzxwq){ { ((void*)0), gen_helper_pmovzxwq_xmm }, (1 << 19) },
3066 [0x35] = SSE41_OP(pmovzxdq){ { ((void*)0), gen_helper_pmovzxdq_xmm }, (1 << 19) },
3067 [0x37] = SSE42_OP(pcmpgtq){ { ((void*)0), gen_helper_pcmpgtq_xmm }, (1 << 20) },
3068 [0x38] = SSE41_OP(pminsb){ { ((void*)0), gen_helper_pminsb_xmm }, (1 << 19) },
3069 [0x39] = SSE41_OP(pminsd){ { ((void*)0), gen_helper_pminsd_xmm }, (1 << 19) },
3070 [0x3a] = SSE41_OP(pminuw){ { ((void*)0), gen_helper_pminuw_xmm }, (1 << 19) },
3071 [0x3b] = SSE41_OP(pminud){ { ((void*)0), gen_helper_pminud_xmm }, (1 << 19) },
3072 [0x3c] = SSE41_OP(pmaxsb){ { ((void*)0), gen_helper_pmaxsb_xmm }, (1 << 19) },
3073 [0x3d] = SSE41_OP(pmaxsd){ { ((void*)0), gen_helper_pmaxsd_xmm }, (1 << 19) },
3074 [0x3e] = SSE41_OP(pmaxuw){ { ((void*)0), gen_helper_pmaxuw_xmm }, (1 << 19) },
3075 [0x3f] = SSE41_OP(pmaxud){ { ((void*)0), gen_helper_pmaxud_xmm }, (1 << 19) },
3076 [0x40] = SSE41_OP(pmulld){ { ((void*)0), gen_helper_pmulld_xmm }, (1 << 19) },
3077 [0x41] = SSE41_OP(phminposuw){ { ((void*)0), gen_helper_phminposuw_xmm }, (1 << 19) },
3078};
3079
3080static const struct SSEOpHelper_ppi sse_op_table7[256] = {
3081 [0x08] = SSE41_OP(roundps){ { ((void*)0), gen_helper_roundps_xmm }, (1 << 19) },
3082 [0x09] = SSE41_OP(roundpd){ { ((void*)0), gen_helper_roundpd_xmm }, (1 << 19) },
3083 [0x0a] = SSE41_OP(roundss){ { ((void*)0), gen_helper_roundss_xmm }, (1 << 19) },
3084 [0x0b] = SSE41_OP(roundsd){ { ((void*)0), gen_helper_roundsd_xmm }, (1 << 19) },
3085 [0x0c] = SSE41_OP(blendps){ { ((void*)0), gen_helper_blendps_xmm }, (1 << 19) },
3086 [0x0d] = SSE41_OP(blendpd){ { ((void*)0), gen_helper_blendpd_xmm }, (1 << 19) },
3087 [0x0e] = SSE41_OP(pblendw){ { ((void*)0), gen_helper_pblendw_xmm }, (1 << 19) },
3088 [0x0f] = SSSE3_OP(palignr){ { gen_helper_palignr_mmx, gen_helper_palignr_xmm }, (1 <<
9) },
3089 [0x14] = SSE41_SPECIAL{ { ((void*)0), ((void *)1) }, (1 << 19) }, /* pextrb */
3090 [0x15] = SSE41_SPECIAL{ { ((void*)0), ((void *)1) }, (1 << 19) }, /* pextrw */
3091 [0x16] = SSE41_SPECIAL{ { ((void*)0), ((void *)1) }, (1 << 19) }, /* pextrd/pextrq */
3092 [0x17] = SSE41_SPECIAL{ { ((void*)0), ((void *)1) }, (1 << 19) }, /* extractps */
3093 [0x20] = SSE41_SPECIAL{ { ((void*)0), ((void *)1) }, (1 << 19) }, /* pinsrb */
3094 [0x21] = SSE41_SPECIAL{ { ((void*)0), ((void *)1) }, (1 << 19) }, /* insertps */
3095 [0x22] = SSE41_SPECIAL{ { ((void*)0), ((void *)1) }, (1 << 19) }, /* pinsrd/pinsrq */
3096 [0x40] = SSE41_OP(dpps){ { ((void*)0), gen_helper_dpps_xmm }, (1 << 19) },
3097 [0x41] = SSE41_OP(dppd){ { ((void*)0), gen_helper_dppd_xmm }, (1 << 19) },
3098 [0x42] = SSE41_OP(mpsadbw){ { ((void*)0), gen_helper_mpsadbw_xmm }, (1 << 19) },
3099 [0x60] = SSE42_OP(pcmpestrm){ { ((void*)0), gen_helper_pcmpestrm_xmm }, (1 << 20) },
3100 [0x61] = SSE42_OP(pcmpestri){ { ((void*)0), gen_helper_pcmpestri_xmm }, (1 << 20) },
3101 [0x62] = SSE42_OP(pcmpistrm){ { ((void*)0), gen_helper_pcmpistrm_xmm }, (1 << 20) },
3102 [0x63] = SSE42_OP(pcmpistri){ { ((void*)0), gen_helper_pcmpistri_xmm }, (1 << 20) },
3103};
3104
3105static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3106{
3107 int b1, op1_offset, op2_offset, is_xmm, val, ot;
3108 int modrm, mod, rm, reg, reg_addr, offset_addr;
3109 SSEFunc_0_pp sse_fn_pp;
3110 SSEFunc_0_ppi sse_fn_ppi;
3111 SSEFunc_0_ppt sse_fn_ppt;
3112
3113 b &= 0xff;
3114 if (s->prefix & PREFIX_DATA0x08)
3115 b1 = 1;
3116 else if (s->prefix & PREFIX_REPZ0x01)
3117 b1 = 2;
3118 else if (s->prefix & PREFIX_REPNZ0x02)
3119 b1 = 3;
3120 else
3121 b1 = 0;
3122 sse_fn_pp = sse_op_table1[b][b1];
3123 if (!sse_fn_pp) {
3124 goto illegal_op;
3125 }
3126 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
3127 is_xmm = 1;
3128 } else {
3129 if (b1 == 0) {
3130 /* MMX case */
3131 is_xmm = 0;
3132 } else {
3133 is_xmm = 1;
3134 }
3135 }
3136 /* simple MMX/SSE operation */
3137 if (s->flags & HF_TS_MASK(1 << 11)) {
3138 gen_exception(s, EXCP07_PREX7, pc_start - s->cs_base);
3139 return;
3140 }
3141 if (s->flags & HF_EM_MASK(1 << 10)) {
3142 illegal_op:
3143 gen_exception(s, EXCP06_ILLOP6, pc_start - s->cs_base);
3144 return;
3145 }
3146 if (is_xmm && !(s->flags & HF_OSFXSR_MASK(1 << 22)))
3147 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA0x08))
3148 goto illegal_op;
3149 if (b == 0x0e) {
3150 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW(1 << 31)))
3151 goto illegal_op;
3152 /* femms */
3153 gen_helper_emms();
3154 return;
3155 }
3156 if (b == 0x77) {
3157 /* emms */
3158 gen_helper_emms();
3159 return;
3160 }
3161 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3162 the static cpu state) */
3163 if (!is_xmm) {
3164 gen_helper_enter_mmx();
3165 }
3166
3167 modrm = ldub_code(s->pc++);
3168 reg = ((modrm >> 3) & 7);
3169 if (is_xmm)
3170 reg |= rex_r;
3171 mod = (modrm >> 6) & 3;
3172 if (sse_fn_pp == SSE_SPECIAL((void *)1)) {
3173 b |= (b1 << 8);
3174 switch(b) {
3175 case 0x0e7: /* movntq */
3176 if (mod == 3)
3177 goto illegal_op;
3178 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3179 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)__builtin_offsetof(CPUX86State, fpregs[reg].mmx));
3180 break;
3181 case 0x1e7: /* movntdq */
3182 case 0x02b: /* movntps */
3183 case 0x12b: /* movntps */
3184 if (mod == 3)
3185 goto illegal_op;
3186 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3187 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]));
3188 break;
3189 case 0x3f0: /* lddqu */
3190 if (mod == 3)
3191 goto illegal_op;
3192 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3193 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]));
3194 break;
3195 case 0x22b: /* movntss */
3196 case 0x32b: /* movntsd */
3197 if (mod == 3)
3198 goto illegal_op;
3199 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3200 if (b1 & 1) {
3201 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg])
3202 xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]));
3203 } else {
3204 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[0])
3205 xmm_regs[reg].XMM_L(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[0]));
3206 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3207 }
3208 break;
3209 case 0x6e: /* movd mm, ea */
3210#ifdef TARGET_X86_64
3211 if (s->dflag == 2) {
3212 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3213 tcg_gen_st_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)__builtin_offsetof(CPUX86State, fpregs[reg].mmx));
3214 } else
3215#endif
3216 {
3217 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3218 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, fpregs[reg].mmx)))
3219 offsetof(CPUX86State,fpregs[reg].mmx))tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, fpregs[reg].mmx)));
3220 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
3221 gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
3222 }
3223 break;
3224 case 0x16e: /* movd xmm, ea */
3225#ifdef TARGET_X86_64
3226 if (s->dflag == 2) {
3227 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3228 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, xmm_regs[reg])))
3229 offsetof(CPUX86State,xmm_regs[reg]))tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, xmm_regs[reg])));
3230 gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
3231 } else
3232#endif
3233 {
3234 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3235 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, xmm_regs[reg])))
3236 offsetof(CPUX86State,xmm_regs[reg]))tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, xmm_regs[reg])));
3237 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
3238 gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
3239 }
3240 break;
3241 case 0x6f: /* movq mm, ea */
3242 if (mod != 3) {
3243 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3244 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)__builtin_offsetof(CPUX86State, fpregs[reg].mmx));
3245 } else {
3246 rm = (modrm & 7);
3247 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3248 offsetof(CPUX86State,fpregs[rm].mmx)__builtin_offsetof(CPUX86State, fpregs[rm].mmx));
3249 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3250 offsetof(CPUX86State,fpregs[reg].mmx)__builtin_offsetof(CPUX86State, fpregs[reg].mmx));
3251 }
3252 break;
3253 case 0x010: /* movups */
3254 case 0x110: /* movupd */
3255 case 0x028: /* movaps */
3256 case 0x128: /* movapd */
3257 case 0x16f: /* movdqa xmm, ea */
3258 case 0x26f: /* movdqu xmm, ea */
3259 if (mod != 3) {
3260 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3261 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]));
3262 } else {
3263 rm = (modrm & 7) | REX_B(s)0;
3264 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]),
3265 offsetof(CPUX86State,xmm_regs[rm])__builtin_offsetof(CPUX86State, xmm_regs[rm]));
3266 }
3267 break;
3268 case 0x210: /* movss xmm, ea */
3269 if (mod != 3) {
3270 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3271 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3272 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[0]));
3273 gen_op_movl_T0_0();
3274 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[1]));
3275 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[2]));
3276 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[3]));
3277 } else {
3278 rm = (modrm & 7) | REX_B(s)0;
3279 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[0]),
3280 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))__builtin_offsetof(CPUX86State, xmm_regs[rm]._l[0]));
3281 }
3282 break;
3283 case 0x310: /* movsd xmm, ea */
3284 if (mod != 3) {
3285 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3286 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]));
3287 gen_op_movl_T0_0();
3288 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[2]));
3289 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[3]));
3290 } else {
3291 rm = (modrm & 7) | REX_B(s)0;
3292 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]),
3293 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[rm]._q[0]));
3294 }
3295 break;
3296 case 0x012: /* movlps */
3297 case 0x112: /* movlpd */
3298 if (mod != 3) {
3299 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3300 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]));
3301 } else {
3302 /* movhlps */
3303 rm = (modrm & 7) | REX_B(s)0;
3304 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]),
3305 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))__builtin_offsetof(CPUX86State, xmm_regs[rm]._q[1]));
3306 }
3307 break;
3308 case 0x212: /* movsldup */
3309 if (mod != 3) {
3310 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3311 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]));
3312 } else {
3313 rm = (modrm & 7) | REX_B(s)0;
3314 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[0]),
3315 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))__builtin_offsetof(CPUX86State, xmm_regs[rm]._l[0]));
3316 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[2]),
3317 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2))__builtin_offsetof(CPUX86State, xmm_regs[rm]._l[2]));
3318 }
3319 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[1]),
3320 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[0]));
3321 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[3]),
3322 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[2]));
3323 break;
3324 case 0x312: /* movddup */
3325 if (mod != 3) {
3326 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3327 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]));
3328 } else {
3329 rm = (modrm & 7) | REX_B(s)0;
3330 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]),
3331 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[rm]._q[0]));
3332 }
3333 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[1]),
3334 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]));
3335 break;
3336 case 0x016: /* movhps */
3337 case 0x116: /* movhpd */
3338 if (mod != 3) {
3339 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3340 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[1]));
3341 } else {
3342 /* movlhps */
3343 rm = (modrm & 7) | REX_B(s)0;
3344 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[1]),
3345 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[rm]._q[0]));
3346 }
3347 break;
3348 case 0x216: /* movshdup */
3349 if (mod != 3) {
3350 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3351 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]));
3352 } else {
3353 rm = (modrm & 7) | REX_B(s)0;
3354 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[1]),
3355 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1))__builtin_offsetof(CPUX86State, xmm_regs[rm]._l[1]));
3356 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[3]),
3357 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3))__builtin_offsetof(CPUX86State, xmm_regs[rm]._l[3]));
3358 }
3359 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[0]),
3360 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[1]));
3361 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[2]),
3362 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[3]));
3363 break;
3364 case 0x178:
3365 case 0x378:
3366 {
3367 int bit_index, field_length;
3368
3369 if (b1 == 1 && reg != 0)
3370 goto illegal_op;
3371 field_length = ldub_code(s->pc++) & 0x3F;
3372 bit_index = ldub_code(s->pc++) & 0x3F;
3373 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, xmm_regs[reg])))
3374 offsetof(CPUX86State,xmm_regs[reg]))tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, xmm_regs[reg])));
3375 if (b1 == 1)
3376 gen_helper_extrq_i(cpu_ptr0, tcg_const_i32(bit_index),
3377 tcg_const_i32(field_length));
3378 else
3379 gen_helper_insertq_i(cpu_ptr0, tcg_const_i32(bit_index),
3380 tcg_const_i32(field_length));
3381 }
3382 break;
3383 case 0x7e: /* movd ea, mm */
3384#ifdef TARGET_X86_64
3385 if (s->dflag == 2) {
3386 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3387 offsetof(CPUX86State,fpregs[reg].mmx)__builtin_offsetof(CPUX86State, fpregs[reg].mmx));
3388 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3389 } else
3390#endif
3391 {
3392 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_T[0], cpu_env,
3393 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0))__builtin_offsetof(CPUX86State, fpregs[reg].mmx._l[0]));
3394 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3395 }
3396 break;
3397 case 0x17e: /* movd ea, xmm */
3398#ifdef TARGET_X86_64
3399 if (s->dflag == 2) {
3400 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3401 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]));
3402 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3403 } else
3404#endif
3405 {
3406 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_T[0], cpu_env,
3407 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[0]));
3408 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3409 }
3410 break;
3411 case 0x27e: /* movq xmm, ea */
3412 if (mod != 3) {
3413 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3414 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]));
3415 } else {
3416 rm = (modrm & 7) | REX_B(s)0;
3417 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]),
3418 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[rm]._q[0]));
3419 }
3420 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[1]));
3421 break;
3422 case 0x7f: /* movq ea, mm */
3423 if (mod != 3) {
3424 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3425 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)__builtin_offsetof(CPUX86State, fpregs[reg].mmx));
3426 } else {
3427 rm = (modrm & 7);
3428 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx)__builtin_offsetof(CPUX86State, fpregs[rm].mmx),
3429 offsetof(CPUX86State,fpregs[reg].mmx)__builtin_offsetof(CPUX86State, fpregs[reg].mmx));
3430 }
3431 break;
3432 case 0x011: /* movups */
3433 case 0x111: /* movupd */
3434 case 0x029: /* movaps */
3435 case 0x129: /* movapd */
3436 case 0x17f: /* movdqa ea, xmm */
3437 case 0x27f: /* movdqu ea, xmm */
3438 if (mod != 3) {
3439 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3440 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]));
3441 } else {
3442 rm = (modrm & 7) | REX_B(s)0;
3443 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm])__builtin_offsetof(CPUX86State, xmm_regs[rm]),
3444 offsetof(CPUX86State,xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]));
3445 }
3446 break;
3447 case 0x211: /* movss ea, xmm */
3448 if (mod != 3) {
3449 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3450 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[0]));
3451 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3452 } else {
3453 rm = (modrm & 7) | REX_B(s)0;
3454 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))__builtin_offsetof(CPUX86State, xmm_regs[rm]._l[0]),
3455 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[0]));
3456 }
3457 break;
3458 case 0x311: /* movsd ea, xmm */
3459 if (mod != 3) {
3460 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3461 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]));
3462 } else {
3463 rm = (modrm & 7) | REX_B(s)0;
3464 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[rm]._q[0]),
3465 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]));
3466 }
3467 break;
3468 case 0x013: /* movlps */
3469 case 0x113: /* movlpd */
3470 if (mod != 3) {
3471 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3472 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]));
3473 } else {
3474 goto illegal_op;
3475 }
3476 break;
3477 case 0x017: /* movhps */
3478 case 0x117: /* movhpd */
3479 if (mod != 3) {
3480 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3481 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[1]));
3482 } else {
3483 goto illegal_op;
3484 }
3485 break;
3486 case 0x71: /* shift mm, im */
3487 case 0x72:
3488 case 0x73:
3489 case 0x171: /* shift xmm, im */
3490 case 0x172:
3491 case 0x173:
3492 if (b1 >= 2) {
3493 goto illegal_op;
3494 }
3495 val = ldub_code(s->pc++);
3496 if (is_xmm) {
3497 gen_op_movl_T0_im(val);
3498 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))__builtin_offsetof(CPUX86State, xmm_t0._l[0]));
3499 gen_op_movl_T0_0();
3500 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))__builtin_offsetof(CPUX86State, xmm_t0._l[1]));
3501 op1_offset = offsetof(CPUX86State,xmm_t0)__builtin_offsetof(CPUX86State, xmm_t0);
3502 } else {
3503 gen_op_movl_T0_im(val);
3504 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))__builtin_offsetof(CPUX86State, mmx_t0._l[0]));
3505 gen_op_movl_T0_0();
3506 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))__builtin_offsetof(CPUX86State, mmx_t0._l[1]));
3507 op1_offset = offsetof(CPUX86State,mmx_t0)__builtin_offsetof(CPUX86State, mmx_t0);
3508 }
3509 sse_fn_pp = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3510 if (!sse_fn_pp) {
3511 goto illegal_op;
3512 }
3513 if (is_xmm) {
3514 rm = (modrm & 7) | REX_B(s)0;
3515 op2_offset = offsetof(CPUX86State,xmm_regs[rm])__builtin_offsetof(CPUX86State, xmm_regs[rm]);
3516 } else {
3517 rm = (modrm & 7);
3518 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx)__builtin_offsetof(CPUX86State, fpregs[rm].mmx);
3519 }
3520 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op2_offset
));
3521 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr1).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op1_offset
));
3522 sse_fn_pp(cpu_ptr0, cpu_ptr1);
3523 break;
3524 case 0x050: /* movmskps */
3525 rm = (modrm & 7) | REX_B(s)0;
3526 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, xmm_regs[rm])))
3527 offsetof(CPUX86State,xmm_regs[rm]))tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, xmm_regs[rm])));
3528 gen_helper_movmskps(cpu_tmp2_i32, cpu_ptr0);
3529 tcg_gen_extu_i32_tltcg_gen_mov_i32(cpu_T[0], cpu_tmp2_i32);
3530 gen_op_mov_reg_T0(OT_LONG, reg);
3531 break;
3532 case 0x150: /* movmskpd */
3533 rm = (modrm & 7) | REX_B(s)0;
3534 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, xmm_regs[rm])))
3535 offsetof(CPUX86State,xmm_regs[rm]))tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, xmm_regs[rm])));
3536 gen_helper_movmskpd(cpu_tmp2_i32, cpu_ptr0);
3537 tcg_gen_extu_i32_tltcg_gen_mov_i32(cpu_T[0], cpu_tmp2_i32);
3538 gen_op_mov_reg_T0(OT_LONG, reg);
3539 break;
3540 case 0x02a: /* cvtpi2ps */
3541 case 0x12a: /* cvtpi2pd */
3542 gen_helper_enter_mmx();
3543 if (mod != 3) {
3544 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3545 op2_offset = offsetof(CPUX86State,mmx_t0)__builtin_offsetof(CPUX86State, mmx_t0);
3546 gen_ldq_env_A0(s->mem_index, op2_offset);
3547 } else {
3548 rm = (modrm & 7);
3549 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx)__builtin_offsetof(CPUX86State, fpregs[rm].mmx);
3550 }
3551 op1_offset = offsetof(CPUX86State,xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]);
3552 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op1_offset
));
3553 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr1).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op2_offset
));
3554 switch(b >> 8) {
3555 case 0x0:
3556 gen_helper_cvtpi2ps(cpu_ptr0, cpu_ptr1);
3557 break;
3558 default:
3559 case 0x1:
3560 gen_helper_cvtpi2pd(cpu_ptr0, cpu_ptr1);
3561 break;
3562 }
3563 break;
3564 case 0x22a: /* cvtsi2ss */
3565 case 0x32a: /* cvtsi2sd */
3566 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3567 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3568 op1_offset = offsetof(CPUX86State,xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]);
3569 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op1_offset
));
3570 if (ot == OT_LONG) {
3571 SSEFunc_0_pi sse_fn_pi = sse_op_table3ai[(b >> 8) - 2];
3572 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
3573 sse_fn_pi(cpu_ptr0, cpu_tmp2_i32);
3574 } else {
3575#ifdef TARGET_X86_64
3576 SSEFunc_0_pl sse_fn_pl = sse_op_table3aq[(b >> 8) - 2];
3577 sse_fn_pl(cpu_ptr0, cpu_T[0]);
3578#else
3579 goto illegal_op;
3580#endif
3581 }
3582 break;
3583 case 0x02c: /* cvttps2pi */
3584 case 0x12c: /* cvttpd2pi */
3585 case 0x02d: /* cvtps2pi */
3586 case 0x12d: /* cvtpd2pi */
3587 gen_helper_enter_mmx();
3588 if (mod != 3) {
3589 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3590 op2_offset = offsetof(CPUX86State,xmm_t0)__builtin_offsetof(CPUX86State, xmm_t0);
3591 gen_ldo_env_A0(s->mem_index, op2_offset);
3592 } else {
3593 rm = (modrm & 7) | REX_B(s)0;
3594 op2_offset = offsetof(CPUX86State,xmm_regs[rm])__builtin_offsetof(CPUX86State, xmm_regs[rm]);
3595 }
3596 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx)__builtin_offsetof(CPUX86State, fpregs[reg & 7].mmx);
3597 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op1_offset
));
3598 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr1).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op2_offset
));
3599 switch(b) {
3600 case 0x02c:
3601 gen_helper_cvttps2pi(cpu_ptr0, cpu_ptr1);
3602 break;
3603 case 0x12c:
3604 gen_helper_cvttpd2pi(cpu_ptr0, cpu_ptr1);
3605 break;
3606 case 0x02d:
3607 gen_helper_cvtps2pi(cpu_ptr0, cpu_ptr1);
3608 break;
3609 case 0x12d:
3610 gen_helper_cvtpd2pi(cpu_ptr0, cpu_ptr1);
3611 break;
3612 }
3613 break;
3614 case 0x22c: /* cvttss2si */
3615 case 0x32c: /* cvttsd2si */
3616 case 0x22d: /* cvtss2si */
3617 case 0x32d: /* cvtsd2si */
3618 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3619 if (mod != 3) {
3620 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3621 if ((b >> 8) & 1) {
3622 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_t0._q[0]));
3623 } else {
3624 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3625 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))__builtin_offsetof(CPUX86State, xmm_t0._l[0]));
3626 }
3627 op2_offset = offsetof(CPUX86State,xmm_t0)__builtin_offsetof(CPUX86State, xmm_t0);
3628 } else {
3629 rm = (modrm & 7) | REX_B(s)0;
3630 op2_offset = offsetof(CPUX86State,xmm_regs[rm])__builtin_offsetof(CPUX86State, xmm_regs[rm]);
3631 }
3632 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op2_offset
));
3633 if (ot == OT_LONG) {
3634 SSEFunc_i_p sse_fn_i_p =
3635 sse_op_table3bi[(b >> 8) - 2 + (b & 1) * 2];
3636 sse_fn_i_p(cpu_tmp2_i32, cpu_ptr0);
3637 tcg_gen_extu_i32_tltcg_gen_mov_i32(cpu_T[0], cpu_tmp2_i32);
3638 } else {
3639#ifdef TARGET_X86_64
3640 SSEFunc_l_p sse_fn_l_p =
3641 sse_op_table3bq[(b >> 8) - 2 + (b & 1) * 2];
3642 sse_fn_l_p(cpu_T[0], cpu_ptr0);
3643#else
3644 goto illegal_op;
3645#endif
3646 }
3647 gen_op_mov_reg_T0(ot, reg);
3648 break;
3649 case 0xc4: /* pinsrw */
3650 case 0x1c4:
3651 s->rip_offset = 1;
3652 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3653 val = ldub_code(s->pc++);
3654 if (b1) {
3655 val &= 7;
3656 tcg_gen_st16_tltcg_gen_st16_i32(cpu_T[0], cpu_env,
3657 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val))__builtin_offsetof(CPUX86State, xmm_regs[reg]._w[val]));
3658 } else {
3659 val &= 3;
3660 tcg_gen_st16_tltcg_gen_st16_i32(cpu_T[0], cpu_env,
3661 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val))__builtin_offsetof(CPUX86State, fpregs[reg].mmx._w[val]));
3662 }
3663 break;
3664 case 0xc5: /* pextrw */
3665 case 0x1c5:
3666 if (mod != 3)
3667 goto illegal_op;
3668 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3669 val = ldub_code(s->pc++);
3670 if (b1) {
3671 val &= 7;
3672 rm = (modrm & 7) | REX_B(s)0;
3673 tcg_gen_ld16u_tltcg_gen_ld16u_i32(cpu_T[0], cpu_env,
3674 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val))__builtin_offsetof(CPUX86State, xmm_regs[rm]._w[val]));
3675 } else {
3676 val &= 3;
3677 rm = (modrm & 7);
3678 tcg_gen_ld16u_tltcg_gen_ld16u_i32(cpu_T[0], cpu_env,
3679 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))__builtin_offsetof(CPUX86State, fpregs[rm].mmx._w[val]));
3680 }
3681 reg = ((modrm >> 3) & 7) | rex_r;
3682 gen_op_mov_reg_T0(ot, reg);
3683 break;
3684 case 0x1d6: /* movq ea, xmm */
3685 if (mod != 3) {
3686 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3687 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]));
3688 } else {
3689 rm = (modrm & 7) | REX_B(s)0;
3690 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[rm]._q[0]),
3691 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]));
3692 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))__builtin_offsetof(CPUX86State, xmm_regs[rm]._q[1]));
3693 }
3694 break;
3695 case 0x2d6: /* movq2dq */
3696 gen_helper_enter_mmx();
3697 rm = (modrm & 7);
3698 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[0]),
3699 offsetof(CPUX86State,fpregs[rm].mmx)__builtin_offsetof(CPUX86State, fpregs[rm].mmx));
3700 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[1]));
3701 break;
3702 case 0x3d6: /* movdq2q */
3703 gen_helper_enter_mmx();
3704 rm = (modrm & 7) | REX_B(s)0;
3705 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx)__builtin_offsetof(CPUX86State, fpregs[reg & 7].mmx),
3706 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))__builtin_offsetof(CPUX86State, xmm_regs[rm]._q[0]));
3707 break;
3708 case 0xd7: /* pmovmskb */
3709 case 0x1d7:
3710 if (mod != 3)
3711 goto illegal_op;
3712 if (b1) {
3713 rm = (modrm & 7) | REX_B(s)0;
3714 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]))tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, xmm_regs[rm])));
3715 gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_ptr0);
3716 } else {
3717 rm = (modrm & 7);
3718 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx))tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (__builtin_offsetof
(CPUX86State, fpregs[rm].mmx)));
3719 gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_ptr0);
3720 }
3721 tcg_gen_extu_i32_tltcg_gen_mov_i32(cpu_T[0], cpu_tmp2_i32);
3722 reg = ((modrm >> 3) & 7) | rex_r;
3723 gen_op_mov_reg_T0(OT_LONG, reg);
3724 break;
3725 case 0x138:
3726 if (s->prefix & PREFIX_REPNZ0x02)
3727 goto crc32;
3728 case 0x038:
3729 b = modrm;
3730 modrm = ldub_code(s->pc++);
3731 rm = modrm & 7;
3732 reg = ((modrm >> 3) & 7) | rex_r;
3733 mod = (modrm >> 6) & 3;
3734 if (b1 >= 2) {
3735 goto illegal_op;
3736 }
3737
3738 sse_fn_pp = sse_op_table6[b].op[b1];
3739 if (!sse_fn_pp) {
3740 goto illegal_op;
3741 }
3742 if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3743 goto illegal_op;
3744
3745 if (b1) {
3746 op1_offset = offsetof(CPUX86State,xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]);
3747 if (mod == 3) {
3748 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)])__builtin_offsetof(CPUX86State, xmm_regs[rm | 0]);
3749 } else {
3750 op2_offset = offsetof(CPUX86State,xmm_t0)__builtin_offsetof(CPUX86State, xmm_t0);
3751 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3752 switch (b) {
3753 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3754 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3755 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3756 gen_ldq_env_A0(s->mem_index, op2_offset +
3757 offsetof(XMMReg, XMM_Q(0))__builtin_offsetof(XMMReg, _q[0]));
3758 break;
3759 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3760 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3761 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3762 (s->mem_index >> 2) - 1);
3763 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_tmp0);
3764 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3765 offsetof(XMMReg, XMM_L(0))__builtin_offsetof(XMMReg, _l[0]));
3766 break;
3767 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3768 tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3769 (s->mem_index >> 2) - 1);
3770 tcg_gen_st16_tltcg_gen_st16_i32(cpu_tmp0, cpu_env, op2_offset +
3771 offsetof(XMMReg, XMM_W(0))__builtin_offsetof(XMMReg, _w[0]));
3772 break;
3773 case 0x2a: /* movntqda */
3774 gen_ldo_env_A0(s->mem_index, op1_offset);
3775 return;
3776 default:
3777 gen_ldo_env_A0(s->mem_index, op2_offset);
3778 }
3779 }
3780 } else {
3781 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx)__builtin_offsetof(CPUX86State, fpregs[reg].mmx);
3782 if (mod == 3) {
3783 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx)__builtin_offsetof(CPUX86State, fpregs[rm].mmx);
3784 } else {
3785 op2_offset = offsetof(CPUX86State,mmx_t0)__builtin_offsetof(CPUX86State, mmx_t0);
3786 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3787 gen_ldq_env_A0(s->mem_index, op2_offset);
3788 }
3789 }
3790 if (sse_fn_pp == SSE_SPECIAL((void *)1)) {
3791 goto illegal_op;
3792 }
3793
3794 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op1_offset
));
3795 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr1).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op2_offset
));
3796 sse_fn_pp(cpu_ptr0, cpu_ptr1);
3797
3798 if (b == 0x17)
3799 s->cc_op = CC_OP_EFLAGS;
3800 break;
3801 case 0x338: /* crc32 */
3802 crc32:
3803 b = modrm;
3804 modrm = ldub_code(s->pc++);
3805 reg = ((modrm >> 3) & 7) | rex_r;
3806
3807 if (b != 0xf0 && b != 0xf1)
3808 goto illegal_op;
3809 if (!(s->cpuid_ext_features & CPUID_EXT_SSE42(1 << 20)))
3810 goto illegal_op;
3811
3812 if (b == 0xf0)
3813 ot = OT_BYTE;
3814 else if (b == 0xf1 && s->dflag != 2)
3815 if (s->prefix & PREFIX_DATA0x08)
3816 ot = OT_WORD;
3817 else
3818 ot = OT_LONG;
3819 else
3820 ot = OT_QUAD;
3821
3822 gen_op_mov_TN_reg(OT_LONG, 0, reg);
3823 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
3824 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3825 gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3826 cpu_T[0], tcg_const_i32(8 << ot));
3827
3828 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3829 gen_op_mov_reg_T0(ot, reg);
3830 break;
3831 case 0x03a:
3832 case 0x13a:
3833 b = modrm;
3834 modrm = ldub_code(s->pc++);
3835 rm = modrm & 7;
3836 reg = ((modrm >> 3) & 7) | rex_r;
3837 mod = (modrm >> 6) & 3;
3838 if (b1 >= 2) {
3839 goto illegal_op;
3840 }
3841
3842 sse_fn_ppi = sse_op_table7[b].op[b1];
3843 if (!sse_fn_ppi) {
3844 goto illegal_op;
3845 }
3846 if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
3847 goto illegal_op;
3848
3849 if (sse_fn_ppi == SSE_SPECIAL((void *)1)) {
3850 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3851 rm = (modrm & 7) | REX_B(s)0;
3852 if (mod != 3)
3853 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3854 reg = ((modrm >> 3) & 7) | rex_r;
3855 val = ldub_code(s->pc++);
3856 switch (b) {
3857 case 0x14: /* pextrb */
3858 tcg_gen_ld8u_tltcg_gen_ld8u_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg]._b[val & 15
])
3859 xmm_regs[reg].XMM_B(val & 15))__builtin_offsetof(CPUX86State, xmm_regs[reg]._b[val & 15
]));
3860 if (mod == 3)
3861 gen_op_mov_reg_T0(ot, rm);
3862 else
3863 tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
3864 (s->mem_index >> 2) - 1);
3865 break;
3866 case 0x15: /* pextrw */
3867 tcg_gen_ld16u_tltcg_gen_ld16u_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg]._w[val & 7]
)
3868 xmm_regs[reg].XMM_W(val & 7))__builtin_offsetof(CPUX86State, xmm_regs[reg]._w[val & 7]
));
3869 if (mod == 3)
3870 gen_op_mov_reg_T0(ot, rm);
3871 else
3872 tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
3873 (s->mem_index >> 2) - 1);
3874 break;
3875 case 0x16:
3876 if (ot == OT_LONG) { /* pextrd */
3877 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3878 offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[val & 3]
)
3879 xmm_regs[reg].XMM_L(val & 3))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[val & 3]
));
3880 tcg_gen_extu_i32_tltcg_gen_mov_i32(cpu_T[0], cpu_tmp2_i32);
3881 if (mod == 3)
3882 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
3883 else
3884 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3885 (s->mem_index >> 2) - 1);
3886 } else { /* pextrq */
3887#ifdef TARGET_X86_64
3888 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3889 offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[val & 1]
)
3890 xmm_regs[reg].XMM_Q(val & 1))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[val & 1]
));
3891 if (mod == 3)
3892 gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
3893 else
3894 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
3895 (s->mem_index >> 2) - 1);
3896#else
3897 goto illegal_op;
3898#endif
3899 }
3900 break;
3901 case 0x17: /* extractps */
3902 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[val & 3]
)
3903 xmm_regs[reg].XMM_L(val & 3))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[val & 3]
));
3904 if (mod == 3)
3905 gen_op_mov_reg_T0(ot, rm);
3906 else
3907 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3908 (s->mem_index >> 2) - 1);
3909 break;
3910 case 0x20: /* pinsrb */
3911 if (mod == 3)
3912 gen_op_mov_TN_reg(OT_LONG, 0, rm);
3913 else
3914 tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
3915 (s->mem_index >> 2) - 1);
3916 tcg_gen_st8_tltcg_gen_st8_i32(cpu_tmp0, cpu_env, offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg]._b[val & 15
])
3917 xmm_regs[reg].XMM_B(val & 15))__builtin_offsetof(CPUX86State, xmm_regs[reg]._b[val & 15
]));
3918 break;
3919 case 0x21: /* insertps */
3920 if (mod == 3) {
3921 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3922 offsetof(CPUX86State,xmm_regs[rm]__builtin_offsetof(CPUX86State, xmm_regs[rm] ._l[(val >>
6) & 3])
3923 .XMM_L((val >> 6) & 3))__builtin_offsetof(CPUX86State, xmm_regs[rm] ._l[(val >>
6) & 3]));
3924 } else {
3925 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3926 (s->mem_index >> 2) - 1);
3927 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_tmp0);
3928 }
3929 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3930 offsetof(CPUX86State,xmm_regs[reg]__builtin_offsetof(CPUX86State, xmm_regs[reg] ._l[(val >>
4) & 3])
3931 .XMM_L((val >> 4) & 3))__builtin_offsetof(CPUX86State, xmm_regs[reg] ._l[(val >>
4) & 3]));
3932 if ((val >> 0) & 1)
3933 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3934 cpu_env, offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[0])
3935 xmm_regs[reg].XMM_L(0))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[0]));
3936 if ((val >> 1) & 1)
3937 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3938 cpu_env, offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[1])
3939 xmm_regs[reg].XMM_L(1))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[1]));
3940 if ((val >> 2) & 1)
3941 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3942 cpu_env, offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[2])
3943 xmm_regs[reg].XMM_L(2))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[2]));
3944 if ((val >> 3) & 1)
3945 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3946 cpu_env, offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[3])
3947 xmm_regs[reg].XMM_L(3))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[3]));
3948 break;
3949 case 0x22:
3950 if (ot == OT_LONG) { /* pinsrd */
3951 if (mod == 3)
3952 gen_op_mov_v_reg(ot, cpu_tmp0, rm);
3953 else
3954 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3955 (s->mem_index >> 2) - 1);
3956 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_tmp0);
3957 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3958 offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[val & 3]
)
3959 xmm_regs[reg].XMM_L(val & 3))__builtin_offsetof(CPUX86State, xmm_regs[reg]._l[val & 3]
));
3960 } else { /* pinsrq */
3961#ifdef TARGET_X86_64
3962 if (mod == 3)
3963 gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
3964 else
3965 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
3966 (s->mem_index >> 2) - 1);
3967 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3968 offsetof(CPUX86State,__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[val & 1]
)
3969 xmm_regs[reg].XMM_Q(val & 1))__builtin_offsetof(CPUX86State, xmm_regs[reg]._q[val & 1]
));
3970#else
3971 goto illegal_op;
3972#endif
3973 }
3974 break;
3975 }
3976 return;
3977 }
3978
3979 if (b1) {
3980 op1_offset = offsetof(CPUX86State,xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]);
3981 if (mod == 3) {
3982 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)])__builtin_offsetof(CPUX86State, xmm_regs[rm | 0]);
3983 } else {
3984 op2_offset = offsetof(CPUX86State,xmm_t0)__builtin_offsetof(CPUX86State, xmm_t0);
3985 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3986 gen_ldo_env_A0(s->mem_index, op2_offset);
3987 }
3988 } else {
3989 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx)__builtin_offsetof(CPUX86State, fpregs[reg].mmx);
3990 if (mod == 3) {
3991 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx)__builtin_offsetof(CPUX86State, fpregs[rm].mmx);
3992 } else {
3993 op2_offset = offsetof(CPUX86State,mmx_t0)__builtin_offsetof(CPUX86State, mmx_t0);
3994 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3995 gen_ldq_env_A0(s->mem_index, op2_offset);
3996 }
3997 }
3998 val = ldub_code(s->pc++);
3999
4000 if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
4001 s->cc_op = CC_OP_EFLAGS;
4002
4003 if (s->dflag == 2)
4004 /* The helper must use entire 64-bit gp registers */
4005 val |= 1 << 8;
4006 }
4007
4008 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op1_offset
));
4009 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr1).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op2_offset
));
4010 sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4011 break;
4012 default:
4013 goto illegal_op;
4014 }
4015 } else {
4016 /* generic MMX or SSE operation */
4017 switch(b) {
4018 case 0x70: /* pshufx insn */
4019 case 0xc6: /* pshufx insn */
4020 case 0xc2: /* compare insns */
4021 s->rip_offset = 1;
4022 break;
4023 default:
4024 break;
4025 }
4026 if (is_xmm) {
4027 op1_offset = offsetof(CPUX86State,xmm_regs[reg])__builtin_offsetof(CPUX86State, xmm_regs[reg]);
4028 if (mod != 3) {
4029 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4030 op2_offset = offsetof(CPUX86State,xmm_t0)__builtin_offsetof(CPUX86State, xmm_t0);
4031 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
4032 b == 0xc2)) {
4033 /* specific case for SSE single instructions */
4034 if (b1 == 2) {
4035 /* 32 bit access */
4036 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4037 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))__builtin_offsetof(CPUX86State, xmm_t0._l[0]));
4038 } else {
4039 /* 64 bit access */
4040 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0))__builtin_offsetof(CPUX86State, xmm_t0._d[0]));
4041 }
4042 } else {
4043 gen_ldo_env_A0(s->mem_index, op2_offset);
4044 }
4045 } else {
4046 rm = (modrm & 7) | REX_B(s)0;
4047 op2_offset = offsetof(CPUX86State,xmm_regs[rm])__builtin_offsetof(CPUX86State, xmm_regs[rm]);
4048 }
4049 } else {
4050 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx)__builtin_offsetof(CPUX86State, fpregs[reg].mmx);
4051 if (mod != 3) {
4052 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4053 op2_offset = offsetof(CPUX86State,mmx_t0)__builtin_offsetof(CPUX86State, mmx_t0);
4054 gen_ldq_env_A0(s->mem_index, op2_offset);
4055 } else {
4056 rm = (modrm & 7);
4057 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx)__builtin_offsetof(CPUX86State, fpregs[rm].mmx);
4058 }
4059 }
4060 switch(b) {
4061 case 0x0f: /* 3DNow! data insns */
4062 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW(1 << 31)))
4063 goto illegal_op;
4064 val = ldub_code(s->pc++);
4065 sse_fn_pp = sse_op_table5[val];
4066 if (!sse_fn_pp) {
4067 goto illegal_op;
4068 }
4069 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op1_offset
));
4070 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr1).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op2_offset
));
4071 sse_fn_pp(cpu_ptr0, cpu_ptr1);
4072 break;
4073 case 0x70: /* pshufx insn */
4074 case 0xc6: /* pshufx insn */
4075 val = ldub_code(s->pc++);
4076 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op1_offset
));
4077 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr1).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op2_offset
));
4078 /* XXX: introduce a new table? */
4079 sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_pp;
4080 sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4081 break;
4082 case 0xc2:
4083 /* compare insns */
4084 val = ldub_code(s->pc++);
4085 if (val >= 8)
4086 goto illegal_op;
4087 sse_fn_pp = sse_op_table4[val][b1];
4088
4089 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op1_offset
));
4090 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr1).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op2_offset
));
4091 sse_fn_pp(cpu_ptr0, cpu_ptr1);
4092 break;
4093 case 0xf7:
4094 /* maskmov : we must prepare A0 */
4095 if (mod != 3)
4096 goto illegal_op;
4097#ifdef TARGET_X86_64
4098 if (s->aflag == 2) {
4099 gen_op_movq_A0_reg(R_EDI7);
4100 } else
4101#endif
4102 {
4103 gen_op_movl_A0_reg(R_EDI7);
4104 if (s->aflag == 0)
4105 gen_op_andl_A0_ffff();
4106 }
4107 gen_add_A0_ds_seg(s);
4108
4109 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op1_offset
));
4110 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr1).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op2_offset
));
4111 /* XXX: introduce a new table? */
4112 sse_fn_ppt = (SSEFunc_0_ppt)sse_fn_pp;
4113 sse_fn_ppt(cpu_ptr0, cpu_ptr1, cpu_A0);
4114 break;
4115 default:
4116 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr0).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op1_offset
));
4117 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset)tcg_gen_addi_i64(__extension__ ({ TCGv_i64 make_tcgv_tmp = {(
(cpu_ptr1).iptr)}; make_tcgv_tmp;}), __extension__ ({ TCGv_i64
make_tcgv_tmp = {((cpu_env).iptr)}; make_tcgv_tmp;}), (op2_offset
));
4118 sse_fn_pp(cpu_ptr0, cpu_ptr1);
4119 break;
4120 }
4121 if (b == 0x2e || b == 0x2f) {
4122 s->cc_op = CC_OP_EFLAGS;
4123 }
4124 }
4125}
4126
4127/* convert one instruction. s->is_jmp is set if the translation must
4128 be stopped. Return the next pc value */
4129static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
4130{
4131 int b, prefixes, aflag, dflag;
4132 int shift, ot;
4133 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
4134 target_ulong next_eip, tval;
4135 int rex_w, rex_r;
4136
4137 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))__builtin_expect(!!(qemu_loglevel_mask((1 << 2))), 0))
4138 tcg_gen_debug_insn_start(pc_start);
4139 s->pc = pc_start;
4140 prefixes = 0;
4141 aflag = s->code32;
4142 dflag = s->code32;
4143 s->override = -1;
4144 rex_w = -1;
Value stored to 'rex_w' is never read
4145 rex_r = 0;
4146#ifdef TARGET_X86_64
4147 s->rex_x = 0;
4148 s->rex_b = 0;
4149 x86_64_hregs = 0;
4150#endif
4151 s->rip_offset = 0; /* for relative ip address */
4152 next_byte:
4153 b = ldub_code(s->pc);
4154 s->pc++;
4155 /* check prefixes */
4156#ifdef TARGET_X86_64
4157 if (CODE64(s)0) {
4158 switch (b) {
4159 case 0xf3:
4160 prefixes |= PREFIX_REPZ0x01;
4161 goto next_byte;
4162 case 0xf2:
4163 prefixes |= PREFIX_REPNZ0x02;
4164 goto next_byte;
4165 case 0xf0:
4166 prefixes |= PREFIX_LOCK0x04;
4167 goto next_byte;
4168 case 0x2e:
4169 s->override = R_CS1;
4170 goto next_byte;
4171 case 0x36:
4172 s->override = R_SS2;
4173 goto next_byte;
4174 case 0x3e:
4175 s->override = R_DS3;
4176 goto next_byte;
4177 case 0x26:
4178 s->override = R_ES0;
4179 goto next_byte;
4180 case 0x64:
4181 s->override = R_FS4;
4182 goto next_byte;
4183 case 0x65:
4184 s->override = R_GS5;
4185 goto next_byte;
4186 case 0x66:
4187 prefixes |= PREFIX_DATA0x08;
4188 goto next_byte;
4189 case 0x67:
4190 prefixes |= PREFIX_ADR0x10;
4191 goto next_byte;
4192 case 0x40 ... 0x4f:
4193 /* REX prefix */
4194 rex_w = (b >> 3) & 1;
4195 rex_r = (b & 0x4) << 1;
4196 s->rex_x = (b & 0x2) << 2;
4197 REX_B(s)0 = (b & 0x1) << 3;
4198 x86_64_hregs = 1; /* select uniform byte register addressing */
4199 goto next_byte;
4200 }
4201 if (rex_w == 1) {
4202 /* 0x66 is ignored if rex.w is set */
4203 dflag = 2;
4204 } else {
4205 if (prefixes & PREFIX_DATA0x08)
4206 dflag ^= 1;
4207 }
4208 if (!(prefixes & PREFIX_ADR0x10))
4209 aflag = 2;
4210 } else
4211#endif
4212 {
4213 switch (b) {
4214 case 0xf3:
4215 prefixes |= PREFIX_REPZ0x01;
4216 goto next_byte;
4217 case 0xf2:
4218 prefixes |= PREFIX_REPNZ0x02;
4219 goto next_byte;
4220 case 0xf0:
4221 prefixes |= PREFIX_LOCK0x04;
4222 goto next_byte;
4223 case 0x2e:
4224 s->override = R_CS1;
4225 goto next_byte;
4226 case 0x36:
4227 s->override = R_SS2;
4228 goto next_byte;
4229 case 0x3e:
4230 s->override = R_DS3;
4231 goto next_byte;
4232 case 0x26:
4233 s->override = R_ES0;
4234 goto next_byte;
4235 case 0x64:
4236 s->override = R_FS4;
4237 goto next_byte;
4238 case 0x65:
4239 s->override = R_GS5;
4240 goto next_byte;
4241 case 0x66:
4242 prefixes |= PREFIX_DATA0x08;
4243 goto next_byte;
4244 case 0x67:
4245 prefixes |= PREFIX_ADR0x10;
4246 goto next_byte;
4247 }
4248 if (prefixes & PREFIX_DATA0x08)
4249 dflag ^= 1;
4250 if (prefixes & PREFIX_ADR0x10)
4251 aflag ^= 1;
4252 }
4253
4254 s->prefix = prefixes;
4255 s->aflag = aflag;
4256 s->dflag = dflag;
4257
4258 /* lock generation */
4259 if (prefixes & PREFIX_LOCK0x04)
4260 gen_helper_lock();
4261
4262 /* now check op code */
4263 reswitch:
4264 switch(b) {
4265 case 0x0f:
4266 /**************************/
4267 /* extended op code */
4268 b = ldub_code(s->pc++) | 0x100;
4269 goto reswitch;
4270
4271 /**************************/
4272 /* arith & logic */
4273 case 0x00 ... 0x05:
4274 case 0x08 ... 0x0d:
4275 case 0x10 ... 0x15:
4276 case 0x18 ... 0x1d:
4277 case 0x20 ... 0x25:
4278 case 0x28 ... 0x2d:
4279 case 0x30 ... 0x35:
4280 case 0x38 ... 0x3d:
4281 {
4282 int op, f, val;
4283 op = (b >> 3) & 7;
4284 f = (b >> 1) & 3;
4285
4286 if ((b & 1) == 0)
4287 ot = OT_BYTE;
4288 else
4289 ot = dflag + OT_WORD;
4290
4291 switch(f) {
4292 case 0: /* OP Ev, Gv */
4293 modrm = ldub_code(s->pc++);
4294 reg = ((modrm >> 3) & 7) | rex_r;
4295 mod = (modrm >> 6) & 3;
4296 rm = (modrm & 7) | REX_B(s)0;
4297 if (mod != 3) {
4298 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4299 opreg = OR_TMP0;
4300 } else if (op == OP_XORL && rm == reg) {
4301 xor_zero:
4302 /* xor reg, reg optimisation */
4303 gen_op_movl_T0_0();
4304 s->cc_op = CC_OP_LOGICB + ot;
4305 gen_op_mov_reg_T0(ot, reg);
4306 gen_op_update1_cc();
4307 break;
4308 } else {
4309 opreg = rm;
4310 }
4311 gen_op_mov_TN_reg(ot, 1, reg);
4312 gen_op(s, op, ot, opreg);
4313 break;
4314 case 1: /* OP Gv, Ev */
4315 modrm = ldub_code(s->pc++);
4316 mod = (modrm >> 6) & 3;
4317 reg = ((modrm >> 3) & 7) | rex_r;
4318 rm = (modrm & 7) | REX_B(s)0;
4319 if (mod != 3) {
4320 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4321 gen_op_ld_T1_A0(ot + s->mem_index);
4322 } else if (op == OP_XORL && rm == reg) {
4323 goto xor_zero;
4324 } else {
4325 gen_op_mov_TN_reg(ot, 1, rm);
4326 }
4327 gen_op(s, op, ot, reg);
4328 break;
4329 case 2: /* OP A, Iv */
4330 val = insn_get(s, ot);
4331 gen_op_movl_T1_im(val);
4332 gen_op(s, op, ot, OR_EAX);
4333 break;
4334 }
4335 }
4336 break;
4337
4338 case 0x82:
4339 if (CODE64(s)0)
4340 goto illegal_op;
4341 case 0x80: /* GRP1 */
4342 case 0x81:
4343 case 0x83:
4344 {
4345 int val;
4346
4347 if ((b & 1) == 0)
4348 ot = OT_BYTE;
4349 else
4350 ot = dflag + OT_WORD;
4351
4352 modrm = ldub_code(s->pc++);
4353 mod = (modrm >> 6) & 3;
4354 rm = (modrm & 7) | REX_B(s)0;
4355 op = (modrm >> 3) & 7;
4356
4357 if (mod != 3) {
4358 if (b == 0x83)
4359 s->rip_offset = 1;
4360 else
4361 s->rip_offset = insn_const_size(ot);
4362 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4363 opreg = OR_TMP0;
4364 } else {
4365 opreg = rm;
4366 }
4367
4368 switch(b) {
4369 default:
4370 case 0x80:
4371 case 0x81:
4372 case 0x82:
4373 val = insn_get(s, ot);
4374 break;
4375 case 0x83:
4376 val = (int8_t)insn_get(s, OT_BYTE);
4377 break;
4378 }
4379 gen_op_movl_T1_im(val);
4380 gen_op(s, op, ot, opreg);
4381 }
4382 break;
4383
4384 /**************************/
4385 /* inc, dec, and other misc arith */
4386 case 0x40 ... 0x47: /* inc Gv */
4387 ot = dflag ? OT_LONG : OT_WORD;
4388 gen_inc(s, ot, OR_EAX + (b & 7), 1);
4389 break;
4390 case 0x48 ... 0x4f: /* dec Gv */
4391 ot = dflag ? OT_LONG : OT_WORD;
4392 gen_inc(s, ot, OR_EAX + (b & 7), -1);
4393 break;
4394 case 0xf6: /* GRP3 */
4395 case 0xf7:
4396 if ((b & 1) == 0)
4397 ot = OT_BYTE;
4398 else
4399 ot = dflag + OT_WORD;
4400
4401 modrm = ldub_code(s->pc++);
4402 mod = (modrm >> 6) & 3;
4403 rm = (modrm & 7) | REX_B(s)0;
4404 op = (modrm >> 3) & 7;
4405 if (mod != 3) {
4406 if (op == 0)
4407 s->rip_offset = insn_const_size(ot);
4408 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4409 gen_op_ld_T0_A0(ot + s->mem_index);
4410 } else {
4411 gen_op_mov_TN_reg(ot, 0, rm);
4412 }
4413
4414 switch(op) {
4415 case 0: /* test */
4416 val = insn_get(s, ot);
4417 gen_op_movl_T1_im(val);
4418 gen_op_testl_T0_T1_cc();
4419 s->cc_op = CC_OP_LOGICB + ot;
4420 break;
4421 case 2: /* not */
4422 tcg_gen_not_tltcg_gen_not_i32(cpu_T[0], cpu_T[0]);
4423 if (mod != 3) {
4424 gen_op_st_T0_A0(ot + s->mem_index);
4425 } else {
4426 gen_op_mov_reg_T0(ot, rm);
4427 }
4428 break;
4429 case 3: /* neg */
4430 tcg_gen_neg_tltcg_gen_neg_i32(cpu_T[0], cpu_T[0]);
4431 if (mod != 3) {
4432 gen_op_st_T0_A0(ot + s->mem_index);
4433 } else {
4434 gen_op_mov_reg_T0(ot, rm);
4435 }
4436 gen_op_update_neg_cc();
4437 s->cc_op = CC_OP_SUBB + ot;
4438 break;
4439 case 4: /* mul */
4440 switch(ot) {
4441 case OT_BYTE:
4442 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX0);
4443 tcg_gen_ext8u_tltcg_gen_ext8u_i32(cpu_T[0], cpu_T[0]);
4444 tcg_gen_ext8u_tltcg_gen_ext8u_i32(cpu_T[1], cpu_T[1]);
4445 /* XXX: use 32 bit mul which could be faster */
4446 tcg_gen_mul_tltcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
4447 gen_op_mov_reg_T0(OT_WORD, R_EAX0);
4448 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
4449 tcg_gen_andi_tltcg_gen_andi_i32(cpu_cc_src, cpu_T[0], 0xff00);
4450 s->cc_op = CC_OP_MULB;
4451 break;
4452 case OT_WORD:
4453 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX0);
4454 tcg_gen_ext16u_tltcg_gen_ext16u_i32(cpu_T[0], cpu_T[0]);
4455 tcg_gen_ext16u_tltcg_gen_ext16u_i32(cpu_T[1], cpu_T[1]);
4456 /* XXX: use 32 bit mul which could be faster */
4457 tcg_gen_mul_tltcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
4458 gen_op_mov_reg_T0(OT_WORD, R_EAX0);
4459 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
4460 tcg_gen_shri_tltcg_gen_shri_i32(cpu_T[0], cpu_T[0], 16);
4461 gen_op_mov_reg_T0(OT_WORD, R_EDX2);
4462 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_src, cpu_T[0]);
4463 s->cc_op = CC_OP_MULW;
4464 break;
4465 default:
4466 case OT_LONG:
4467#ifdef TARGET_X86_64
4468 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX0);
4469 tcg_gen_ext32u_tltcg_gen_mov_i32(cpu_T[0], cpu_T[0]);
4470 tcg_gen_ext32u_tltcg_gen_mov_i32(cpu_T[1], cpu_T[1]);
4471 tcg_gen_mul_tltcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
4472 gen_op_mov_reg_T0(OT_LONG, R_EAX0);
4473 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
4474 tcg_gen_shri_tltcg_gen_shri_i32(cpu_T[0], cpu_T[0], 32);
4475 gen_op_mov_reg_T0(OT_LONG, R_EDX2);
4476 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_src, cpu_T[0]);
4477#else
4478 {
4479 TCGv_i64 t0, t1;
4480 t0 = tcg_temp_new_i64();
4481 t1 = tcg_temp_new_i64();
4482 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX0);
4483 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4484 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4485 tcg_gen_mul_i64(t0, t0, t1);
4486 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4487 gen_op_mov_reg_T0(OT_LONG, R_EAX0);
4488 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
4489 tcg_gen_shri_i64(t0, t0, 32);
4490 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4491 gen_op_mov_reg_T0(OT_LONG, R_EDX2);
4492 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_src, cpu_T[0]);
4493 }
4494#endif
4495 s->cc_op = CC_OP_MULL;
4496 break;
4497#ifdef TARGET_X86_64
4498 case OT_QUAD:
4499 gen_helper_mulq_EAX_T0(cpu_T[0]);
4500 s->cc_op = CC_OP_MULQ;
4501 break;
4502#endif
4503 }
4504 break;
4505 case 5: /* imul */
4506 switch(ot) {
4507 case OT_BYTE:
4508 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX0);
4509 tcg_gen_ext8s_tltcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]);
4510 tcg_gen_ext8s_tltcg_gen_ext8s_i32(cpu_T[1], cpu_T[1]);
4511 /* XXX: use 32 bit mul which could be faster */
4512 tcg_gen_mul_tltcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
4513 gen_op_mov_reg_T0(OT_WORD, R_EAX0);
4514 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
4515 tcg_gen_ext8s_tltcg_gen_ext8s_i32(cpu_tmp0, cpu_T[0]);
4516 tcg_gen_sub_tltcg_gen_sub_i32(cpu_cc_src, cpu_T[0], cpu_tmp0);
4517 s->cc_op = CC_OP_MULB;
4518 break;
4519 case OT_WORD:
4520 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX0);
4521 tcg_gen_ext16s_tltcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
4522 tcg_gen_ext16s_tltcg_gen_ext16s_i32(cpu_T[1], cpu_T[1]);
4523 /* XXX: use 32 bit mul which could be faster */
4524 tcg_gen_mul_tltcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
4525 gen_op_mov_reg_T0(OT_WORD, R_EAX0);
4526 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
4527 tcg_gen_ext16s_tltcg_gen_ext16s_i32(cpu_tmp0, cpu_T[0]);
4528 tcg_gen_sub_tltcg_gen_sub_i32(cpu_cc_src, cpu_T[0], cpu_tmp0);
4529 tcg_gen_shri_tltcg_gen_shri_i32(cpu_T[0], cpu_T[0], 16);
4530 gen_op_mov_reg_T0(OT_WORD, R_EDX2);
4531 s->cc_op = CC_OP_MULW;
4532 break;
4533 default:
4534 case OT_LONG:
4535#ifdef TARGET_X86_64
4536 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX0);
4537 tcg_gen_ext32s_tltcg_gen_mov_i32(cpu_T[0], cpu_T[0]);
4538 tcg_gen_ext32s_tltcg_gen_mov_i32(cpu_T[1], cpu_T[1]);
4539 tcg_gen_mul_tltcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
4540 gen_op_mov_reg_T0(OT_LONG, R_EAX0);
4541 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
4542 tcg_gen_ext32s_tltcg_gen_mov_i32(cpu_tmp0, cpu_T[0]);
4543 tcg_gen_sub_tltcg_gen_sub_i32(cpu_cc_src, cpu_T[0], cpu_tmp0);
4544 tcg_gen_shri_tltcg_gen_shri_i32(cpu_T[0], cpu_T[0], 32);
4545 gen_op_mov_reg_T0(OT_LONG, R_EDX2);
4546#else
4547 {
4548 TCGv_i64 t0, t1;
4549 t0 = tcg_temp_new_i64();
4550 t1 = tcg_temp_new_i64();
4551 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX0);
4552 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4553 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4554 tcg_gen_mul_i64(t0, t0, t1);
4555 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4556 gen_op_mov_reg_T0(OT_LONG, R_EAX0);
4557 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
4558 tcg_gen_sari_tltcg_gen_sari_i32(cpu_tmp0, cpu_T[0], 31);
4559 tcg_gen_shri_i64(t0, t0, 32);
4560 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4561 gen_op_mov_reg_T0(OT_LONG, R_EDX2);
4562 tcg_gen_sub_tltcg_gen_sub_i32(cpu_cc_src, cpu_T[0], cpu_tmp0);
4563 }
4564#endif
4565 s->cc_op = CC_OP_MULL;
4566 break;
4567#ifdef TARGET_X86_64
4568 case OT_QUAD:
4569 gen_helper_imulq_EAX_T0(cpu_T[0]);
4570 s->cc_op = CC_OP_MULQ;
4571 break;
4572#endif
4573 }
4574 break;
4575 case 6: /* div */
4576 switch(ot) {
4577 case OT_BYTE:
4578 gen_jmp_im(pc_start - s->cs_base);
4579 gen_helper_divb_AL(cpu_T[0]);
4580 break;
4581 case OT_WORD:
4582 gen_jmp_im(pc_start - s->cs_base);
4583 gen_helper_divw_AX(cpu_T[0]);
4584 break;
4585 default:
4586 case OT_LONG:
4587 gen_jmp_im(pc_start - s->cs_base);
4588 gen_helper_divl_EAX(cpu_T[0]);
4589 break;
4590#ifdef TARGET_X86_64
4591 case OT_QUAD:
4592 gen_jmp_im(pc_start - s->cs_base);
4593 gen_helper_divq_EAX(cpu_T[0]);
4594 break;
4595#endif
4596 }
4597 break;
4598 case 7: /* idiv */
4599 switch(ot) {
4600 case OT_BYTE:
4601 gen_jmp_im(pc_start - s->cs_base);
4602 gen_helper_idivb_AL(cpu_T[0]);
4603 break;
4604 case OT_WORD:
4605 gen_jmp_im(pc_start - s->cs_base);
4606 gen_helper_idivw_AX(cpu_T[0]);
4607 break;
4608 default:
4609 case OT_LONG:
4610 gen_jmp_im(pc_start - s->cs_base);
4611 gen_helper_idivl_EAX(cpu_T[0]);
4612 break;
4613#ifdef TARGET_X86_64
4614 case OT_QUAD:
4615 gen_jmp_im(pc_start - s->cs_base);
4616 gen_helper_idivq_EAX(cpu_T[0]);
4617 break;
4618#endif
4619 }
4620 break;
4621 default:
4622 goto illegal_op;
4623 }
4624 break;
4625
4626 case 0xfe: /* GRP4 */
4627 case 0xff: /* GRP5 */
4628 if ((b & 1) == 0)
4629 ot = OT_BYTE;
4630 else
4631 ot = dflag + OT_WORD;
4632
4633 modrm = ldub_code(s->pc++);
4634 mod = (modrm >> 6) & 3;
4635 rm = (modrm & 7) | REX_B(s)0;
4636 op = (modrm >> 3) & 7;
4637 if (op >= 2 && b == 0xfe) {
4638 goto illegal_op;
4639 }
4640 if (CODE64(s)0) {
4641 if (op == 2 || op == 4) {
4642 /* operand size for jumps is 64 bit */
4643 ot = OT_QUAD;
4644 } else if (op == 3 || op == 5) {
4645 ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD;
4646 } else if (op == 6) {
4647 /* default push size is 64 bit */
4648 ot = dflag ? OT_QUAD : OT_WORD;
4649 }
4650 }
4651 if (mod != 3) {
4652 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4653 if (op >= 2 && op != 3 && op != 5)
4654 gen_op_ld_T0_A0(ot + s->mem_index);
4655 } else {
4656 gen_op_mov_TN_reg(ot, 0, rm);
4657 }
4658
4659 switch(op) {
4660 case 0: /* inc Ev */
4661 if (mod != 3)
4662 opreg = OR_TMP0;
4663 else
4664 opreg = rm;
4665 gen_inc(s, ot, opreg, 1);
4666 break;
4667 case 1: /* dec Ev */
4668 if (mod != 3)
4669 opreg = OR_TMP0;
4670 else
4671 opreg = rm;
4672 gen_inc(s, ot, opreg, -1);
4673 break;
4674 case 2: /* call Ev */
4675 /* XXX: optimize if memory (no 'and' is necessary) */
4676 if (s->dflag == 0)
4677 gen_op_andl_T0_ffff();
4678 next_eip = s->pc - s->cs_base;
4679 gen_movtl_T1_im(next_eip);
4680 gen_push_T1(s);
4681 gen_op_jmp_T0();
4682 gen_eob(s);
4683 break;
4684 case 3: /* lcall Ev */
4685 gen_op_ld_T1_A0(ot + s->mem_index);
4686 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4687 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4688 do_lcall:
4689 if (s->pe && !s->vm86) {
4690 if (s->cc_op != CC_OP_DYNAMIC)
4691 gen_op_set_cc_op(s->cc_op);
4692 gen_jmp_im(pc_start - s->cs_base);
4693 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
4694 gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1],
4695 tcg_const_i32(dflag),
4696 tcg_const_i32(s->pc - pc_start));
4697 } else {
4698 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
4699 gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1],
4700 tcg_const_i32(dflag),
4701 tcg_const_i32(s->pc - s->cs_base));
4702 }
4703 gen_eob(s);
4704 break;
4705 case 4: /* jmp Ev */
4706 if (s->dflag == 0)
4707 gen_op_andl_T0_ffff();
4708 gen_op_jmp_T0();
4709 gen_eob(s);
4710 break;
4711 case 5: /* ljmp Ev */
4712 gen_op_ld_T1_A0(ot + s->mem_index);
4713 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4714 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4715 do_ljmp:
4716 if (s->pe && !s->vm86) {
4717 if (s->cc_op != CC_OP_DYNAMIC)
4718 gen_op_set_cc_op(s->cc_op);
4719 gen_jmp_im(pc_start - s->cs_base);
4720 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
4721 gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1],
4722 tcg_const_i32(s->pc - pc_start));
4723 } else {
4724 gen_op_movl_seg_T0_vm(R_CS1);
4725 gen_op_movl_T0_T1();
4726 gen_op_jmp_T0();
4727 }
4728 gen_eob(s);
4729 break;
4730 case 6: /* push Ev */
4731 gen_push_T0(s);
4732 break;
4733 default:
4734 goto illegal_op;
4735 }
4736 break;
4737
4738 case 0x84: /* test Ev, Gv */
4739 case 0x85:
4740 if ((b & 1) == 0)
4741 ot = OT_BYTE;
4742 else
4743 ot = dflag + OT_WORD;
4744
4745 modrm = ldub_code(s->pc++);
4746 reg = ((modrm >> 3) & 7) | rex_r;
4747
4748 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4749 gen_op_mov_TN_reg(ot, 1, reg);
4750 gen_op_testl_T0_T1_cc();
4751 s->cc_op = CC_OP_LOGICB + ot;
4752 break;
4753
4754 case 0xa8: /* test eAX, Iv */
4755 case 0xa9:
4756 if ((b & 1) == 0)
4757 ot = OT_BYTE;
4758 else
4759 ot = dflag + OT_WORD;
4760 val = insn_get(s, ot);
4761
4762 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4763 gen_op_movl_T1_im(val);
4764 gen_op_testl_T0_T1_cc();
4765 s->cc_op = CC_OP_LOGICB + ot;
4766 break;
4767
4768 case 0x98: /* CWDE/CBW */
4769#ifdef TARGET_X86_64
4770 if (dflag == 2) {
4771 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX0);
4772 tcg_gen_ext32s_tltcg_gen_mov_i32(cpu_T[0], cpu_T[0]);
4773 gen_op_mov_reg_T0(OT_QUAD, R_EAX0);
4774 } else
4775#endif
4776 if (dflag == 1) {
4777 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX0);
4778 tcg_gen_ext16s_tltcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
4779 gen_op_mov_reg_T0(OT_LONG, R_EAX0);
4780 } else {
4781 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX0);
4782 tcg_gen_ext8s_tltcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]);
4783 gen_op_mov_reg_T0(OT_WORD, R_EAX0);
4784 }
4785 break;
4786 case 0x99: /* CDQ/CWD */
4787#ifdef TARGET_X86_64
4788 if (dflag == 2) {
4789 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX0);
4790 tcg_gen_sari_tltcg_gen_sari_i32(cpu_T[0], cpu_T[0], 63);
4791 gen_op_mov_reg_T0(OT_QUAD, R_EDX2);
4792 } else
4793#endif
4794 if (dflag == 1) {
4795 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX0);
4796 tcg_gen_ext32s_tltcg_gen_mov_i32(cpu_T[0], cpu_T[0]);
4797 tcg_gen_sari_tltcg_gen_sari_i32(cpu_T[0], cpu_T[0], 31);
4798 gen_op_mov_reg_T0(OT_LONG, R_EDX2);
4799 } else {
4800 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX0);
4801 tcg_gen_ext16s_tltcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
4802 tcg_gen_sari_tltcg_gen_sari_i32(cpu_T[0], cpu_T[0], 15);
4803 gen_op_mov_reg_T0(OT_WORD, R_EDX2);
4804 }
4805 break;
4806 case 0x1af: /* imul Gv, Ev */
4807 case 0x69: /* imul Gv, Ev, I */
4808 case 0x6b:
4809 ot = dflag + OT_WORD;
4810 modrm = ldub_code(s->pc++);
4811 reg = ((modrm >> 3) & 7) | rex_r;
4812 if (b == 0x69)
4813 s->rip_offset = insn_const_size(ot);
4814 else if (b == 0x6b)
4815 s->rip_offset = 1;
4816 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4817 if (b == 0x69) {
4818 val = insn_get(s, ot);
4819 gen_op_movl_T1_im(val);
4820 } else if (b == 0x6b) {
4821 val = (int8_t)insn_get(s, OT_BYTE);
4822 gen_op_movl_T1_im(val);
4823 } else {
4824 gen_op_mov_TN_reg(ot, 1, reg);
4825 }
4826
4827#ifdef TARGET_X86_64
4828 if (ot == OT_QUAD) {
4829 gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]);
4830 } else
4831#endif
4832 if (ot == OT_LONG) {
4833#ifdef TARGET_X86_64
4834 tcg_gen_ext32s_tltcg_gen_mov_i32(cpu_T[0], cpu_T[0]);
4835 tcg_gen_ext32s_tltcg_gen_mov_i32(cpu_T[1], cpu_T[1]);
4836 tcg_gen_mul_tltcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
4837 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
4838 tcg_gen_ext32s_tltcg_gen_mov_i32(cpu_tmp0, cpu_T[0]);
4839 tcg_gen_sub_tltcg_gen_sub_i32(cpu_cc_src, cpu_T[0], cpu_tmp0);
4840#else
4841 {
4842 TCGv_i64 t0, t1;
4843 t0 = tcg_temp_new_i64();
4844 t1 = tcg_temp_new_i64();
4845 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4846 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4847 tcg_gen_mul_i64(t0, t0, t1);
4848 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4849 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
4850 tcg_gen_sari_tltcg_gen_sari_i32(cpu_tmp0, cpu_T[0], 31);
4851 tcg_gen_shri_i64(t0, t0, 32);
4852 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4853 tcg_gen_sub_tltcg_gen_sub_i32(cpu_cc_src, cpu_T[1], cpu_tmp0);
4854 }
4855#endif
4856 } else {
4857 tcg_gen_ext16s_tltcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
4858 tcg_gen_ext16s_tltcg_gen_ext16s_i32(cpu_T[1], cpu_T[1]);
4859 /* XXX: use 32 bit mul which could be faster */
4860 tcg_gen_mul_tltcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
4861 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, cpu_T[0]);
4862 tcg_gen_ext16s_tltcg_gen_ext16s_i32(cpu_tmp0, cpu_T[0]);
4863 tcg_gen_sub_tltcg_gen_sub_i32(cpu_cc_src, cpu_T[0], cpu_tmp0);
4864 }
4865 gen_op_mov_reg_T0(ot, reg);
4866 s->cc_op = CC_OP_MULB + ot;
4867 break;
4868 case 0x1c0:
4869 case 0x1c1: /* xadd Ev, Gv */
4870 if ((b & 1) == 0)
4871 ot = OT_BYTE;
4872 else
4873 ot = dflag + OT_WORD;
4874 modrm = ldub_code(s->pc++);
4875 reg = ((modrm >> 3) & 7) | rex_r;
4876 mod = (modrm >> 6) & 3;
4877 if (mod == 3) {
4878 rm = (modrm & 7) | REX_B(s)0;
4879 gen_op_mov_TN_reg(ot, 0, reg);
4880 gen_op_mov_TN_reg(ot, 1, rm);
4881 gen_op_addl_T0_T1();
4882 gen_op_mov_reg_T1(ot, reg);
4883 gen_op_mov_reg_T0(ot, rm);
4884 } else {
4885 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4886 gen_op_mov_TN_reg(ot, 0, reg);
4887 gen_op_ld_T1_A0(ot + s->mem_index);
4888 gen_op_addl_T0_T1();
4889 gen_op_st_T0_A0(ot + s->mem_index);
4890 gen_op_mov_reg_T1(ot, reg);
4891 }
4892 gen_op_update2_cc();
4893 s->cc_op = CC_OP_ADDB + ot;
4894 break;
4895 case 0x1b0:
4896 case 0x1b1: /* cmpxchg Ev, Gv */
4897 {
4898 int label1, label2;
4899 TCGvTCGv_i32 t0, t1, t2, a0;
4900
4901 if ((b & 1) == 0)
4902 ot = OT_BYTE;
4903 else
4904 ot = dflag + OT_WORD;
4905 modrm = ldub_code(s->pc++);
4906 reg = ((modrm >> 3) & 7) | rex_r;
4907 mod = (modrm >> 6) & 3;
4908 t0 = tcg_temp_local_new()tcg_temp_local_new_i32();
4909 t1 = tcg_temp_local_new()tcg_temp_local_new_i32();
4910 t2 = tcg_temp_local_new()tcg_temp_local_new_i32();
4911 a0 = tcg_temp_local_new()tcg_temp_local_new_i32();
4912 gen_op_mov_v_reg(ot, t1, reg);
4913 if (mod == 3) {
4914 rm = (modrm & 7) | REX_B(s)0;
4915 gen_op_mov_v_reg(ot, t0, rm);
4916 } else {
4917 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4918 tcg_gen_mov_tltcg_gen_mov_i32(a0, cpu_A0);
4919 gen_op_ld_v(ot + s->mem_index, t0, a0);
4920 rm = 0; /* avoid warning */
4921 }
4922 label1 = gen_new_label();
4923 tcg_gen_sub_tltcg_gen_sub_i32(t2, cpu_regs[R_EAX0], t0);
4924 gen_extu(ot, t2);
4925 tcg_gen_brcondi_tltcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, label1);
4926 label2 = gen_new_label();
4927 if (mod == 3) {
4928 gen_op_mov_reg_v(ot, R_EAX0, t0);
4929 tcg_gen_br(label2);
4930 gen_set_label(label1);
4931 gen_op_mov_reg_v(ot, rm, t1);
4932 } else {
4933 /* perform no-op store cycle like physical cpu; must be
4934 before changing accumulator to ensure idempotency if
4935 the store faults and the instruction is restarted */
4936 gen_op_st_v(ot + s->mem_index, t0, a0);
4937 gen_op_mov_reg_v(ot, R_EAX0, t0);
4938 tcg_gen_br(label2);
4939 gen_set_label(label1);
4940 gen_op_st_v(ot + s->mem_index, t1, a0);
4941 }
4942 gen_set_label(label2);
4943 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_src, t0);
4944 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_dst, t2);
4945 s->cc_op = CC_OP_SUBB + ot;
4946 tcg_temp_freetcg_temp_free_i32(t0);
4947 tcg_temp_freetcg_temp_free_i32(t1);
4948 tcg_temp_freetcg_temp_free_i32(t2);
4949 tcg_temp_freetcg_temp_free_i32(a0);
4950 }
4951 break;
4952 case 0x1c7: /* cmpxchg8b */
4953 modrm = ldub_code(s->pc++);
4954 mod = (modrm >> 6) & 3;
4955 if ((mod == 3) || ((modrm & 0x38) != 0x8))
4956 goto illegal_op;
4957#ifdef TARGET_X86_64
4958 if (dflag == 2) {
4959 if (!(s->cpuid_ext_features & CPUID_EXT_CX16(1 << 13)))
4960 goto illegal_op;
4961 gen_jmp_im(pc_start - s->cs_base);
4962 if (s->cc_op != CC_OP_DYNAMIC)
4963 gen_op_set_cc_op(s->cc_op);
4964 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4965 gen_helper_cmpxchg16b(cpu_A0);
4966 } else
4967#endif
4968 {
4969 if (!(s->cpuid_features & CPUID_CX8(1 << 8)))
4970 goto illegal_op;
4971 gen_jmp_im(pc_start - s->cs_base);
4972 if (s->cc_op != CC_OP_DYNAMIC)
4973 gen_op_set_cc_op(s->cc_op);
4974 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4975 gen_helper_cmpxchg8b(cpu_A0);
4976 }
4977 s->cc_op = CC_OP_EFLAGS;
4978 break;
4979
4980 /**************************/
4981 /* push/pop */
4982 case 0x50 ... 0x57: /* push */
4983 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s)0);
4984 gen_push_T0(s);
4985 break;
4986 case 0x58 ... 0x5f: /* pop */
4987 if (CODE64(s)0) {
4988 ot = dflag ? OT_QUAD : OT_WORD;
4989 } else {
4990 ot = dflag + OT_WORD;
4991 }
4992 gen_pop_T0(s);
4993 /* NOTE: order is important for pop %sp */
4994 gen_pop_update(s);
4995 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s)0);
4996 break;
4997 case 0x60: /* pusha */
4998 if (CODE64(s)0)
4999 goto illegal_op;
5000 gen_pusha(s);
5001 break;
5002 case 0x61: /* popa */
5003 if (CODE64(s)0)
5004 goto illegal_op;
5005 gen_popa(s);
5006 break;
5007 case 0x68: /* push Iv */
5008 case 0x6a:
5009 if (CODE64(s)0) {
5010 ot = dflag ? OT_QUAD : OT_WORD;
5011 } else {
5012 ot = dflag + OT_WORD;
5013 }
5014 if (b == 0x68)
5015 val = insn_get(s, ot);
5016 else
5017 val = (int8_t)insn_get(s, OT_BYTE);
5018 gen_op_movl_T0_im(val);
5019 gen_push_T0(s);
5020 break;
5021 case 0x8f: /* pop Ev */
5022 if (CODE64(s)0) {
5023 ot = dflag ? OT_QUAD : OT_WORD;
5024 } else {
5025 ot = dflag + OT_WORD;
5026 }
5027 modrm = ldub_code(s->pc++);
5028 mod = (modrm >> 6) & 3;
5029 gen_pop_T0(s);
5030 if (mod == 3) {
5031 /* NOTE: order is important for pop %sp */
5032 gen_pop_update(s);
5033 rm = (modrm & 7) | REX_B(s)0;
5034 gen_op_mov_reg_T0(ot, rm);
5035 } else {
5036 /* NOTE: order is important too for MMU exceptions */
5037 s->popl_esp_hack = 1 << ot;
5038 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5039 s->popl_esp_hack = 0;
5040 gen_pop_update(s);
5041 }
5042 break;
5043 case 0xc8: /* enter */
5044 {
5045 int level;
5046 val = lduw_code(s->pc);
5047 s->pc += 2;
5048 level = ldub_code(s->pc++);
5049 gen_enter(s, val, level);
5050 }
5051 break;
5052 case 0xc9: /* leave */
5053 /* XXX: exception not precise (ESP is updated before potential exception) */
5054 if (CODE64(s)0) {
5055 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP5);
5056 gen_op_mov_reg_T0(OT_QUAD, R_ESP4);
5057 } else if (s->ss32) {
5058 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP5);
5059 gen_op_mov_reg_T0(OT_LONG, R_ESP4);
5060 } else {
5061 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP5);
5062 gen_op_mov_reg_T0(OT_WORD, R_ESP4);
5063 }
5064 gen_pop_T0(s);
5065 if (CODE64(s)0) {
5066 ot = dflag ? OT_QUAD : OT_WORD;
5067 } else {
5068 ot = dflag + OT_WORD;
5069 }
5070 gen_op_mov_reg_T0(ot, R_EBP5);
5071 gen_pop_update(s);
5072 break;
5073 case 0x06: /* push es */
5074 case 0x0e: /* push cs */
5075 case 0x16: /* push ss */
5076 case 0x1e: /* push ds */
5077 if (CODE64(s)0)
5078 goto illegal_op;
5079 gen_op_movl_T0_seg(b >> 3);
5080 gen_push_T0(s);
5081 break;
5082 case 0x1a0: /* push fs */
5083 case 0x1a8: /* push gs */
5084 gen_op_movl_T0_seg((b >> 3) & 7);
5085 gen_push_T0(s);
5086 break;
5087 case 0x07: /* pop es */
5088 case 0x17: /* pop ss */
5089 case 0x1f: /* pop ds */
5090 if (CODE64(s)0)
5091 goto illegal_op;
5092 reg = b >> 3;
5093 gen_pop_T0(s);
5094 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5095 gen_pop_update(s);
5096 if (reg == R_SS2) {
5097 /* if reg == SS, inhibit interrupts/trace. */
5098 /* If several instructions disable interrupts, only the
5099 _first_ does it */
5100 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK(1 << 3)))
5101 gen_helper_set_inhibit_irq();
5102 s->tf = 0;
5103 }
5104 if (s->is_jmp) {
5105 gen_jmp_im(s->pc - s->cs_base);
5106 gen_eob(s);
5107 }
5108 break;
5109 case 0x1a1: /* pop fs */
5110 case 0x1a9: /* pop gs */
5111 gen_pop_T0(s);
5112 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
5113 gen_pop_update(s);
5114 if (s->is_jmp) {
5115 gen_jmp_im(s->pc - s->cs_base);
5116 gen_eob(s);
5117 }
5118 break;
5119
5120 /**************************/
5121 /* mov */
5122 case 0x88:
5123 case 0x89: /* mov Gv, Ev */
5124 if ((b & 1) == 0)
5125 ot = OT_BYTE;
5126 else
5127 ot = dflag + OT_WORD;
5128 modrm = ldub_code(s->pc++);
5129 reg = ((modrm >> 3) & 7) | rex_r;
5130
5131 /* generate a generic store */
5132 gen_ldst_modrm(s, modrm, ot, reg, 1);
5133 break;
5134 case 0xc6:
5135 case 0xc7: /* mov Ev, Iv */
5136 if ((b & 1) == 0)
5137 ot = OT_BYTE;
5138 else
5139 ot = dflag + OT_WORD;
5140 modrm = ldub_code(s->pc++);
5141 mod = (modrm >> 6) & 3;
5142 if (mod != 3) {
5143 s->rip_offset = insn_const_size(ot);
5144 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5145 }
5146 val = insn_get(s, ot);
5147 gen_op_movl_T0_im(val);
5148 if (mod != 3)
5149 gen_op_st_T0_A0(ot + s->mem_index);
5150 else
5151 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s)0);
5152 break;
5153 case 0x8a:
5154 case 0x8b: /* mov Ev, Gv */
5155 if ((b & 1) == 0)
5156 ot = OT_BYTE;
5157 else
5158 ot = OT_WORD + dflag;
5159 modrm = ldub_code(s->pc++);
5160 reg = ((modrm >> 3) & 7) | rex_r;
5161
5162 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5163 gen_op_mov_reg_T0(ot, reg);
5164 break;
5165 case 0x8e: /* mov seg, Gv */
5166 modrm = ldub_code(s->pc++);
5167 reg = (modrm >> 3) & 7;
5168 if (reg >= 6 || reg == R_CS1)
5169 goto illegal_op;
5170 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5171 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5172 if (reg == R_SS2) {
5173 /* if reg == SS, inhibit interrupts/trace */
5174 /* If several instructions disable interrupts, only the
5175 _first_ does it */
5176 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK(1 << 3)))
5177 gen_helper_set_inhibit_irq();
5178 s->tf = 0;
5179 }
5180 if (s->is_jmp) {
5181 gen_jmp_im(s->pc - s->cs_base);
5182 gen_eob(s);
5183 }
5184 break;
5185 case 0x8c: /* mov Gv, seg */
5186 modrm = ldub_code(s->pc++);
5187 reg = (modrm >> 3) & 7;
5188 mod = (modrm >> 6) & 3;
5189 if (reg >= 6)
5190 goto illegal_op;
5191 gen_op_movl_T0_seg(reg);
5192 if (mod == 3)
5193 ot = OT_WORD + dflag;
5194 else
5195 ot = OT_WORD;
5196 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5197 break;
5198
5199 case 0x1b6: /* movzbS Gv, Eb */
5200 case 0x1b7: /* movzwS Gv, Eb */
5201 case 0x1be: /* movsbS Gv, Eb */
5202 case 0x1bf: /* movswS Gv, Eb */
5203 {
5204 int d_ot;
5205 /* d_ot is the size of destination */
5206 d_ot = dflag + OT_WORD;
5207 /* ot is the size of source */
5208 ot = (b & 1) + OT_BYTE;
5209 modrm = ldub_code(s->pc++);
5210 reg = ((modrm >> 3) & 7) | rex_r;
5211 mod = (modrm >> 6) & 3;
5212 rm = (modrm & 7) | REX_B(s)0;
5213
5214 if (mod == 3) {
5215 gen_op_mov_TN_reg(ot, 0, rm);
5216 switch(ot | (b & 8)) {
5217 case OT_BYTE:
5218 tcg_gen_ext8u_tltcg_gen_ext8u_i32(cpu_T[0], cpu_T[0]);
5219 break;
5220 case OT_BYTE | 8:
5221 tcg_gen_ext8s_tltcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]);
5222 break;
5223 case OT_WORD:
5224 tcg_gen_ext16u_tltcg_gen_ext16u_i32(cpu_T[0], cpu_T[0]);
5225 break;
5226 default:
5227 case OT_WORD | 8:
5228 tcg_gen_ext16s_tltcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
5229 break;
5230 }
5231 gen_op_mov_reg_T0(d_ot, reg);
5232 } else {
5233 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5234 if (b & 8) {
5235 gen_op_lds_T0_A0(ot + s->mem_index);
5236 } else {
5237 gen_op_ldu_T0_A0(ot + s->mem_index);
5238 }
5239 gen_op_mov_reg_T0(d_ot, reg);
5240 }
5241 }
5242 break;
5243
5244 case 0x8d: /* lea */
5245 ot = dflag + OT_WORD;
5246 modrm = ldub_code(s->pc++);
5247 mod = (modrm >> 6) & 3;
5248 if (mod == 3)
5249 goto illegal_op;
5250 reg = ((modrm >> 3) & 7) | rex_r;
5251 /* we must ensure that no segment is added */
5252 s->override = -1;
5253 val = s->addseg;
5254 s->addseg = 0;
5255 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5256 s->addseg = val;
5257 gen_op_mov_reg_A0(ot - OT_WORD, reg);
5258 break;
5259
5260 case 0xa0: /* mov EAX, Ov */
5261 case 0xa1:
5262 case 0xa2: /* mov Ov, EAX */
5263 case 0xa3:
5264 {
5265 target_ulong offset_addr;
5266
5267 if ((b & 1) == 0)
5268 ot = OT_BYTE;
5269 else
5270 ot = dflag + OT_WORD;
5271#ifdef TARGET_X86_64
5272 if (s->aflag == 2) {
5273 offset_addr = ldq_code(s->pc);
5274 s->pc += 8;
5275 gen_op_movq_A0_im(offset_addr);
5276 } else
5277#endif
5278 {
5279 if (s->aflag) {
5280 offset_addr = insn_get(s, OT_LONG);
5281 } else {
5282 offset_addr = insn_get(s, OT_WORD);
5283 }
5284 gen_op_movl_A0_im(offset_addr);
5285 }
5286 gen_add_A0_ds_seg(s);
5287 if ((b & 2) == 0) {
5288 gen_op_ld_T0_A0(ot + s->mem_index);
5289 gen_op_mov_reg_T0(ot, R_EAX0);
5290 } else {
5291 gen_op_mov_TN_reg(ot, 0, R_EAX0);
5292 gen_op_st_T0_A0(ot + s->mem_index);
5293 }
5294 }
5295 break;
5296 case 0xd7: /* xlat */
5297#ifdef TARGET_X86_64
5298 if (s->aflag == 2) {
5299 gen_op_movq_A0_reg(R_EBX3);
5300 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX0);
5301 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
5302 tcg_gen_add_tltcg_gen_add_i32(cpu_A0, cpu_A0, cpu_T[0]);
5303 } else
5304#endif
5305 {
5306 gen_op_movl_A0_reg(R_EBX3);
5307 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX0);
5308 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
5309 tcg_gen_add_tltcg_gen_add_i32(cpu_A0, cpu_A0, cpu_T[0]);
5310 if (s->aflag == 0)
5311 gen_op_andl_A0_ffff();
5312 else
5313 tcg_gen_andi_tltcg_gen_andi_i32(cpu_A0, cpu_A0, 0xffffffff);
5314 }
5315 gen_add_A0_ds_seg(s);
5316 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
5317 gen_op_mov_reg_T0(OT_BYTE, R_EAX0);
5318 break;
5319 case 0xb0 ... 0xb7: /* mov R, Ib */
5320 val = insn_get(s, OT_BYTE);
5321 gen_op_movl_T0_im(val);
5322 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s)0);
5323 break;
5324 case 0xb8 ... 0xbf: /* mov R, Iv */
5325#ifdef TARGET_X86_64
5326 if (dflag == 2) {
5327 uint64_t tmp;
5328 /* 64 bit case */
5329 tmp = ldq_code(s->pc);
5330 s->pc += 8;
5331 reg = (b & 7) | REX_B(s)0;
5332 gen_movtl_T0_im(tmp);
5333 gen_op_mov_reg_T0(OT_QUAD, reg);
5334 } else
5335#endif
5336 {
5337 ot = dflag ? OT_LONG : OT_WORD;
5338 val = insn_get(s, ot);
5339 reg = (b & 7) | REX_B(s)0;
5340 gen_op_movl_T0_im(val);
5341 gen_op_mov_reg_T0(ot, reg);
5342 }
5343 break;
5344
5345 case 0x91 ... 0x97: /* xchg R, EAX */
5346 do_xchg_reg_eax:
5347 ot = dflag + OT_WORD;
5348 reg = (b & 7) | REX_B(s)0;
5349 rm = R_EAX0;
5350 goto do_xchg_reg;
5351 case 0x86:
5352 case 0x87: /* xchg Ev, Gv */
5353 if ((b & 1) == 0)
5354 ot = OT_BYTE;
5355 else
5356 ot = dflag + OT_WORD;
5357 modrm = ldub_code(s->pc++);
5358 reg = ((modrm >> 3) & 7) | rex_r;
5359 mod = (modrm >> 6) & 3;
5360 if (mod == 3) {
5361 rm = (modrm & 7) | REX_B(s)0;
5362 do_xchg_reg:
5363 gen_op_mov_TN_reg(ot, 0, reg);
5364 gen_op_mov_TN_reg(ot, 1, rm);
5365 gen_op_mov_reg_T0(ot, rm);
5366 gen_op_mov_reg_T1(ot, reg);
5367 } else {
5368 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5369 gen_op_mov_TN_reg(ot, 0, reg);
5370 /* for xchg, lock is implicit */
5371 if (!(prefixes & PREFIX_LOCK0x04))
5372 gen_helper_lock();
5373 gen_op_ld_T1_A0(ot + s->mem_index);
5374 gen_op_st_T0_A0(ot + s->mem_index);
5375 if (!(prefixes & PREFIX_LOCK0x04))
5376 gen_helper_unlock();
5377 gen_op_mov_reg_T1(ot, reg);
5378 }
5379 break;
5380 case 0xc4: /* les Gv */
5381 if (CODE64(s)0)
5382 goto illegal_op;
5383 op = R_ES0;
5384 goto do_lxx;
5385 case 0xc5: /* lds Gv */
5386 if (CODE64(s)0)
5387 goto illegal_op;
5388 op = R_DS3;
5389 goto do_lxx;
5390 case 0x1b2: /* lss Gv */
5391 op = R_SS2;
5392 goto do_lxx;
5393 case 0x1b4: /* lfs Gv */
5394 op = R_FS4;
5395 goto do_lxx;
5396 case 0x1b5: /* lgs Gv */
5397 op = R_GS5;
5398 do_lxx:
5399 ot = dflag ? OT_LONG : OT_WORD;
5400 modrm = ldub_code(s->pc++);
5401 reg = ((modrm >> 3) & 7) | rex_r;
5402 mod = (modrm >> 6) & 3;
5403 if (mod == 3)
5404 goto illegal_op;
5405 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5406 gen_op_ld_T1_A0(ot + s->mem_index);
5407 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
5408 /* load the segment first to handle exceptions properly */
5409 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
5410 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5411 /* then put the data */
5412 gen_op_mov_reg_T1(ot, reg);
5413 if (s->is_jmp) {
5414 gen_jmp_im(s->pc - s->cs_base);
5415 gen_eob(s);
5416 }
5417 break;
5418
5419 /************************/
5420 /* shifts */
5421 case 0xc0:
5422 case 0xc1:
5423 /* shift Ev,Ib */
5424 shift = 2;
5425 grp2:
5426 {
5427 if ((b & 1) == 0)
5428 ot = OT_BYTE;
5429 else
5430 ot = dflag + OT_WORD;
5431
5432 modrm = ldub_code(s->pc++);
5433 mod = (modrm >> 6) & 3;
5434 op = (modrm >> 3) & 7;
5435
5436 if (mod != 3) {
5437 if (shift == 2) {
5438 s->rip_offset = 1;
5439 }
5440 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5441 opreg = OR_TMP0;
5442 } else {
5443 opreg = (modrm & 7) | REX_B(s)0;
5444 }
5445
5446 /* simpler op */
5447 if (shift == 0) {
5448 gen_shift(s, op, ot, opreg, OR_ECX);
5449 } else {
5450 if (shift == 2) {
5451 shift = ldub_code(s->pc++);
5452 }
5453 gen_shifti(s, op, ot, opreg, shift);
5454 }
5455 }
5456 break;
5457 case 0xd0:
5458 case 0xd1:
5459 /* shift Ev,1 */
5460 shift = 1;
5461 goto grp2;
5462 case 0xd2:
5463 case 0xd3:
5464 /* shift Ev,cl */
5465 shift = 0;
5466 goto grp2;
5467
5468 case 0x1a4: /* shld imm */
5469 op = 0;
5470 shift = 1;
5471 goto do_shiftd;
5472 case 0x1a5: /* shld cl */
5473 op = 0;
5474 shift = 0;
5475 goto do_shiftd;
5476 case 0x1ac: /* shrd imm */
5477 op = 1;
5478 shift = 1;
5479 goto do_shiftd;
5480 case 0x1ad: /* shrd cl */
5481 op = 1;
5482 shift = 0;
5483 do_shiftd:
5484 ot = dflag + OT_WORD;
5485 modrm = ldub_code(s->pc++);
5486 mod = (modrm >> 6) & 3;
5487 rm = (modrm & 7) | REX_B(s)0;
5488 reg = ((modrm >> 3) & 7) | rex_r;
5489 if (mod != 3) {
5490 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5491 opreg = OR_TMP0;
5492 } else {
5493 opreg = rm;
5494 }
5495 gen_op_mov_TN_reg(ot, 1, reg);
5496
5497 if (shift) {
5498 val = ldub_code(s->pc++);
5499 tcg_gen_movi_tltcg_gen_movi_i32(cpu_T3, val);
5500 } else {
5501 tcg_gen_mov_tltcg_gen_mov_i32(cpu_T3, cpu_regs[R_ECX1]);
5502 }
5503 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
5504 break;
5505
5506 /************************/
5507 /* floats */
5508 case 0xd8 ... 0xdf:
5509 if (s->flags & (HF_EM_MASK(1 << 10) | HF_TS_MASK(1 << 11))) {
5510 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5511 /* XXX: what to do if illegal op ? */
5512 gen_exception(s, EXCP07_PREX7, pc_start - s->cs_base);
5513 break;
5514 }
5515 modrm = ldub_code(s->pc++);
5516 mod = (modrm >> 6) & 3;
5517 rm = modrm & 7;
5518 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5519 if (mod != 3) {
5520 /* memory op */
5521 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5522 switch(op) {
5523 case 0x00 ... 0x07: /* fxxxs */
5524 case 0x10 ... 0x17: /* fixxxl */
5525 case 0x20 ... 0x27: /* fxxxl */
5526 case 0x30 ... 0x37: /* fixxx */
5527 {
5528 int op1;
5529 op1 = op & 7;
5530
5531 switch(op >> 4) {
5532 case 0:
5533 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5534 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
5535 gen_helper_flds_FT0(cpu_tmp2_i32);
5536 break;
5537 case 1:
5538 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5539 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
5540 gen_helper_fildl_FT0(cpu_tmp2_i32);
5541 break;
5542 case 2:
5543 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5544 (s->mem_index >> 2) - 1);
5545 gen_helper_fldl_FT0(cpu_tmp1_i64);
5546 break;
5547 case 3:
5548 default:
5549 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5550 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
5551 gen_helper_fildl_FT0(cpu_tmp2_i32);
5552 break;
5553 }
5554
5555 gen_helper_fp_arith_ST0_FT0(op1);
5556 if (op1 == 3) {
5557 /* fcomp needs pop */
5558 gen_helper_fpop();
5559 }
5560 }
5561 break;
5562 case 0x08: /* flds */
5563 case 0x0a: /* fsts */
5564 case 0x0b: /* fstps */
5565 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5566 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5567 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5568 switch(op & 7) {
5569 case 0:
5570 switch(op >> 4) {
5571 case 0:
5572 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5573 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
5574 gen_helper_flds_ST0(cpu_tmp2_i32);
5575 break;
5576 case 1:
5577 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5578 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
5579 gen_helper_fildl_ST0(cpu_tmp2_i32);
5580 break;
5581 case 2:
5582 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5583 (s->mem_index >> 2) - 1);
5584 gen_helper_fldl_ST0(cpu_tmp1_i64);
5585 break;
5586 case 3:
5587 default:
5588 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5589 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
5590 gen_helper_fildl_ST0(cpu_tmp2_i32);
5591 break;
5592 }
5593 break;
5594 case 1:
5595 /* XXX: the corresponding CPUID bit must be tested ! */
5596 switch(op >> 4) {
5597 case 1:
5598 gen_helper_fisttl_ST0(cpu_tmp2_i32);
5599 tcg_gen_extu_i32_tltcg_gen_mov_i32(cpu_T[0], cpu_tmp2_i32);
5600 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5601 break;
5602 case 2:
5603 gen_helper_fisttll_ST0(cpu_tmp1_i64);
5604 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5605 (s->mem_index >> 2) - 1);
5606 break;
5607 case 3:
5608 default:
5609 gen_helper_fistt_ST0(cpu_tmp2_i32);
5610 tcg_gen_extu_i32_tltcg_gen_mov_i32(cpu_T[0], cpu_tmp2_i32);
5611 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5612 break;
5613 }
5614 gen_helper_fpop();
5615 break;
5616 default:
5617 switch(op >> 4) {
5618 case 0:
5619 gen_helper_fsts_ST0(cpu_tmp2_i32);
5620 tcg_gen_extu_i32_tltcg_gen_mov_i32(cpu_T[0], cpu_tmp2_i32);
5621 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5622 break;
5623 case 1:
5624 gen_helper_fistl_ST0(cpu_tmp2_i32);
5625 tcg_gen_extu_i32_tltcg_gen_mov_i32(cpu_T[0], cpu_tmp2_i32);
5626 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5627 break;
5628 case 2:
5629 gen_helper_fstl_ST0(cpu_tmp1_i64);
5630 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5631 (s->mem_index >> 2) - 1);
5632 break;
5633 case 3:
5634 default:
5635 gen_helper_fist_ST0(cpu_tmp2_i32);
5636 tcg_gen_extu_i32_tltcg_gen_mov_i32(cpu_T[0], cpu_tmp2_i32);
5637 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5638 break;
5639 }
5640 if ((op & 7) == 3)
5641 gen_helper_fpop();
5642 break;
5643 }
5644 break;
5645 case 0x0c: /* fldenv mem */
5646 if (s->cc_op != CC_OP_DYNAMIC)
5647 gen_op_set_cc_op(s->cc_op);
5648 gen_jmp_im(pc_start - s->cs_base);
5649 gen_helper_fldenv(
5650 cpu_A0, tcg_const_i32(s->dflag));
5651 break;
5652 case 0x0d: /* fldcw mem */
5653 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5654 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
5655 gen_helper_fldcw(cpu_tmp2_i32);
5656 break;
5657 case 0x0e: /* fnstenv mem */
5658 if (s->cc_op != CC_OP_DYNAMIC)
5659 gen_op_set_cc_op(s->cc_op);
5660 gen_jmp_im(pc_start - s->cs_base);
5661 gen_helper_fstenv(cpu_A0, tcg_const_i32(s->dflag));
5662 break;
5663 case 0x0f: /* fnstcw mem */
5664 gen_helper_fnstcw(cpu_tmp2_i32);
5665 tcg_gen_extu_i32_tltcg_gen_mov_i32(cpu_T[0], cpu_tmp2_i32);
5666 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5667 break;
5668 case 0x1d: /* fldt mem */
5669 if (s->cc_op != CC_OP_DYNAMIC)
5670 gen_op_set_cc_op(s->cc_op);
5671 gen_jmp_im(pc_start - s->cs_base);
5672 gen_helper_fldt_ST0(cpu_A0);
5673 break;
5674 case 0x1f: /* fstpt mem */
5675 if (s->cc_op != CC_OP_DYNAMIC)
5676 gen_op_set_cc_op(s->cc_op);
5677 gen_jmp_im(pc_start - s->cs_base);
5678 gen_helper_fstt_ST0(cpu_A0);
5679 gen_helper_fpop();
5680 break;
5681 case 0x2c: /* frstor mem */
5682 if (s->cc_op != CC_OP_DYNAMIC)
5683 gen_op_set_cc_op(s->cc_op);
5684 gen_jmp_im(pc_start - s->cs_base);
5685 gen_helper_frstor(cpu_A0, tcg_const_i32(s->dflag));
5686 break;
5687 case 0x2e: /* fnsave mem */
5688 if (s->cc_op != CC_OP_DYNAMIC)
5689 gen_op_set_cc_op(s->cc_op);
5690 gen_jmp_im(pc_start - s->cs_base);
5691 gen_helper_fsave(cpu_A0, tcg_const_i32(s->dflag));
5692 break;
5693 case 0x2f: /* fnstsw mem */
5694 gen_helper_fnstsw(cpu_tmp2_i32);
5695 tcg_gen_extu_i32_tltcg_gen_mov_i32(cpu_T[0], cpu_tmp2_i32);
5696 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5697 break;
5698 case 0x3c: /* fbld */
5699 if (s->cc_op != CC_OP_DYNAMIC)
5700 gen_op_set_cc_op(s->cc_op);
5701 gen_jmp_im(pc_start - s->cs_base);
5702 gen_helper_fbld_ST0(cpu_A0);
5703 break;
5704 case 0x3e: /* fbstp */
5705 if (s->cc_op != CC_OP_DYNAMIC)
5706 gen_op_set_cc_op(s->cc_op);
5707 gen_jmp_im(pc_start - s->cs_base);
5708 gen_helper_fbst_ST0(cpu_A0);
5709 gen_helper_fpop();
5710 break;
5711 case 0x3d: /* fildll */
5712 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5713 (s->mem_index >> 2) - 1);
5714 gen_helper_fildll_ST0(cpu_tmp1_i64);
5715 break;
5716 case 0x3f: /* fistpll */
5717 gen_helper_fistll_ST0(cpu_tmp1_i64);
5718 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5719 (s->mem_index >> 2) - 1);
5720 gen_helper_fpop();
5721 break;
5722 default:
5723 goto illegal_op;
5724 }
5725 } else {
5726 /* register float ops */
5727 opreg = rm;
5728
5729 switch(op) {
5730 case 0x08: /* fld sti */
5731 gen_helper_fpush();
5732 gen_helper_fmov_ST0_STN(tcg_const_i32((opreg + 1) & 7));
5733 break;
5734 case 0x09: /* fxchg sti */
5735 case 0x29: /* fxchg4 sti, undocumented op */
5736 case 0x39: /* fxchg7 sti, undocumented op */
5737 gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg));
5738 break;
5739 case 0x0a: /* grp d9/2 */
5740 switch(rm) {
5741 case 0: /* fnop */
5742 /* check exceptions (FreeBSD FPU probe) */
5743 if (s->cc_op != CC_OP_DYNAMIC)
5744 gen_op_set_cc_op(s->cc_op);
5745 gen_jmp_im(pc_start - s->cs_base);
5746 gen_helper_fwait();
5747 break;
5748 default:
5749 goto illegal_op;
5750 }
5751 break;
5752 case 0x0c: /* grp d9/4 */
5753 switch(rm) {
5754 case 0: /* fchs */
5755 gen_helper_fchs_ST0();
5756 break;
5757 case 1: /* fabs */
5758 gen_helper_fabs_ST0();
5759 break;
5760 case 4: /* ftst */
5761 gen_helper_fldz_FT0();
5762 gen_helper_fcom_ST0_FT0();
5763 break;
5764 case 5: /* fxam */
5765 gen_helper_fxam_ST0();
5766 break;
5767 default:
5768 goto illegal_op;
5769 }
5770 break;
5771 case 0x0d: /* grp d9/5 */
5772 {
5773 switch(rm) {
5774 case 0:
5775 gen_helper_fpush();
5776 gen_helper_fld1_ST0();
5777 break;
5778 case 1:
5779 gen_helper_fpush();
5780 gen_helper_fldl2t_ST0();
5781 break;
5782 case 2:
5783 gen_helper_fpush();
5784 gen_helper_fldl2e_ST0();
5785 break;
5786 case 3:
5787 gen_helper_fpush();
5788 gen_helper_fldpi_ST0();
5789 break;
5790 case 4:
5791 gen_helper_fpush();
5792 gen_helper_fldlg2_ST0();
5793 break;
5794 case 5:
5795 gen_helper_fpush();
5796 gen_helper_fldln2_ST0();
5797 break;
5798 case 6:
5799 gen_helper_fpush();
5800 gen_helper_fldz_ST0();
5801 break;
5802 default:
5803 goto illegal_op;
5804 }
5805 }
5806 break;
5807 case 0x0e: /* grp d9/6 */
5808 switch(rm) {
5809 case 0: /* f2xm1 */
5810 gen_helper_f2xm1();
5811 break;
5812 case 1: /* fyl2x */
5813 gen_helper_fyl2x();
5814 break;
5815 case 2: /* fptan */
5816 gen_helper_fptan();
5817 break;
5818 case 3: /* fpatan */
5819 gen_helper_fpatan();
5820 break;
5821 case 4: /* fxtract */
5822 gen_helper_fxtract();
5823 break;
5824 case 5: /* fprem1 */
5825 gen_helper_fprem1();
5826 break;
5827 case 6: /* fdecstp */
5828 gen_helper_fdecstp();
5829 break;
5830 default:
5831 case 7: /* fincstp */
5832 gen_helper_fincstp();
5833 break;
5834 }
5835 break;
5836 case 0x0f: /* grp d9/7 */
5837 switch(rm) {
5838 case 0: /* fprem */
5839 gen_helper_fprem();
5840 break;
5841 case 1: /* fyl2xp1 */
5842 gen_helper_fyl2xp1();
5843 break;
5844 case 2: /* fsqrt */
5845 gen_helper_fsqrt();
5846 break;
5847 case 3: /* fsincos */
5848 gen_helper_fsincos();
5849 break;
5850 case 5: /* fscale */
5851 gen_helper_fscale();
5852 break;
5853 case 4: /* frndint */
5854 gen_helper_frndint();
5855 break;
5856 case 6: /* fsin */
5857 gen_helper_fsin();
5858 break;
5859 default:
5860 case 7: /* fcos */
5861 gen_helper_fcos();
5862 break;
5863 }
5864 break;
5865 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5866 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5867 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5868 {
5869 int op1;
5870
5871 op1 = op & 7;
5872 if (op >= 0x20) {
5873 gen_helper_fp_arith_STN_ST0(op1, opreg);
5874 if (op >= 0x30)
5875 gen_helper_fpop();
5876 } else {
5877 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5878 gen_helper_fp_arith_ST0_FT0(op1);
5879 }
5880 }
5881 break;
5882 case 0x02: /* fcom */
5883 case 0x22: /* fcom2, undocumented op */
5884 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5885 gen_helper_fcom_ST0_FT0();
5886 break;
5887 case 0x03: /* fcomp */
5888 case 0x23: /* fcomp3, undocumented op */
5889 case 0x32: /* fcomp5, undocumented op */
5890 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5891 gen_helper_fcom_ST0_FT0();
5892 gen_helper_fpop();
5893 break;
5894 case 0x15: /* da/5 */
5895 switch(rm) {
5896 case 1: /* fucompp */
5897 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5898 gen_helper_fucom_ST0_FT0();
5899 gen_helper_fpop();
5900 gen_helper_fpop();
5901 break;
5902 default:
5903 goto illegal_op;
5904 }
5905 break;
5906 case 0x1c:
5907 switch(rm) {
5908 case 0: /* feni (287 only, just do nop here) */
5909 break;
5910 case 1: /* fdisi (287 only, just do nop here) */
5911 break;
5912 case 2: /* fclex */
5913 gen_helper_fclex();
5914 break;
5915 case 3: /* fninit */
5916 gen_helper_fninit();
5917 break;
5918 case 4: /* fsetpm (287 only, just do nop here) */
5919 break;
5920 default:
5921 goto illegal_op;
5922 }
5923 break;
5924 case 0x1d: /* fucomi */
5925 if (s->cc_op != CC_OP_DYNAMIC)
5926 gen_op_set_cc_op(s->cc_op);
5927 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5928 gen_helper_fucomi_ST0_FT0();
5929 s->cc_op = CC_OP_EFLAGS;
5930 break;
5931 case 0x1e: /* fcomi */
5932 if (s->cc_op != CC_OP_DYNAMIC)
5933 gen_op_set_cc_op(s->cc_op);
5934 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5935 gen_helper_fcomi_ST0_FT0();
5936 s->cc_op = CC_OP_EFLAGS;
5937 break;
5938 case 0x28: /* ffree sti */
5939 gen_helper_ffree_STN(tcg_const_i32(opreg));
5940 break;
5941 case 0x2a: /* fst sti */
5942 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5943 break;
5944 case 0x2b: /* fstp sti */
5945 case 0x0b: /* fstp1 sti, undocumented op */
5946 case 0x3a: /* fstp8 sti, undocumented op */
5947 case 0x3b: /* fstp9 sti, undocumented op */
5948 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5949 gen_helper_fpop();
5950 break;
5951 case 0x2c: /* fucom st(i) */
5952 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5953 gen_helper_fucom_ST0_FT0();
5954 break;
5955 case 0x2d: /* fucomp st(i) */
5956 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5957 gen_helper_fucom_ST0_FT0();
5958 gen_helper_fpop();
5959 break;
5960 case 0x33: /* de/3 */
5961 switch(rm) {
5962 case 1: /* fcompp */
5963 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5964 gen_helper_fcom_ST0_FT0();
5965 gen_helper_fpop();
5966 gen_helper_fpop();
5967 break;
5968 default:
5969 goto illegal_op;
5970 }
5971 break;
5972 case 0x38: /* ffreep sti, undocumented op */
5973 gen_helper_ffree_STN(tcg_const_i32(opreg));
5974 gen_helper_fpop();
5975 break;
5976 case 0x3c: /* df/4 */
5977 switch(rm) {
5978 case 0:
5979 gen_helper_fnstsw(cpu_tmp2_i32);
5980 tcg_gen_extu_i32_tltcg_gen_mov_i32(cpu_T[0], cpu_tmp2_i32);
5981 gen_op_mov_reg_T0(OT_WORD, R_EAX0);
5982 break;
5983 default:
5984 goto illegal_op;
5985 }
5986 break;
5987 case 0x3d: /* fucomip */
5988 if (s->cc_op != CC_OP_DYNAMIC)
5989 gen_op_set_cc_op(s->cc_op);
5990 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5991 gen_helper_fucomi_ST0_FT0();
5992 gen_helper_fpop();
5993 s->cc_op = CC_OP_EFLAGS;
5994 break;
5995 case 0x3e: /* fcomip */
5996 if (s->cc_op != CC_OP_DYNAMIC)
5997 gen_op_set_cc_op(s->cc_op);
5998 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5999 gen_helper_fcomi_ST0_FT0();
6000 gen_helper_fpop();
6001 s->cc_op = CC_OP_EFLAGS;
6002 break;
6003 case 0x10 ... 0x13: /* fcmovxx */
6004 case 0x18 ... 0x1b:
6005 {
6006 int op1, l1;
6007 static const uint8_t fcmov_cc[8] = {
6008 (JCC_B << 1),
6009 (JCC_Z << 1),
6010 (JCC_BE << 1),
6011 (JCC_P << 1),
6012 };
6013 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
6014 l1 = gen_new_label();
6015 gen_jcc1(s, s->cc_op, op1, l1);
6016 gen_helper_fmov_ST0_STN(tcg_const_i32(opreg));
6017 gen_set_label(l1);
6018 }
6019 break;
6020 default:
6021 goto illegal_op;
6022 }
6023 }
6024 break;
6025 /************************/
6026 /* string ops */
6027
6028 case 0xa4: /* movsS */
6029 case 0xa5:
6030 if ((b & 1) == 0)
6031 ot = OT_BYTE;
6032 else
6033 ot = dflag + OT_WORD;
6034
6035 if (prefixes & (PREFIX_REPZ0x01 | PREFIX_REPNZ0x02)) {
6036 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6037 } else {
6038 gen_movs(s, ot);
6039 }
6040 break;
6041
6042 case 0xaa: /* stosS */
6043 case 0xab:
6044 if ((b & 1) == 0)
6045 ot = OT_BYTE;
6046 else
6047 ot = dflag + OT_WORD;
6048
6049 if (prefixes & (PREFIX_REPZ0x01 | PREFIX_REPNZ0x02)) {
6050 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6051 } else {
6052 gen_stos(s, ot);
6053 }
6054 break;
6055 case 0xac: /* lodsS */
6056 case 0xad:
6057 if ((b & 1) == 0)
6058 ot = OT_BYTE;
6059 else
6060 ot = dflag + OT_WORD;
6061 if (prefixes & (PREFIX_REPZ0x01 | PREFIX_REPNZ0x02)) {
6062 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6063 } else {
6064 gen_lods(s, ot);
6065 }
6066 break;
6067 case 0xae: /* scasS */
6068 case 0xaf:
6069 if ((b & 1) == 0)
6070 ot = OT_BYTE;
6071 else
6072 ot = dflag + OT_WORD;
6073 if (prefixes & PREFIX_REPNZ0x02) {
6074 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6075 } else if (prefixes & PREFIX_REPZ0x01) {
6076 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6077 } else {
6078 gen_scas(s, ot);
6079 s->cc_op = CC_OP_SUBB + ot;
6080 }
6081 break;
6082
6083 case 0xa6: /* cmpsS */
6084 case 0xa7:
6085 if ((b & 1) == 0)
6086 ot = OT_BYTE;
6087 else
6088 ot = dflag + OT_WORD;
6089 if (prefixes & PREFIX_REPNZ0x02) {
6090 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6091 } else if (prefixes & PREFIX_REPZ0x01) {
6092 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6093 } else {
6094 gen_cmps(s, ot);
6095 s->cc_op = CC_OP_SUBB + ot;
6096 }
6097 break;
6098 case 0x6c: /* insS */
6099 case 0x6d:
6100 if ((b & 1) == 0)
6101 ot = OT_BYTE;
6102 else
6103 ot = dflag ? OT_LONG : OT_WORD;
6104 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX2);
6105 gen_op_andl_T0_ffff();
6106 gen_check_io(s, ot, pc_start - s->cs_base,
6107 SVM_IOIO_TYPE_MASK1 | svm_is_rep(prefixes) | 4);
6108 if (prefixes & (PREFIX_REPZ0x01 | PREFIX_REPNZ0x02)) {
6109 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6110 } else {
6111 gen_ins(s, ot);
6112 if (use_icount) {
6113 gen_jmp(s, s->pc - s->cs_base);
6114 }
6115 }
6116 break;
6117 case 0x6e: /* outsS */
6118 case 0x6f:
6119 if ((b & 1) == 0)
6120 ot = OT_BYTE;
6121 else
6122 ot = dflag ? OT_LONG : OT_WORD;
6123 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX2);
6124 gen_op_andl_T0_ffff();
6125 gen_check_io(s, ot, pc_start - s->cs_base,
6126 svm_is_rep(prefixes) | 4);
6127 if (prefixes & (PREFIX_REPZ0x01 | PREFIX_REPNZ0x02)) {
6128 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6129 } else {
6130 gen_outs(s, ot);
6131 if (use_icount) {
6132 gen_jmp(s, s->pc - s->cs_base);
6133 }
6134 }
6135 break;
6136
6137 /************************/
6138 /* port I/O */
6139
6140 case 0xe4:
6141 case 0xe5:
6142 if ((b & 1) == 0)
6143 ot = OT_BYTE;
6144 else
6145 ot = dflag ? OT_LONG : OT_WORD;
6146 val = ldub_code(s->pc++);
6147 gen_op_movl_T0_im(val);
6148 gen_check_io(s, ot, pc_start - s->cs_base,
6149 SVM_IOIO_TYPE_MASK1 | svm_is_rep(prefixes));
6150 if (use_icount)
6151 gen_io_start();
6152 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
6153 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6154 gen_op_mov_reg_T1(ot, R_EAX0);
6155 if (use_icount) {
6156 gen_io_end();
6157 gen_jmp(s, s->pc - s->cs_base);
6158 }
6159 break;
6160 case 0xe6:
6161 case 0xe7:
6162 if ((b & 1) == 0)
6163 ot = OT_BYTE;
6164 else
6165 ot = dflag ? OT_LONG : OT_WORD;
6166 val = ldub_code(s->pc++);
6167 gen_op_movl_T0_im(val);
6168 gen_check_io(s, ot, pc_start - s->cs_base,
6169 svm_is_rep(prefixes));
6170 gen_op_mov_TN_reg(ot, 1, R_EAX0);
6171
6172 if (use_icount)
6173 gen_io_start();
6174 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
6175 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp3_i32, cpu_T[1]);
6176 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6177 if (use_icount) {
6178 gen_io_end();
6179 gen_jmp(s, s->pc - s->cs_base);
6180 }
6181 break;
6182 case 0xec:
6183 case 0xed:
6184 if ((b & 1) == 0)
6185 ot = OT_BYTE;
6186 else
6187 ot = dflag ? OT_LONG : OT_WORD;
6188 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX2);
6189 gen_op_andl_T0_ffff();
6190 gen_check_io(s, ot, pc_start - s->cs_base,
6191 SVM_IOIO_TYPE_MASK1 | svm_is_rep(prefixes));
6192 if (use_icount)
6193 gen_io_start();
6194 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
6195 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6196 gen_op_mov_reg_T1(ot, R_EAX0);
6197 if (use_icount) {
6198 gen_io_end();
6199 gen_jmp(s, s->pc - s->cs_base);
6200 }
6201 break;
6202 case 0xee:
6203 case 0xef:
6204 if ((b & 1) == 0)
6205 ot = OT_BYTE;
6206 else
6207 ot = dflag ? OT_LONG : OT_WORD;
6208 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX2);
6209 gen_op_andl_T0_ffff();
6210 gen_check_io(s, ot, pc_start - s->cs_base,
6211 svm_is_rep(prefixes));
6212 gen_op_mov_TN_reg(ot, 1, R_EAX0);
6213
6214 if (use_icount)
6215 gen_io_start();
6216 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
6217 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp3_i32, cpu_T[1]);
6218 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6219 if (use_icount) {
6220 gen_io_end();
6221 gen_jmp(s, s->pc - s->cs_base);
6222 }
6223 break;
6224
6225 /************************/
6226 /* control */
6227 case 0xc2: /* ret im */
6228 val = ldsw_code(s->pc);
6229 s->pc += 2;
6230 gen_pop_T0(s);
6231 if (CODE64(s)0 && s->dflag)
6232 s->dflag = 2;
6233 gen_stack_update(s, val + (2 << s->dflag));
6234 if (s->dflag == 0)
6235 gen_op_andl_T0_ffff();
6236 gen_op_jmp_T0();
6237 gen_eob(s);
6238 break;
6239 case 0xc3: /* ret */
6240 gen_pop_T0(s);
6241 gen_pop_update(s);
6242 if (s->dflag == 0)
6243 gen_op_andl_T0_ffff();
6244 gen_op_jmp_T0();
6245 gen_eob(s);
6246 break;
6247 case 0xca: /* lret im */
6248 val = ldsw_code(s->pc);
6249 s->pc += 2;
6250 do_lret:
6251 if (s->pe && !s->vm86) {
6252 if (s->cc_op != CC_OP_DYNAMIC)
6253 gen_op_set_cc_op(s->cc_op);
6254 gen_jmp_im(pc_start - s->cs_base);
6255 gen_helper_lret_protected(tcg_const_i32(s->dflag),
6256 tcg_const_i32(val));
6257 } else {
6258 gen_stack_A0(s);
6259 /* pop offset */
6260 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6261 if (s->dflag == 0)
6262 gen_op_andl_T0_ffff();
6263 /* NOTE: keeping EIP updated is not a problem in case of
6264 exception */
6265 gen_op_jmp_T0();
6266 /* pop selector */
6267 gen_op_addl_A0_im(2 << s->dflag);
6268 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6269 gen_op_movl_seg_T0_vm(R_CS1);
6270 /* add stack offset */
6271 gen_stack_update(s, val + (4 << s->dflag));
6272 }
6273 gen_eob(s);
6274 break;
6275 case 0xcb: /* lret */
6276 val = 0;
6277 goto do_lret;
6278 case 0xcf: /* iret */
6279 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET0x074);
6280 if (!s->pe) {
6281 /* real mode */
6282 gen_helper_iret_real(tcg_const_i32(s->dflag));
6283 s->cc_op = CC_OP_EFLAGS;
6284 } else if (s->vm86) {
6285 if (s->iopl != 3) {
6286 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
6287 } else {
6288 gen_helper_iret_real(tcg_const_i32(s->dflag));
6289 s->cc_op = CC_OP_EFLAGS;
6290 }
6291 } else {
6292 if (s->cc_op != CC_OP_DYNAMIC)
6293 gen_op_set_cc_op(s->cc_op);
6294 gen_jmp_im(pc_start - s->cs_base);
6295 gen_helper_iret_protected(tcg_const_i32(s->dflag),
6296 tcg_const_i32(s->pc - s->cs_base));
6297 s->cc_op = CC_OP_EFLAGS;
6298 }
6299 gen_eob(s);
6300 break;
6301 case 0xe8: /* call im */
6302 {
6303 if (dflag)
6304 tval = (int32_t)insn_get(s, OT_LONG);
6305 else
6306 tval = (int16_t)insn_get(s, OT_WORD);
6307 next_eip = s->pc - s->cs_base;
6308 tval += next_eip;
6309 if (s->dflag == 0)
6310 tval &= 0xffff;
6311 else if(!CODE64(s)0)
6312 tval &= 0xffffffff;
6313 gen_movtl_T0_im(next_eip);
6314 gen_push_T0(s);
6315 gen_jmp(s, tval);
6316 }
6317 break;
6318 case 0x9a: /* lcall im */
6319 {
6320 unsigned int selector, offset;
6321
6322 if (CODE64(s)0)
6323 goto illegal_op;
6324 ot = dflag ? OT_LONG : OT_WORD;
6325 offset = insn_get(s, ot);
6326 selector = insn_get(s, OT_WORD);
6327
6328 gen_op_movl_T0_im(selector);
6329 gen_op_movl_T1_imu(offset);
6330 }
6331 goto do_lcall;
6332 case 0xe9: /* jmp im */
6333 if (dflag)
6334 tval = (int32_t)insn_get(s, OT_LONG);
6335 else
6336 tval = (int16_t)insn_get(s, OT_WORD);
6337 tval += s->pc - s->cs_base;
6338 if (s->dflag == 0)
6339 tval &= 0xffff;
6340 else if(!CODE64(s)0)
6341 tval &= 0xffffffff;
6342 gen_jmp(s, tval);
6343 break;
6344 case 0xea: /* ljmp im */
6345 {
6346 unsigned int selector, offset;
6347
6348 if (CODE64(s)0)
6349 goto illegal_op;
6350 ot = dflag ? OT_LONG : OT_WORD;
6351 offset = insn_get(s, ot);
6352 selector = insn_get(s, OT_WORD);
6353
6354 gen_op_movl_T0_im(selector);
6355 gen_op_movl_T1_imu(offset);
6356 }
6357 goto do_ljmp;
6358 case 0xeb: /* jmp Jb */
6359 tval = (int8_t)insn_get(s, OT_BYTE);
6360 tval += s->pc - s->cs_base;
6361 if (s->dflag == 0)
6362 tval &= 0xffff;
6363 gen_jmp(s, tval);
6364 break;
6365 case 0x70 ... 0x7f: /* jcc Jb */
6366 tval = (int8_t)insn_get(s, OT_BYTE);
6367 goto do_jcc;
6368 case 0x180 ... 0x18f: /* jcc Jv */
6369 if (dflag) {
6370 tval = (int32_t)insn_get(s, OT_LONG);
6371 } else {
6372 tval = (int16_t)insn_get(s, OT_WORD);
6373 }
6374 do_jcc:
6375 next_eip = s->pc - s->cs_base;
6376 tval += next_eip;
6377 if (s->dflag == 0)
6378 tval &= 0xffff;
6379 gen_jcc(s, b, tval, next_eip);
6380 break;
6381
6382 case 0x190 ... 0x19f: /* setcc Gv */
6383 modrm = ldub_code(s->pc++);
6384 gen_setcc(s, b);
6385 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
6386 break;
6387 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6388 {
6389 int l1;
6390 TCGvTCGv_i32 t0;
6391
6392 ot = dflag + OT_WORD;
6393 modrm = ldub_code(s->pc++);
6394 reg = ((modrm >> 3) & 7) | rex_r;
6395 mod = (modrm >> 6) & 3;
6396 t0 = tcg_temp_local_new()tcg_temp_local_new_i32();
6397 if (mod != 3) {
6398 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6399 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
6400 } else {
6401 rm = (modrm & 7) | REX_B(s)0;
6402 gen_op_mov_v_reg(ot, t0, rm);
6403 }
6404#ifdef TARGET_X86_64
6405 if (ot == OT_LONG) {
6406 /* XXX: specific Intel behaviour ? */
6407 l1 = gen_new_label();
6408 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6409 tcg_gen_mov_tltcg_gen_mov_i32(cpu_regs[reg], t0);
6410 gen_set_label(l1);
6411 tcg_gen_ext32u_tltcg_gen_mov_i32(cpu_regs[reg], cpu_regs[reg]);
6412 } else
6413#endif
6414 {
6415 l1 = gen_new_label();
6416 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6417 gen_op_mov_reg_v(ot, reg, t0);
6418 gen_set_label(l1);
6419 }
6420 tcg_temp_freetcg_temp_free_i32(t0);
6421 }
6422 break;
6423
6424 /************************/
6425 /* flags */
6426 case 0x9c: /* pushf */
6427 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF0x070);
6428 if (s->vm86 && s->iopl != 3) {
6429 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
6430 } else {
6431 if (s->cc_op != CC_OP_DYNAMIC)
6432 gen_op_set_cc_op(s->cc_op);
6433 gen_helper_read_eflags(cpu_T[0]);
6434 gen_push_T0(s);
6435 }
6436 break;
6437 case 0x9d: /* popf */
6438 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF0x071);
6439 if (s->vm86 && s->iopl != 3) {
6440 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
6441 } else {
6442 gen_pop_T0(s);
6443 if (s->cpl == 0) {
6444 if (s->dflag) {
6445 gen_helper_write_eflags(cpu_T[0],
6446 tcg_const_i32((TF_MASK0x00000100 | AC_MASK0x00040000 | ID_MASK0x00200000 | NT_MASK0x00004000 | IF_MASK0x00000200 | IOPL_MASK0x00003000)));
6447 } else {
6448 gen_helper_write_eflags(cpu_T[0],
6449 tcg_const_i32((TF_MASK0x00000100 | AC_MASK0x00040000 | ID_MASK0x00200000 | NT_MASK0x00004000 | IF_MASK0x00000200 | IOPL_MASK0x00003000) & 0xffff));
6450 }
6451 } else {
6452 if (s->cpl <= s->iopl) {
6453 if (s->dflag) {
6454 gen_helper_write_eflags(cpu_T[0],
6455 tcg_const_i32((TF_MASK0x00000100 | AC_MASK0x00040000 | ID_MASK0x00200000 | NT_MASK0x00004000 | IF_MASK0x00000200)));
6456 } else {
6457 gen_helper_write_eflags(cpu_T[0],
6458 tcg_const_i32((TF_MASK0x00000100 | AC_MASK0x00040000 | ID_MASK0x00200000 | NT_MASK0x00004000 | IF_MASK0x00000200) & 0xffff));
6459 }
6460 } else {
6461 if (s->dflag) {
6462 gen_helper_write_eflags(cpu_T[0],
6463 tcg_const_i32((TF_MASK0x00000100 | AC_MASK0x00040000 | ID_MASK0x00200000 | NT_MASK0x00004000)));
6464 } else {
6465 gen_helper_write_eflags(cpu_T[0],
6466 tcg_const_i32((TF_MASK0x00000100 | AC_MASK0x00040000 | ID_MASK0x00200000 | NT_MASK0x00004000) & 0xffff));
6467 }
6468 }
6469 }
6470 gen_pop_update(s);
6471 s->cc_op = CC_OP_EFLAGS;
6472 /* abort translation because TF flag may change */
6473 gen_jmp_im(s->pc - s->cs_base);
6474 gen_eob(s);
6475 }
6476 break;
6477 case 0x9e: /* sahf */
6478 if (CODE64(s)0 && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM(1 << 0)))
6479 goto illegal_op;
6480 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH4);
6481 if (s->cc_op != CC_OP_DYNAMIC)
6482 gen_op_set_cc_op(s->cc_op);
6483 gen_compute_eflags(cpu_cc_src);
6484 tcg_gen_andi_tltcg_gen_andi_i32(cpu_cc_src, cpu_cc_src, CC_O0x0800);
6485 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[0], cpu_T[0], CC_S0x0080 | CC_Z0x0040 | CC_A0x0010 | CC_P0x0004 | CC_C0x0001);
6486 tcg_gen_or_tltcg_gen_or_i32(cpu_cc_src, cpu_cc_src, cpu_T[0]);
6487 s->cc_op = CC_OP_EFLAGS;
6488 break;
6489 case 0x9f: /* lahf */
6490 if (CODE64(s)0 && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM(1 << 0)))
6491 goto illegal_op;
6492 if (s->cc_op != CC_OP_DYNAMIC)
6493 gen_op_set_cc_op(s->cc_op);
6494 gen_compute_eflags(cpu_T[0]);
6495 /* Note: gen_compute_eflags() only gives the condition codes */
6496 tcg_gen_ori_tltcg_gen_ori_i32(cpu_T[0], cpu_T[0], 0x02);
6497 gen_op_mov_reg_T0(OT_BYTE, R_AH4);
6498 break;
6499 case 0xf5: /* cmc */
6500 if (s->cc_op != CC_OP_DYNAMIC)
6501 gen_op_set_cc_op(s->cc_op);
6502 gen_compute_eflags(cpu_cc_src);
6503 tcg_gen_xori_tltcg_gen_xori_i32(cpu_cc_src, cpu_cc_src, CC_C0x0001);
6504 s->cc_op = CC_OP_EFLAGS;
6505 break;
6506 case 0xf8: /* clc */
6507 if (s->cc_op != CC_OP_DYNAMIC)
6508 gen_op_set_cc_op(s->cc_op);
6509 gen_compute_eflags(cpu_cc_src);
6510 tcg_gen_andi_tltcg_gen_andi_i32(cpu_cc_src, cpu_cc_src, ~CC_C0x0001);
6511 s->cc_op = CC_OP_EFLAGS;
6512 break;
6513 case 0xf9: /* stc */
6514 if (s->cc_op != CC_OP_DYNAMIC)
6515 gen_op_set_cc_op(s->cc_op);
6516 gen_compute_eflags(cpu_cc_src);
6517 tcg_gen_ori_tltcg_gen_ori_i32(cpu_cc_src, cpu_cc_src, CC_C0x0001);
6518 s->cc_op = CC_OP_EFLAGS;
6519 break;
6520 case 0xfc: /* cld */
6521 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6522 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)__builtin_offsetof(CPUX86State, df));
6523 break;
6524 case 0xfd: /* std */
6525 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6526 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)__builtin_offsetof(CPUX86State, df));
6527 break;
6528
6529 /************************/
6530 /* bit operations */
6531 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6532 ot = dflag + OT_WORD;
6533 modrm = ldub_code(s->pc++);
6534 op = (modrm >> 3) & 7;
6535 mod = (modrm >> 6) & 3;
6536 rm = (modrm & 7) | REX_B(s)0;
6537 if (mod != 3) {
6538 s->rip_offset = 1;
6539 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6540 gen_op_ld_T0_A0(ot + s->mem_index);
6541 } else {
6542 gen_op_mov_TN_reg(ot, 0, rm);
6543 }
6544 /* load shift */
6545 val = ldub_code(s->pc++);
6546 gen_op_movl_T1_im(val);
6547 if (op < 4)
6548 goto illegal_op;
6549 op -= 4;
6550 goto bt_op;
6551 case 0x1a3: /* bt Gv, Ev */
6552 op = 0;
6553 goto do_btx;
6554 case 0x1ab: /* bts */
6555 op = 1;
6556 goto do_btx;
6557 case 0x1b3: /* btr */
6558 op = 2;
6559 goto do_btx;
6560 case 0x1bb: /* btc */
6561 op = 3;
6562 do_btx:
6563 ot = dflag + OT_WORD;
6564 modrm = ldub_code(s->pc++);
6565 reg = ((modrm >> 3) & 7) | rex_r;
6566 mod = (modrm >> 6) & 3;
6567 rm = (modrm & 7) | REX_B(s)0;
6568 gen_op_mov_TN_reg(OT_LONG, 1, reg);
6569 if (mod != 3) {
6570 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6571 /* specific case: we need to add a displacement */
6572 gen_exts(ot, cpu_T[1]);
6573 tcg_gen_sari_tltcg_gen_sari_i32(cpu_tmp0, cpu_T[1], 3 + ot);
6574 tcg_gen_shli_tltcg_gen_shli_i32(cpu_tmp0, cpu_tmp0, ot);
6575 tcg_gen_add_tltcg_gen_add_i32(cpu_A0, cpu_A0, cpu_tmp0);
6576 gen_op_ld_T0_A0(ot + s->mem_index);
6577 } else {
6578 gen_op_mov_TN_reg(ot, 0, rm);
6579 }
6580 bt_op:
6581 tcg_gen_andi_tltcg_gen_andi_i32(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6582 switch(op) {
6583 case 0:
6584 tcg_gen_shr_tltcg_gen_shr_i32(cpu_cc_src, cpu_T[0], cpu_T[1]);
6585 tcg_gen_movi_tltcg_gen_movi_i32(cpu_cc_dst, 0);
6586 break;
6587 case 1:
6588 tcg_gen_shr_tltcg_gen_shr_i32(cpu_tmp4, cpu_T[0], cpu_T[1]);
6589 tcg_gen_movi_tltcg_gen_movi_i32(cpu_tmp0, 1);
6590 tcg_gen_shl_tltcg_gen_shl_i32(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6591 tcg_gen_or_tltcg_gen_or_i32(cpu_T[0], cpu_T[0], cpu_tmp0);
6592 break;
6593 case 2:
6594 tcg_gen_shr_tltcg_gen_shr_i32(cpu_tmp4, cpu_T[0], cpu_T[1]);
6595 tcg_gen_movi_tltcg_gen_movi_i32(cpu_tmp0, 1);
6596 tcg_gen_shl_tltcg_gen_shl_i32(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6597 tcg_gen_not_tltcg_gen_not_i32(cpu_tmp0, cpu_tmp0);
6598 tcg_gen_and_tltcg_gen_and_i32(cpu_T[0], cpu_T[0], cpu_tmp0);
6599 break;
6600 default:
6601 case 3:
6602 tcg_gen_shr_tltcg_gen_shr_i32(cpu_tmp4, cpu_T[0], cpu_T[1]);
6603 tcg_gen_movi_tltcg_gen_movi_i32(cpu_tmp0, 1);
6604 tcg_gen_shl_tltcg_gen_shl_i32(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6605 tcg_gen_xor_tltcg_gen_xor_i32(cpu_T[0], cpu_T[0], cpu_tmp0);
6606 break;
6607 }
6608 s->cc_op = CC_OP_SARB + ot;
6609 if (op != 0) {
6610 if (mod != 3)
6611 gen_op_st_T0_A0(ot + s->mem_index);
6612 else
6613 gen_op_mov_reg_T0(ot, rm);
6614 tcg_gen_mov_tltcg_gen_mov_i32(cpu_cc_src, cpu_tmp4);
6615 tcg_gen_movi_tltcg_gen_movi_i32(cpu_cc_dst, 0);
6616 }
6617 break;
6618 case 0x1bc: /* bsf */
6619 case 0x1bd: /* bsr */
6620 {
6621 int label1;
6622 TCGvTCGv_i32 t0;
6623
6624 ot = dflag + OT_WORD;
6625 modrm = ldub_code(s->pc++);
6626 reg = ((modrm >> 3) & 7) | rex_r;
6627 gen_ldst_modrm(s,modrm, ot, OR_TMP0, 0);
6628 gen_extu(ot, cpu_T[0]);
6629 t0 = tcg_temp_local_new()tcg_temp_local_new_i32();
6630 tcg_gen_mov_tltcg_gen_mov_i32(t0, cpu_T[0]);
6631 if ((b & 1) && (prefixes & PREFIX_REPZ0x01) &&
6632 (s->cpuid_ext3_features & CPUID_EXT3_ABM(1 << 5))) {
6633 switch(ot) {
6634 case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0,
6635 tcg_const_i32(16)); break;
6636 case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0,
6637 tcg_const_i32(32)); break;
6638 case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0,
6639 tcg_const_i32(64)); break;
6640 }
6641 gen_op_mov_reg_T0(ot, reg);
6642 } else {
6643 label1 = gen_new_label();
6644 tcg_gen_movi_tltcg_gen_movi_i32(cpu_cc_dst, 0);
6645 tcg_gen_brcondi_tltcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, label1);
6646 if (b & 1) {
6647 gen_helper_bsr(cpu_T[0], t0);
6648 } else {
6649 gen_helper_bsf(cpu_T[0], t0);
6650 }
6651 gen_op_mov_reg_T0(ot, reg);
6652 tcg_gen_movi_tltcg_gen_movi_i32(cpu_cc_dst, 1);
6653 gen_set_label(label1);
6654 tcg_gen_discard_tltcg_gen_discard_i32(cpu_cc_src);
6655 s->cc_op = CC_OP_LOGICB + ot;
6656 }
6657 tcg_temp_freetcg_temp_free_i32(t0);
6658 }
6659 break;
6660 /************************/
6661 /* bcd */
6662 case 0x27: /* daa */
6663 if (CODE64(s)0)
6664 goto illegal_op;
6665 if (s->cc_op != CC_OP_DYNAMIC)
6666 gen_op_set_cc_op(s->cc_op);
6667 gen_helper_daa();
6668 s->cc_op = CC_OP_EFLAGS;
6669 break;
6670 case 0x2f: /* das */
6671 if (CODE64(s)0)
6672 goto illegal_op;
6673 if (s->cc_op != CC_OP_DYNAMIC)
6674 gen_op_set_cc_op(s->cc_op);
6675 gen_helper_das();
6676 s->cc_op = CC_OP_EFLAGS;
6677 break;
6678 case 0x37: /* aaa */
6679 if (CODE64(s)0)
6680 goto illegal_op;
6681 if (s->cc_op != CC_OP_DYNAMIC)
6682 gen_op_set_cc_op(s->cc_op);
6683 gen_helper_aaa();
6684 s->cc_op = CC_OP_EFLAGS;
6685 break;
6686 case 0x3f: /* aas */
6687 if (CODE64(s)0)
6688 goto illegal_op;
6689 if (s->cc_op != CC_OP_DYNAMIC)
6690 gen_op_set_cc_op(s->cc_op);
6691 gen_helper_aas();
6692 s->cc_op = CC_OP_EFLAGS;
6693 break;
6694 case 0xd4: /* aam */
6695 if (CODE64(s)0)
6696 goto illegal_op;
6697 val = ldub_code(s->pc++);
6698 if (val == 0) {
6699 gen_exception(s, EXCP00_DIVZ0, pc_start - s->cs_base);
6700 } else {
6701 gen_helper_aam(tcg_const_i32(val));
6702 s->cc_op = CC_OP_LOGICB;
6703 }
6704 break;
6705 case 0xd5: /* aad */
6706 if (CODE64(s)0)
6707 goto illegal_op;
6708 val = ldub_code(s->pc++);
6709 gen_helper_aad(tcg_const_i32(val));
6710 s->cc_op = CC_OP_LOGICB;
6711 break;
6712 /************************/
6713 /* misc */
6714 case 0x90: /* nop */
6715 /* XXX: correct lock test for all insn */
6716 if (prefixes & PREFIX_LOCK0x04) {
6717 goto illegal_op;
6718 }
6719 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6720 if (REX_B(s)0) {
6721 goto do_xchg_reg_eax;
6722 }
6723 if (prefixes & PREFIX_REPZ0x01) {
6724 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE0x077);
6725 }
6726 break;
6727 case 0x9b: /* fwait */
6728 if ((s->flags & (HF_MP_MASK(1 << 9) | HF_TS_MASK(1 << 11))) ==
6729 (HF_MP_MASK(1 << 9) | HF_TS_MASK(1 << 11))) {
6730 gen_exception(s, EXCP07_PREX7, pc_start - s->cs_base);
6731 } else {
6732 if (s->cc_op != CC_OP_DYNAMIC)
6733 gen_op_set_cc_op(s->cc_op);
6734 gen_jmp_im(pc_start - s->cs_base);
6735 gen_helper_fwait();
6736 }
6737 break;
6738 case 0xcc: /* int3 */
6739 gen_interrupt(s, EXCP03_INT33, pc_start - s->cs_base, s->pc - s->cs_base);
6740 break;
6741 case 0xcd: /* int N */
6742 val = ldub_code(s->pc++);
6743 if (s->vm86 && s->iopl != 3) {
6744 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
6745 } else {
6746 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6747 }
6748 break;
6749 case 0xce: /* into */
6750 if (CODE64(s)0)
6751 goto illegal_op;
6752 if (s->cc_op != CC_OP_DYNAMIC)
6753 gen_op_set_cc_op(s->cc_op);
6754 gen_jmp_im(pc_start - s->cs_base);
6755 gen_helper_into(tcg_const_i32(s->pc - pc_start));
6756 break;
6757#ifdef WANT_ICEBP
6758 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6759 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP0x088);
6760#if 1
6761 gen_debug(s, pc_start - s->cs_base);
6762#else
6763 /* start debug */
6764 tb_flush(cpu_single_envtls__cpu_single_env);
6765 cpu_set_log(CPU_LOG_INT(1 << 4) | CPU_LOG_TB_IN_ASM(1 << 1));
6766#endif
6767 break;
6768#endif
6769 case 0xfa: /* cli */
6770 if (!s->vm86) {
6771 if (s->cpl <= s->iopl) {
6772 gen_helper_cli();
6773 } else {
6774 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
6775 }
6776 } else {
6777 if (s->iopl == 3) {
6778 gen_helper_cli();
6779 } else {
6780 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
6781 }
6782 }
6783 break;
6784 case 0xfb: /* sti */
6785 if (!s->vm86) {
6786 if (s->cpl <= s->iopl) {
6787 gen_sti:
6788 gen_helper_sti();
6789 /* interruptions are enabled only the first insn after sti */
6790 /* If several instructions disable interrupts, only the
6791 _first_ does it */
6792 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK(1 << 3)))
6793 gen_helper_set_inhibit_irq();
6794 /* give a chance to handle pending irqs */
6795 gen_jmp_im(s->pc - s->cs_base);
6796 gen_eob(s);
6797 } else {
6798 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
6799 }
6800 } else {
6801 if (s->iopl == 3) {
6802 goto gen_sti;
6803 } else {
6804 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
6805 }
6806 }
6807 break;
6808 case 0x62: /* bound */
6809 if (CODE64(s)0)
6810 goto illegal_op;
6811 ot = dflag ? OT_LONG : OT_WORD;
6812 modrm = ldub_code(s->pc++);
6813 reg = (modrm >> 3) & 7;
6814 mod = (modrm >> 6) & 3;
6815 if (mod == 3)
6816 goto illegal_op;
6817 gen_op_mov_TN_reg(ot, 0, reg);
6818 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6819 gen_jmp_im(pc_start - s->cs_base);
6820 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
6821 if (ot == OT_WORD)
6822 gen_helper_boundw(cpu_A0, cpu_tmp2_i32);
6823 else
6824 gen_helper_boundl(cpu_A0, cpu_tmp2_i32);
6825 break;
6826 case 0x1c8 ... 0x1cf: /* bswap reg */
6827 reg = (b & 7) | REX_B(s)0;
6828#ifdef TARGET_X86_64
6829 if (dflag == 2) {
6830 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6831 tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
6832 gen_op_mov_reg_T0(OT_QUAD, reg);
6833 } else
6834#endif
6835 {
6836 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6837 tcg_gen_ext32u_tltcg_gen_mov_i32(cpu_T[0], cpu_T[0]);
6838 tcg_gen_bswap32_tltcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]);
6839 gen_op_mov_reg_T0(OT_LONG, reg);
6840 }
6841 break;
6842 case 0xd6: /* salc */
6843 if (CODE64(s)0)
6844 goto illegal_op;
6845 if (s->cc_op != CC_OP_DYNAMIC)
6846 gen_op_set_cc_op(s->cc_op);
6847 gen_compute_eflags_c(cpu_T[0]);
6848 tcg_gen_neg_tltcg_gen_neg_i32(cpu_T[0], cpu_T[0]);
6849 gen_op_mov_reg_T0(OT_BYTE, R_EAX0);
6850 break;
6851 case 0xe0: /* loopnz */
6852 case 0xe1: /* loopz */
6853 case 0xe2: /* loop */
6854 case 0xe3: /* jecxz */
6855 {
6856 int l1, l2, l3;
6857
6858 tval = (int8_t)insn_get(s, OT_BYTE);
6859 next_eip = s->pc - s->cs_base;
6860 tval += next_eip;
6861 if (s->dflag == 0)
6862 tval &= 0xffff;
6863
6864 l1 = gen_new_label();
6865 l2 = gen_new_label();
6866 l3 = gen_new_label();
6867 b &= 3;
6868 switch(b) {
6869 case 0: /* loopnz */
6870 case 1: /* loopz */
6871 if (s->cc_op != CC_OP_DYNAMIC)
6872 gen_op_set_cc_op(s->cc_op);
6873 gen_op_add_reg_im(s->aflag, R_ECX1, -1);
6874 gen_op_jz_ecx(s->aflag, l3);
6875 gen_compute_eflags(cpu_tmp0);
6876 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp0, cpu_tmp0, CC_Z0x0040);
6877 if (b == 0) {
6878 tcg_gen_brcondi_tltcg_gen_brcondi_i32(TCG_COND_EQ, cpu_tmp0, 0, l1);
6879 } else {
6880 tcg_gen_brcondi_tltcg_gen_brcondi_i32(TCG_COND_NE, cpu_tmp0, 0, l1);
6881 }
6882 break;
6883 case 2: /* loop */
6884 gen_op_add_reg_im(s->aflag, R_ECX1, -1);
6885 gen_op_jnz_ecx(s->aflag, l1);
6886 break;
6887 default:
6888 case 3: /* jcxz */
6889 gen_op_jz_ecx(s->aflag, l1);
6890 break;
6891 }
6892
6893 gen_set_label(l3);
6894 gen_jmp_im(next_eip);
6895 tcg_gen_br(l2);
6896
6897 gen_set_label(l1);
6898 gen_jmp_im(tval);
6899 gen_set_label(l2);
6900 gen_eob(s);
6901 }
6902 break;
6903 case 0x130: /* wrmsr */
6904 case 0x132: /* rdmsr */
6905 if (s->cpl != 0) {
6906 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
6907 } else {
6908 if (s->cc_op != CC_OP_DYNAMIC)
6909 gen_op_set_cc_op(s->cc_op);
6910 gen_jmp_im(pc_start - s->cs_base);
6911 if (b & 2) {
6912 gen_helper_rdmsr();
6913 } else {
6914 gen_helper_wrmsr();
6915 }
6916 }
6917 break;
6918 case 0x131: /* rdtsc */
6919 if (s->cc_op != CC_OP_DYNAMIC)
6920 gen_op_set_cc_op(s->cc_op);
6921 gen_jmp_im(pc_start - s->cs_base);
6922 if (use_icount)
6923 gen_io_start();
6924 gen_helper_rdtsc();
6925 if (use_icount) {
6926 gen_io_end();
6927 gen_jmp(s, s->pc - s->cs_base);
6928 }
6929 break;
6930 case 0x133: /* rdpmc */
6931 if (s->cc_op != CC_OP_DYNAMIC)
6932 gen_op_set_cc_op(s->cc_op);
6933 gen_jmp_im(pc_start - s->cs_base);
6934 gen_helper_rdpmc();
6935 break;
6936 case 0x134: /* sysenter */
6937 /* For Intel SYSENTER is valid on 64-bit */
6938 if (CODE64(s)0 && cpu_single_envtls__cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_10x756e6547)
6939 goto illegal_op;
6940 if (!s->pe) {
6941 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
6942 } else {
6943 gen_update_cc_op(s);
6944 gen_jmp_im(pc_start - s->cs_base);
6945 gen_helper_sysenter();
6946 gen_eob(s);
6947 }
6948 break;
6949 case 0x135: /* sysexit */
6950 /* For Intel SYSEXIT is valid on 64-bit */
6951 if (CODE64(s)0 && cpu_single_envtls__cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_10x756e6547)
6952 goto illegal_op;
6953 if (!s->pe) {
6954 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
6955 } else {
6956 gen_update_cc_op(s);
6957 gen_jmp_im(pc_start - s->cs_base);
6958 gen_helper_sysexit(tcg_const_i32(dflag));
6959 gen_eob(s);
6960 }
6961 break;
6962#ifdef TARGET_X86_64
6963 case 0x105: /* syscall */
6964 /* XXX: is it usable in real mode ? */
6965 gen_update_cc_op(s);
6966 gen_jmp_im(pc_start - s->cs_base);
6967 gen_helper_syscall(tcg_const_i32(s->pc - pc_start));
6968 gen_eob(s);
6969 break;
6970 case 0x107: /* sysret */
6971 if (!s->pe) {
6972 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
6973 } else {
6974 gen_update_cc_op(s);
6975 gen_jmp_im(pc_start - s->cs_base);
6976 gen_helper_sysret(tcg_const_i32(s->dflag));
6977 /* condition codes are modified only in long mode */
6978 if (s->lma)
6979 s->cc_op = CC_OP_EFLAGS;
6980 gen_eob(s);
6981 }
6982 break;
6983#endif
6984 case 0x1a2: /* cpuid */
6985 if (s->cc_op != CC_OP_DYNAMIC)
6986 gen_op_set_cc_op(s->cc_op);
6987 gen_jmp_im(pc_start - s->cs_base);
6988 gen_helper_cpuid();
6989 break;
6990 case 0xf4: /* hlt */
6991 if (s->cpl != 0) {
6992 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
6993 } else {
6994 if (s->cc_op != CC_OP_DYNAMIC)
6995 gen_op_set_cc_op(s->cc_op);
6996 gen_jmp_im(pc_start - s->cs_base);
6997 gen_helper_hlt(tcg_const_i32(s->pc - pc_start));
6998 s->is_jmp = DISAS_TB_JUMP3;
6999 }
7000 break;
7001 case 0x100:
7002 modrm = ldub_code(s->pc++);
7003 mod = (modrm >> 6) & 3;
7004 op = (modrm >> 3) & 7;
7005 switch(op) {
7006 case 0: /* sldt */
7007 if (!s->pe || s->vm86)
7008 goto illegal_op;
7009 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ0x068);
7010 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector)__builtin_offsetof(CPUX86State, ldt.selector));
7011 ot = OT_WORD;
7012 if (mod == 3)
7013 ot += s->dflag;
7014 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
7015 break;
7016 case 2: /* lldt */
7017 if (!s->pe || s->vm86)
7018 goto illegal_op;
7019 if (s->cpl != 0) {
7020 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7021 } else {
7022 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE0x06c);
7023 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7024 gen_jmp_im(pc_start - s->cs_base);
7025 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
7026 gen_helper_lldt(cpu_tmp2_i32);
7027 }
7028 break;
7029 case 1: /* str */
7030 if (!s->pe || s->vm86)
7031 goto illegal_op;
7032 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ0x069);
7033 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector)__builtin_offsetof(CPUX86State, tr.selector));
7034 ot = OT_WORD;
7035 if (mod == 3)
7036 ot += s->dflag;
7037 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
7038 break;
7039 case 3: /* ltr */
7040 if (!s->pe || s->vm86)
7041 goto illegal_op;
7042 if (s->cpl != 0) {
7043 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7044 } else {
7045 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE0x06d);
7046 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7047 gen_jmp_im(pc_start - s->cs_base);
7048 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
7049 gen_helper_ltr(cpu_tmp2_i32);
7050 }
7051 break;
7052 case 4: /* verr */
7053 case 5: /* verw */
7054 if (!s->pe || s->vm86)
7055 goto illegal_op;
7056 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7057 if (s->cc_op != CC_OP_DYNAMIC)
7058 gen_op_set_cc_op(s->cc_op);
7059 if (op == 4)
7060 gen_helper_verr(cpu_T[0]);
7061 else
7062 gen_helper_verw(cpu_T[0]);
7063 s->cc_op = CC_OP_EFLAGS;
7064 break;
7065 default:
7066 goto illegal_op;
7067 }
7068 break;
7069 case 0x101:
7070 modrm = ldub_code(s->pc++);
7071 mod = (modrm >> 6) & 3;
7072 op = (modrm >> 3) & 7;
7073 rm = modrm & 7;
7074 switch(op) {
7075 case 0: /* sgdt */
7076 if (mod == 3)
7077 goto illegal_op;
7078 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ0x067);
7079 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7080 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)__builtin_offsetof(CPUX86State, gdt.limit));
7081 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7082 gen_add_A0_im(s, 2);
7083 tcg_gen_ld_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)__builtin_offsetof(CPUX86State, gdt.base));
7084 if (!s->dflag)
7085 gen_op_andl_T0_im(0xffffff);
7086 gen_op_st_T0_A0(CODE64(s)0 + OT_LONG + s->mem_index);
7087 break;
7088 case 1:
7089 if (mod == 3) {
7090 switch (rm) {
7091 case 0: /* monitor */
7092 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR(1 << 3)) ||
7093 s->cpl != 0)
7094 goto illegal_op;
7095 if (s->cc_op != CC_OP_DYNAMIC)
7096 gen_op_set_cc_op(s->cc_op);
7097 gen_jmp_im(pc_start - s->cs_base);
7098#ifdef TARGET_X86_64
7099 if (s->aflag == 2) {
7100 gen_op_movq_A0_reg(R_EAX0);
7101 } else
7102#endif
7103 {
7104 gen_op_movl_A0_reg(R_EAX0);
7105 if (s->aflag == 0)
7106 gen_op_andl_A0_ffff();
7107 }
7108 gen_add_A0_ds_seg(s);
7109 gen_helper_monitor(cpu_A0);
7110 break;
7111 case 1: /* mwait */
7112 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR(1 << 3)) ||
7113 s->cpl != 0)
7114 goto illegal_op;
7115 gen_update_cc_op(s);
7116 gen_jmp_im(pc_start - s->cs_base);
7117 gen_helper_mwait(tcg_const_i32(s->pc - pc_start));
7118 gen_eob(s);
7119 break;
7120 default:
7121 goto illegal_op;
7122 }
7123 } else { /* sidt */
7124 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ0x066);
7125 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7126 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)__builtin_offsetof(CPUX86State, idt.limit));
7127 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7128 gen_add_A0_im(s, 2);
7129 tcg_gen_ld_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)__builtin_offsetof(CPUX86State, idt.base));
7130 if (!s->dflag)
7131 gen_op_andl_T0_im(0xffffff);
7132 gen_op_st_T0_A0(CODE64(s)0 + OT_LONG + s->mem_index);
7133 }
7134 break;
7135 case 2: /* lgdt */
7136 case 3: /* lidt */
7137 if (mod == 3) {
7138 if (s->cc_op != CC_OP_DYNAMIC)
7139 gen_op_set_cc_op(s->cc_op);
7140 gen_jmp_im(pc_start - s->cs_base);
7141 switch(rm) {
7142 case 0: /* VMRUN */
7143 if (!(s->flags & HF_SVME_MASK(1 << 20)) || !s->pe)
7144 goto illegal_op;
7145 if (s->cpl != 0) {
7146 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7147 break;
7148 } else {
7149 gen_helper_vmrun(tcg_const_i32(s->aflag),
7150 tcg_const_i32(s->pc - pc_start));
7151 tcg_gen_exit_tb(0);
7152 s->is_jmp = DISAS_TB_JUMP3;
7153 }
7154 break;
7155 case 1: /* VMMCALL */
7156 if (!(s->flags & HF_SVME_MASK(1 << 20)))
7157 goto illegal_op;
7158 gen_helper_vmmcall();
7159 break;
7160 case 2: /* VMLOAD */
7161 if (!(s->flags & HF_SVME_MASK(1 << 20)) || !s->pe)
7162 goto illegal_op;
7163 if (s->cpl != 0) {
7164 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7165 break;
7166 } else {
7167 gen_helper_vmload(tcg_const_i32(s->aflag));
7168 }
7169 break;
7170 case 3: /* VMSAVE */
7171 if (!(s->flags & HF_SVME_MASK(1 << 20)) || !s->pe)
7172 goto illegal_op;
7173 if (s->cpl != 0) {
7174 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7175 break;
7176 } else {
7177 gen_helper_vmsave(tcg_const_i32(s->aflag));
7178 }
7179 break;
7180 case 4: /* STGI */
7181 if ((!(s->flags & HF_SVME_MASK(1 << 20)) &&
7182 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT(1 << 12))) ||
7183 !s->pe)
7184 goto illegal_op;
7185 if (s->cpl != 0) {
7186 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7187 break;
7188 } else {
7189 gen_helper_stgi();
7190 }
7191 break;
7192 case 5: /* CLGI */
7193 if (!(s->flags & HF_SVME_MASK(1 << 20)) || !s->pe)
7194 goto illegal_op;
7195 if (s->cpl != 0) {
7196 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7197 break;
7198 } else {
7199 gen_helper_clgi();
7200 }
7201 break;
7202 case 6: /* SKINIT */
7203 if ((!(s->flags & HF_SVME_MASK(1 << 20)) &&
7204 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT(1 << 12))) ||
7205 !s->pe)
7206 goto illegal_op;
7207 gen_helper_skinit();
7208 break;
7209 case 7: /* INVLPGA */
7210 if (!(s->flags & HF_SVME_MASK(1 << 20)) || !s->pe)
7211 goto illegal_op;
7212 if (s->cpl != 0) {
7213 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7214 break;
7215 } else {
7216 gen_helper_invlpga(tcg_const_i32(s->aflag));
7217 }
7218 break;
7219 default:
7220 goto illegal_op;
7221 }
7222 } else if (s->cpl != 0) {
7223 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7224 } else {
7225 gen_svm_check_intercept(s, pc_start,
7226 op==2 ? SVM_EXIT_GDTR_WRITE0x06b : SVM_EXIT_IDTR_WRITE0x06a);
7227 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7228 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
7229 gen_add_A0_im(s, 2);
7230 gen_op_ld_T0_A0(CODE64(s)0 + OT_LONG + s->mem_index);
7231 if (!s->dflag)
7232 gen_op_andl_T0_im(0xffffff);
7233 if (op == 2) {
7234 tcg_gen_st_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)__builtin_offsetof(CPUX86State, gdt.base));
7235 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)__builtin_offsetof(CPUX86State, gdt.limit));
7236 } else {
7237 tcg_gen_st_tltcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base)__builtin_offsetof(CPUX86State, idt.base));
7238 tcg_gen_st32_tltcg_gen_st_i32(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit)__builtin_offsetof(CPUX86State, idt.limit));
7239 }
7240 }
7241 break;
7242 case 4: /* smsw */
7243 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR00x000);
7244#if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7245 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])__builtin_offsetof(CPUX86State, cr[0]) + 4);
7246#else
7247 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])__builtin_offsetof(CPUX86State, cr[0]));
7248#endif
7249 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
7250 break;
7251 case 6: /* lmsw */
7252 if (s->cpl != 0) {
7253 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7254 } else {
7255 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR00x010);
7256 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7257 gen_helper_lmsw(cpu_T[0]);
7258 gen_jmp_im(s->pc - s->cs_base);
7259 gen_eob(s);
7260 }
7261 break;
7262 case 7:
7263 if (mod != 3) { /* invlpg */
7264 if (s->cpl != 0) {
7265 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7266 } else {
7267 if (s->cc_op != CC_OP_DYNAMIC)
7268 gen_op_set_cc_op(s->cc_op);
7269 gen_jmp_im(pc_start - s->cs_base);
7270 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7271 gen_helper_invlpg(cpu_A0);
7272 gen_jmp_im(s->pc - s->cs_base);
7273 gen_eob(s);
7274 }
7275 } else {
7276 switch (rm) {
7277 case 0: /* swapgs */
7278#ifdef TARGET_X86_64
7279 if (CODE64(s)0) {
7280 if (s->cpl != 0) {
7281 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7282 } else {
7283 tcg_gen_ld_tltcg_gen_ld_i32(cpu_T[0], cpu_env,
7284 offsetof(CPUX86State,segs[R_GS].base)__builtin_offsetof(CPUX86State, segs[5].base));
7285 tcg_gen_ld_tltcg_gen_ld_i32(cpu_T[1], cpu_env,
7286 offsetof(CPUX86State,kernelgsbase)__builtin_offsetof(CPUX86State, kernelgsbase));
7287 tcg_gen_st_tltcg_gen_st_i32(cpu_T[1], cpu_env,
7288 offsetof(CPUX86State,segs[R_GS].base)__builtin_offsetof(CPUX86State, segs[5].base));
7289 tcg_gen_st_tltcg_gen_st_i32(cpu_T[0], cpu_env,
7290 offsetof(CPUX86State,kernelgsbase)__builtin_offsetof(CPUX86State, kernelgsbase));
7291 }
7292 } else
7293#endif
7294 {
7295 goto illegal_op;
7296 }
7297 break;
7298 case 1: /* rdtscp */
7299 if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP(1 << 27)))
7300 goto illegal_op;
7301 if (s->cc_op != CC_OP_DYNAMIC)
7302 gen_op_set_cc_op(s->cc_op);
7303 gen_jmp_im(pc_start - s->cs_base);
7304 if (use_icount)
7305 gen_io_start();
7306 gen_helper_rdtscp();
7307 if (use_icount) {
7308 gen_io_end();
7309 gen_jmp(s, s->pc - s->cs_base);
7310 }
7311 break;
7312 default:
7313 goto illegal_op;
7314 }
7315 }
7316 break;
7317 default:
7318 goto illegal_op;
7319 }
7320 break;
7321 case 0x108: /* invd */
7322 case 0x109: /* wbinvd */
7323 if (s->cpl != 0) {
7324 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7325 } else {
7326 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD0x076 : SVM_EXIT_WBINVD0x089);
7327 /* nothing to do */
7328 }
7329 break;
7330 case 0x63: /* arpl or movslS (x86_64) */
7331#ifdef TARGET_X86_64
7332 if (CODE64(s)0) {
7333 int d_ot;
7334 /* d_ot is the size of destination */
7335 d_ot = dflag + OT_WORD;
7336
7337 modrm = ldub_code(s->pc++);
7338 reg = ((modrm >> 3) & 7) | rex_r;
7339 mod = (modrm >> 6) & 3;
7340 rm = (modrm & 7) | REX_B(s)0;
7341
7342 if (mod == 3) {
7343 gen_op_mov_TN_reg(OT_LONG, 0, rm);
7344 /* sign extend */
7345 if (d_ot == OT_QUAD)
7346 tcg_gen_ext32s_tltcg_gen_mov_i32(cpu_T[0], cpu_T[0]);
7347 gen_op_mov_reg_T0(d_ot, reg);
7348 } else {
7349 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7350 if (d_ot == OT_QUAD) {
7351 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
7352 } else {
7353 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7354 }
7355 gen_op_mov_reg_T0(d_ot, reg);
7356 }
7357 } else
7358#endif
7359 {
7360 int label1;
7361 TCGvTCGv_i32 t0, t1, t2, a0;
7362
7363 if (!s->pe || s->vm86)
7364 goto illegal_op;
7365 t0 = tcg_temp_local_new()tcg_temp_local_new_i32();
7366 t1 = tcg_temp_local_new()tcg_temp_local_new_i32();
7367 t2 = tcg_temp_local_new()tcg_temp_local_new_i32();
7368 ot = OT_WORD;
7369 modrm = ldub_code(s->pc++);
7370 reg = (modrm >> 3) & 7;
7371 mod = (modrm >> 6) & 3;
7372 rm = modrm & 7;
7373 if (mod != 3) {
7374 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7375 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
7376 a0 = tcg_temp_local_new()tcg_temp_local_new_i32();
7377 tcg_gen_mov_tltcg_gen_mov_i32(a0, cpu_A0);
7378 } else {
7379 gen_op_mov_v_reg(ot, t0, rm);
7380 TCGV_UNUSED(a0)a0 = __extension__ ({ TCGv_i32 make_tcgv_tmp = {-1}; make_tcgv_tmp
;});
7381 }
7382 gen_op_mov_v_reg(ot, t1, reg);
7383 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp0, t0, 3);
7384 tcg_gen_andi_tltcg_gen_andi_i32(t1, t1, 3);
7385 tcg_gen_movi_tltcg_gen_movi_i32(t2, 0);
7386 label1 = gen_new_label();
7387 tcg_gen_brcond_tltcg_gen_brcond_i32(TCG_COND_GE, cpu_tmp0, t1, label1);
7388 tcg_gen_andi_tltcg_gen_andi_i32(t0, t0, ~3);
7389 tcg_gen_or_tltcg_gen_or_i32(t0, t0, t1);
7390 tcg_gen_movi_tltcg_gen_movi_i32(t2, CC_Z0x0040);
7391 gen_set_label(label1);
7392 if (mod != 3) {
7393 gen_op_st_v(ot + s->mem_index, t0, a0);
7394 tcg_temp_freetcg_temp_free_i32(a0);
7395 } else {
7396 gen_op_mov_reg_v(ot, rm, t0);
7397 }
7398 if (s->cc_op != CC_OP_DYNAMIC)
7399 gen_op_set_cc_op(s->cc_op);
7400 gen_compute_eflags(cpu_cc_src);
7401 tcg_gen_andi_tltcg_gen_andi_i32(cpu_cc_src, cpu_cc_src, ~CC_Z0x0040);
7402 tcg_gen_or_tltcg_gen_or_i32(cpu_cc_src, cpu_cc_src, t2);
7403 s->cc_op = CC_OP_EFLAGS;
7404 tcg_temp_freetcg_temp_free_i32(t0);
7405 tcg_temp_freetcg_temp_free_i32(t1);
7406 tcg_temp_freetcg_temp_free_i32(t2);
7407 }
7408 break;
7409 case 0x102: /* lar */
7410 case 0x103: /* lsl */
7411 {
7412 int label1;
7413 TCGvTCGv_i32 t0;
7414 if (!s->pe || s->vm86)
7415 goto illegal_op;
7416 ot = dflag ? OT_LONG : OT_WORD;
7417 modrm = ldub_code(s->pc++);
7418 reg = ((modrm >> 3) & 7) | rex_r;
7419 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7420 t0 = tcg_temp_local_new()tcg_temp_local_new_i32();
7421 if (s->cc_op != CC_OP_DYNAMIC)
7422 gen_op_set_cc_op(s->cc_op);
7423 if (b == 0x102)
7424 gen_helper_lar(t0, cpu_T[0]);
7425 else
7426 gen_helper_lsl(t0, cpu_T[0]);
7427 tcg_gen_andi_tltcg_gen_andi_i32(cpu_tmp0, cpu_cc_src, CC_Z0x0040);
7428 label1 = gen_new_label();
7429 tcg_gen_brcondi_tltcg_gen_brcondi_i32(TCG_COND_EQ, cpu_tmp0, 0, label1);
7430 gen_op_mov_reg_v(ot, reg, t0);
7431 gen_set_label(label1);
7432 s->cc_op = CC_OP_EFLAGS;
7433 tcg_temp_freetcg_temp_free_i32(t0);
7434 }
7435 break;
7436 case 0x118:
7437 modrm = ldub_code(s->pc++);
7438 mod = (modrm >> 6) & 3;
7439 op = (modrm >> 3) & 7;
7440 switch(op) {
7441 case 0: /* prefetchnta */
7442 case 1: /* prefetchnt0 */
7443 case 2: /* prefetchnt0 */
7444 case 3: /* prefetchnt0 */
7445 if (mod == 3)
7446 goto illegal_op;
7447 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7448 /* nothing more to do */
7449 break;
7450 default: /* nop (multi byte) */
7451 gen_nop_modrm(s, modrm);
7452 break;
7453 }
7454 break;
7455 case 0x119 ... 0x11f: /* nop (multi byte) */
7456 modrm = ldub_code(s->pc++);
7457 gen_nop_modrm(s, modrm);
7458 break;
7459 case 0x120: /* mov reg, crN */
7460 case 0x122: /* mov crN, reg */
7461 if (s->cpl != 0) {
7462 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7463 } else {
7464 modrm = ldub_code(s->pc++);
7465 if ((modrm & 0xc0) != 0xc0)
7466 goto illegal_op;
7467 rm = (modrm & 7) | REX_B(s)0;
7468 reg = ((modrm >> 3) & 7) | rex_r;
7469 if (CODE64(s)0)
7470 ot = OT_QUAD;
7471 else
7472 ot = OT_LONG;
7473 if ((prefixes & PREFIX_LOCK0x04) && (reg == 0) &&
7474 (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG(1 << 4))) {
7475 reg = 8;
7476 }
7477 switch(reg) {
7478 case 0:
7479 case 2:
7480 case 3:
7481 case 4:
7482 case 8:
7483 if (s->cc_op != CC_OP_DYNAMIC)
7484 gen_op_set_cc_op(s->cc_op);
7485 gen_jmp_im(pc_start - s->cs_base);
7486 if (b & 2) {
7487 gen_op_mov_TN_reg(ot, 0, rm);
7488 gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]);
7489 gen_jmp_im(s->pc - s->cs_base);
7490 gen_eob(s);
7491 } else {
7492 gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg));
7493 gen_op_mov_reg_T0(ot, rm);
7494 }
7495 break;
7496 default:
7497 goto illegal_op;
7498 }
7499 }
7500 break;
7501 case 0x121: /* mov reg, drN */
7502 case 0x123: /* mov drN, reg */
7503 if (s->cpl != 0) {
7504 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7505 } else {
7506 modrm = ldub_code(s->pc++);
7507 if ((modrm & 0xc0) != 0xc0)
7508 goto illegal_op;
7509 rm = (modrm & 7) | REX_B(s)0;
7510 reg = ((modrm >> 3) & 7) | rex_r;
7511 if (CODE64(s)0)
7512 ot = OT_QUAD;
7513 else
7514 ot = OT_LONG;
7515 /* XXX: do it dynamically with CR4.DE bit */
7516 if (reg == 4 || reg == 5 || reg >= 8)
7517 goto illegal_op;
7518 if (b & 2) {
7519 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR00x030 + reg);
7520 gen_op_mov_TN_reg(ot, 0, rm);
7521 gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]);
7522 gen_jmp_im(s->pc - s->cs_base);
7523 gen_eob(s);
7524 } else {
7525 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR00x020 + reg);
7526 tcg_gen_ld_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg])__builtin_offsetof(CPUX86State, dr[reg]));
7527 gen_op_mov_reg_T0(ot, rm);
7528 }
7529 }
7530 break;
7531 case 0x106: /* clts */
7532 if (s->cpl != 0) {
7533 gen_exception(s, EXCP0D_GPF13, pc_start - s->cs_base);
7534 } else {
7535 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR00x010);
7536 gen_helper_clts();
7537 /* abort block because static cpu state changed */
7538 gen_jmp_im(s->pc - s->cs_base);
7539 gen_eob(s);
7540 }
7541 break;
7542 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7543 case 0x1c3: /* MOVNTI reg, mem */
7544 if (!(s->cpuid_features & CPUID_SSE2(1 << 26)))
7545 goto illegal_op;
7546 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7547 modrm = ldub_code(s->pc++);
7548 mod = (modrm >> 6) & 3;
7549 if (mod == 3)
7550 goto illegal_op;
7551 reg = ((modrm >> 3) & 7) | rex_r;
7552 /* generate a generic store */
7553 gen_ldst_modrm(s, modrm, ot, reg, 1);
7554 break;
7555 case 0x1ae:
7556 modrm = ldub_code(s->pc++);
7557 mod = (modrm >> 6) & 3;
7558 op = (modrm >> 3) & 7;
7559 switch(op) {
7560 case 0: /* fxsave */
7561 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR(1 << 24)) ||
7562 (s->prefix & PREFIX_LOCK0x04))
7563 goto illegal_op;
7564 if ((s->flags & HF_EM_MASK(1 << 10)) || (s->flags & HF_TS_MASK(1 << 11))) {
7565 gen_exception(s, EXCP07_PREX7, pc_start - s->cs_base);
7566 break;
7567 }
7568 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7569 if (s->cc_op != CC_OP_DYNAMIC)
7570 gen_op_set_cc_op(s->cc_op);
7571 gen_jmp_im(pc_start - s->cs_base);
7572 gen_helper_fxsave(cpu_A0, tcg_const_i32((s->dflag == 2)));
7573 break;
7574 case 1: /* fxrstor */
7575 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR(1 << 24)) ||
7576 (s->prefix & PREFIX_LOCK0x04))
7577 goto illegal_op;
7578 if ((s->flags & HF_EM_MASK(1 << 10)) || (s->flags & HF_TS_MASK(1 << 11))) {
7579 gen_exception(s, EXCP07_PREX7, pc_start - s->cs_base);
7580 break;
7581 }
7582 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7583 if (s->cc_op != CC_OP_DYNAMIC)
7584 gen_op_set_cc_op(s->cc_op);
7585 gen_jmp_im(pc_start - s->cs_base);
7586 gen_helper_fxrstor(cpu_A0, tcg_const_i32((s->dflag == 2)));
7587 break;
7588 case 2: /* ldmxcsr */
7589 case 3: /* stmxcsr */
7590 if (s->flags & HF_TS_MASK(1 << 11)) {
7591 gen_exception(s, EXCP07_PREX7, pc_start - s->cs_base);
7592 break;
7593 }
7594 if ((s->flags & HF_EM_MASK(1 << 10)) || !(s->flags & HF_OSFXSR_MASK(1 << 22)) ||
7595 mod == 3)
7596 goto illegal_op;
7597 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7598 if (op == 2) {
7599 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7600 tcg_gen_trunc_tl_i32tcg_gen_mov_i32(cpu_tmp2_i32, cpu_T[0]);
7601 gen_helper_ldmxcsr(cpu_tmp2_i32);
7602 } else {
7603 tcg_gen_ld32u_tltcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)__builtin_offsetof(CPUX86State, mxcsr));
7604 gen_op_st_T0_A0(OT_LONG + s->mem_index);
7605 }
7606 break;
7607 case 5: /* lfence */
7608 case 6: /* mfence */
7609 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2(1 << 26)))
7610 goto illegal_op;
7611 break;
7612 case 7: /* sfence / clflush */
7613 if ((modrm & 0xc7) == 0xc0) {
7614 /* sfence */
7615 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7616 if (!(s->cpuid_features & CPUID_SSE(1 << 25)))
7617 goto illegal_op;
7618 } else {
7619 /* clflush */
7620 if (!(s->cpuid_features & CPUID_CLFLUSH(1 << 19)))
7621 goto illegal_op;
7622 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7623 }
7624 break;
7625 default:
7626 goto illegal_op;
7627 }
7628 break;
7629 case 0x10d: /* 3DNow! prefetch(w) */
7630 modrm = ldub_code(s->pc++);
7631 mod = (modrm >> 6) & 3;
7632 if (mod == 3)
7633 goto illegal_op;
7634 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7635 /* ignore for now */
7636 break;
7637 case 0x1aa: /* rsm */
7638 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM0x073);
7639 if (!(s->flags & HF_SMM_MASK(1 << 19)))
7640 goto illegal_op;
7641 gen_update_cc_op(s);
7642 gen_jmp_im(s->pc - s->cs_base);
7643 gen_helper_rsm();
7644 gen_eob(s);
7645 break;
7646 case 0x1b8: /* SSE4.2 popcnt */
7647 if ((prefixes & (PREFIX_REPZ0x01 | PREFIX_LOCK0x04 | PREFIX_REPNZ0x02)) !=
7648 PREFIX_REPZ0x01)
7649 goto illegal_op;
7650 if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT(1 << 23)))
7651 goto illegal_op;
7652
7653 modrm = ldub_code(s->pc++);
7654 reg = ((modrm >> 3) & 7);
7655
7656 if (s->prefix & PREFIX_DATA0x08)
7657 ot = OT_WORD;
7658 else if (s->dflag != 2)
7659 ot = OT_LONG;
7660 else
7661 ot = OT_QUAD;
7662
7663 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
7664 gen_helper_popcnt(cpu_T[0], cpu_T[0], tcg_const_i32(ot));
7665 gen_op_mov_reg_T0(ot, reg);
7666
7667 s->cc_op = CC_OP_EFLAGS;
7668 break;
7669 case 0x10e ... 0x10f:
7670 /* 3DNow! instructions, ignore prefixes */
7671 s->prefix &= ~(PREFIX_REPZ0x01 | PREFIX_REPNZ0x02 | PREFIX_DATA0x08);
7672 case 0x110 ... 0x117:
7673 case 0x128 ... 0x12f:
7674 case 0x138 ... 0x13a:
7675 case 0x150 ... 0x179:
7676 case 0x17c ... 0x17f:
7677 case 0x1c2:
7678 case 0x1c4 ... 0x1c6:
7679 case 0x1d0 ... 0x1fe:
7680 gen_sse(s, b, pc_start, rex_r);
7681 break;
7682 default:
7683 goto illegal_op;
7684 }
7685 /* lock generation */
7686 if (s->prefix & PREFIX_LOCK0x04)
7687 gen_helper_unlock();
7688 return s->pc;
7689 illegal_op:
7690 if (s->prefix & PREFIX_LOCK0x04)
7691 gen_helper_unlock();
7692 /* XXX: ensure that no lock was generated */
7693 gen_exception(s, EXCP06_ILLOP6, pc_start - s->cs_base);
7694 return s->pc;
7695}
7696
7697void optimize_flags_init(void)
7698{
7699 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env")__extension__ ({ TCGv_ptr make_tcgv_tmp = {((tcg_global_reg_new_i64
((TCG_REG_R14), ("env"))).i64)}; make_tcgv_tmp; });
7700 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0TCG_REG_R14,
7701 offsetof(CPUX86State, cc_op)__builtin_offsetof(CPUX86State, cc_op), "cc_op");
7702 cpu_cc_src = tcg_global_mem_newtcg_global_mem_new_i32(TCG_AREG0TCG_REG_R14, offsetof(CPUX86State, cc_src)__builtin_offsetof(CPUX86State, cc_src),
7703 "cc_src");
7704 cpu_cc_dst = tcg_global_mem_newtcg_global_mem_new_i32(TCG_AREG0TCG_REG_R14, offsetof(CPUX86State, cc_dst)__builtin_offsetof(CPUX86State, cc_dst),
7705 "cc_dst");
7706 cpu_cc_tmp = tcg_global_mem_newtcg_global_mem_new_i32(TCG_AREG0TCG_REG_R14, offsetof(CPUX86State, cc_tmp)__builtin_offsetof(CPUX86State, cc_tmp),
7707 "cc_tmp");
7708
7709#ifdef TARGET_X86_64
7710 cpu_regs[R_EAX0] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7711 offsetof(CPUX86State, regs[R_EAX])__builtin_offsetof(CPUX86State, regs[0]), "rax");
7712 cpu_regs[R_ECX1] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7713 offsetof(CPUX86State, regs[R_ECX])__builtin_offsetof(CPUX86State, regs[1]), "rcx");
7714 cpu_regs[R_EDX2] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7715 offsetof(CPUX86State, regs[R_EDX])__builtin_offsetof(CPUX86State, regs[2]), "rdx");
7716 cpu_regs[R_EBX3] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7717 offsetof(CPUX86State, regs[R_EBX])__builtin_offsetof(CPUX86State, regs[3]), "rbx");
7718 cpu_regs[R_ESP4] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7719 offsetof(CPUX86State, regs[R_ESP])__builtin_offsetof(CPUX86State, regs[4]), "rsp");
7720 cpu_regs[R_EBP5] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7721 offsetof(CPUX86State, regs[R_EBP])__builtin_offsetof(CPUX86State, regs[5]), "rbp");
7722 cpu_regs[R_ESI6] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7723 offsetof(CPUX86State, regs[R_ESI])__builtin_offsetof(CPUX86State, regs[6]), "rsi");
7724 cpu_regs[R_EDI7] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7725 offsetof(CPUX86State, regs[R_EDI])__builtin_offsetof(CPUX86State, regs[7]), "rdi");
7726 cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7727 offsetof(CPUX86State, regs[8])__builtin_offsetof(CPUX86State, regs[8]), "r8");
7728 cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7729 offsetof(CPUX86State, regs[9])__builtin_offsetof(CPUX86State, regs[9]), "r9");
7730 cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7731 offsetof(CPUX86State, regs[10])__builtin_offsetof(CPUX86State, regs[10]), "r10");
7732 cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7733 offsetof(CPUX86State, regs[11])__builtin_offsetof(CPUX86State, regs[11]), "r11");
7734 cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7735 offsetof(CPUX86State, regs[12])__builtin_offsetof(CPUX86State, regs[12]), "r12");
7736 cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7737 offsetof(CPUX86State, regs[13])__builtin_offsetof(CPUX86State, regs[13]), "r13");
7738 cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7739 offsetof(CPUX86State, regs[14])__builtin_offsetof(CPUX86State, regs[14]), "r14");
7740 cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0TCG_REG_R14,
7741 offsetof(CPUX86State, regs[15])__builtin_offsetof(CPUX86State, regs[15]), "r15");
7742#else
7743 cpu_regs[R_EAX0] = tcg_global_mem_new_i32(TCG_AREG0TCG_REG_R14,
7744 offsetof(CPUX86State, regs[R_EAX])__builtin_offsetof(CPUX86State, regs[0]), "eax");
7745 cpu_regs[R_ECX1] = tcg_global_mem_new_i32(TCG_AREG0TCG_REG_R14,
7746 offsetof(CPUX86State, regs[R_ECX])__builtin_offsetof(CPUX86State, regs[1]), "ecx");
7747 cpu_regs[R_EDX2] = tcg_global_mem_new_i32(TCG_AREG0TCG_REG_R14,
7748 offsetof(CPUX86State, regs[R_EDX])__builtin_offsetof(CPUX86State, regs[2]), "edx");
7749 cpu_regs[R_EBX3] = tcg_global_mem_new_i32(TCG_AREG0TCG_REG_R14,
7750 offsetof(CPUX86State, regs[R_EBX])__builtin_offsetof(CPUX86State, regs[3]), "ebx");
7751 cpu_regs[R_ESP4] = tcg_global_mem_new_i32(TCG_AREG0TCG_REG_R14,
7752 offsetof(CPUX86State, regs[R_ESP])__builtin_offsetof(CPUX86State, regs[4]), "esp");
7753 cpu_regs[R_EBP5] = tcg_global_mem_new_i32(TCG_AREG0TCG_REG_R14,
7754 offsetof(CPUX86State, regs[R_EBP])__builtin_offsetof(CPUX86State, regs[5]), "ebp");
7755 cpu_regs[R_ESI6] = tcg_global_mem_new_i32(TCG_AREG0TCG_REG_R14,
7756 offsetof(CPUX86State, regs[R_ESI])__builtin_offsetof(CPUX86State, regs[6]), "esi");
7757 cpu_regs[R_EDI7] = tcg_global_mem_new_i32(TCG_AREG0TCG_REG_R14,
7758 offsetof(CPUX86State, regs[R_EDI])__builtin_offsetof(CPUX86State, regs[7]), "edi");
7759#endif
7760
7761 /* register helpers */
7762#define GEN_HELPER 2
7763#include "helper.h"
7764}
7765
7766/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7767 basic block 'tb'. If search_pc is TRUE, also generate PC
7768 information for each intermediate instruction. */
7769static inline void gen_intermediate_code_internal(CPUX86State *env,
7770 TranslationBlock *tb,
7771 int search_pc)
7772{
7773 DisasContext dc1, *dc = &dc1;
7774 target_ulong pc_ptr;
7775 uint16_t *gen_opc_end;
7776 CPUBreakpoint *bp;
7777 int j, lj;
7778 uint64_t flags;
7779 target_ulong pc_start;
7780 target_ulong cs_base;
7781 int num_insns;
7782 int max_insns;
7783
7784 /* generate intermediate code */
7785 pc_start = tb->pc;
7786 cs_base = tb->cs_base;
7787 flags = tb->flags;
7788
7789 dc->pe = (flags >> HF_PE_SHIFT7) & 1;
7790 dc->code32 = (flags >> HF_CS32_SHIFT4) & 1;
7791 dc->ss32 = (flags >> HF_SS32_SHIFT5) & 1;
7792 dc->addseg = (flags >> HF_ADDSEG_SHIFT6) & 1;
7793 dc->f_st = 0;
7794 dc->vm86 = (flags >> VM_SHIFT17) & 1;
7795 dc->cpl = (flags >> HF_CPL_SHIFT0) & 3;
7796 dc->iopl = (flags >> IOPL_SHIFT12) & 3;
7797 dc->tf = (flags >> TF_SHIFT8) & 1;
7798 dc->singlestep_enabled = env->singlestep_enabled;
7799 dc->cc_op = CC_OP_DYNAMIC;
7800 dc->cs_base = cs_base;
7801 dc->tb = tb;
7802 dc->popl_esp_hack = 0;
7803 /* select memory access functions */
7804 dc->mem_index = 0;
7805 if (flags & HF_SOFTMMU_MASK(1 << 2)) {
7806 if (dc->cpl == 3)
7807 dc->mem_index = 2 * 4;
7808 else
7809 dc->mem_index = 1 * 4;
7810 }
7811 dc->cpuid_features = env->cpuid_features;
7812 dc->cpuid_ext_features = env->cpuid_ext_features;
7813 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7814 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7815#ifdef TARGET_X86_64
7816 dc->lma = (flags >> HF_LMA_SHIFT14) & 1;
7817 dc->code64 = (flags >> HF_CS64_SHIFT15) & 1;
7818#endif
7819 dc->flags = flags;
7820 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7821 (flags & HF_INHIBIT_IRQ_MASK(1 << 3))
7822#ifndef CONFIG_SOFTMMU1
7823 || (flags & HF_SOFTMMU_MASK(1 << 2))
7824#endif
7825 );
7826#if 0
7827 /* check addseg logic */
7828 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7829 printf("ERROR addseg\n");
7830#endif
7831
7832 cpu_T[0] = tcg_temp_new()tcg_temp_new_i32();
7833 cpu_T[1] = tcg_temp_new()tcg_temp_new_i32();
7834 cpu_A0 = tcg_temp_new()tcg_temp_new_i32();
7835 cpu_T3 = tcg_temp_new()tcg_temp_new_i32();
7836
7837 cpu_tmp0 = tcg_temp_new()tcg_temp_new_i32();
7838 cpu_tmp1_i64 = tcg_temp_new_i64();
7839 cpu_tmp2_i32 = tcg_temp_new_i32();
7840 cpu_tmp3_i32 = tcg_temp_new_i32();
7841 cpu_tmp4 = tcg_temp_new()tcg_temp_new_i32();
7842 cpu_tmp5 = tcg_temp_new()tcg_temp_new_i32();
7843 cpu_ptr0 = tcg_temp_new_ptr()__extension__ ({ TCGv_ptr make_tcgv_tmp = {((tcg_temp_new_i64
()).i64)}; make_tcgv_tmp; });
7844 cpu_ptr1 = tcg_temp_new_ptr()__extension__ ({ TCGv_ptr make_tcgv_tmp = {((tcg_temp_new_i64
()).i64)}; make_tcgv_tmp; });
7845
7846 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE(640 - 208);
7847
7848 dc->is_jmp = DISAS_NEXT0;
7849 pc_ptr = pc_start;
7850 lj = -1;
7851 num_insns = 0;
7852 max_insns = tb->cflags & CF_COUNT_MASK0x7fff;
7853 if (max_insns == 0)
7854 max_insns = CF_COUNT_MASK0x7fff;
7855
7856 gen_icount_start();
7857 for(;;) {
7858 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))__builtin_expect(!!(!((&env->breakpoints)->tqh_first
== ((void*)0))), 0)) {
7859 QTAILQ_FOREACH(bp, &env->breakpoints, entry)for ((bp) = ((&env->breakpoints)->tqh_first); (bp);
(bp) = ((bp)->entry.tqe_next)) {
7860 if (bp->pc == pc_ptr &&
7861 !((bp->flags & BP_CPU0x20) && (tb->flags & HF_RF_MASK(1 << 16)))) {
7862 gen_debug(dc, pc_ptr - dc->cs_base);
7863 break;
7864 }
7865 }
7866 }
7867 if (search_pc) {
7868 j = gen_opc_ptr - gen_opc_buf;
7869 if (lj < j) {
7870 lj++;
7871 while (lj < j)
7872 gen_opc_instr_start[lj++] = 0;
7873 }
7874 gen_opc_pc[lj] = pc_ptr;
7875 gen_opc_cc_op[lj] = dc->cc_op;
7876 gen_opc_instr_start[lj] = 1;
7877 gen_opc_icount[lj] = num_insns;
7878 }
7879 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO0x8000))
7880 gen_io_start();
7881
7882 pc_ptr = disas_insn(dc, pc_ptr);
7883 num_insns++;
7884 /* stop translation if indicated */
7885 if (dc->is_jmp)
7886 break;
7887 /* if single step mode, we generate only one instruction and
7888 generate an exception */
7889 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7890 the flag and abort the translation to give the irqs a
7891 change to be happen */
7892 if (dc->tf || dc->singlestep_enabled ||
7893 (flags & HF_INHIBIT_IRQ_MASK(1 << 3))) {
7894 gen_jmp_im(pc_ptr - dc->cs_base);
7895 gen_eob(dc);
7896 break;
7897 }
7898 /* if too long translation, stop generation too */
7899 if (gen_opc_ptr >= gen_opc_end ||
7900 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE(1 << 12) - 32) ||
7901 num_insns >= max_insns) {
7902 gen_jmp_im(pc_ptr - dc->cs_base);
7903 gen_eob(dc);
7904 break;
7905 }
7906 if (singlestep) {
7907 gen_jmp_im(pc_ptr - dc->cs_base);
7908 gen_eob(dc);
7909 break;
7910 }
7911 }
7912 if (tb->cflags & CF_LAST_IO0x8000)
7913 gen_io_end();
7914 gen_icount_end(tb, num_insns);
7915 *gen_opc_ptr = INDEX_op_end;
7916 /* we don't forget to fill the last values */
7917 if (search_pc) {
7918 j = gen_opc_ptr - gen_opc_buf;
7919 lj++;
7920 while (lj <= j)
7921 gen_opc_instr_start[lj++] = 0;
7922 }
7923
7924#ifdef DEBUG_DISAS
7925 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM(1 << 1))) {
7926 int disas_flags;
7927 qemu_log("----------------\n");
7928 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7929#ifdef TARGET_X86_64
7930 if (dc->code64)
7931 disas_flags = 2;
7932 else
7933#endif
7934 disas_flags = !dc->code32;
7935 log_target_disas(pc_start, pc_ptr - pc_start, disas_flags);
7936 qemu_log("\n");
7937 }
7938#endif
7939
7940 if (!search_pc) {
7941 tb->size = pc_ptr - pc_start;
7942 tb->icount = num_insns;
7943 }
7944}
7945
7946void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
7947{
7948 gen_intermediate_code_internal(env, tb, 0);
7949}
7950
7951void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb)
7952{
7953 gen_intermediate_code_internal(env, tb, 1);
7954}
7955
7956void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos)
7957{
7958 int cc_op;
7959#ifdef DEBUG_DISAS
7960 if (qemu_loglevel_mask(CPU_LOG_TB_OP(1 << 2))) {
7961 int i;
7962 qemu_log("RESTORE:\n");
7963 for(i = 0;i <= pc_pos; i++) {
7964 if (gen_opc_instr_start[i]) {
7965 qemu_log("0x%04x: " TARGET_FMT_lx"%08x" "\n", i, gen_opc_pc[i]);
7966 }
7967 }
7968 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx"%08x" " cs_base=%x\n",
7969 pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7970 (uint32_t)tb->cs_base);
7971 }
7972#endif
7973 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7974 cc_op = gen_opc_cc_op[pc_pos];
7975 if (cc_op != CC_OP_DYNAMIC)
7976 env->cc_op = cc_op;
7977}