Bug Summary

File:target-i386/kvm.c
Location:line 268, column 9
Description:Pass-by-value argument in function call is undefined

Annotated Source Code

1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
18#include <sys/utsname.h>
19
20#include <linux1/kvm.h>
21#include <linux1/kvm_para.h>
22
23#include "qemu-common.h"
24#include "sysemu.h"
25#include "kvm.h"
26#include "cpu.h"
27#include "gdbstub.h"
28#include "host-utils.h"
29#include "hw/pc.h"
30#include "hw/apic.h"
31#include "ioport.h"
32#include "hyperv.h"
33
34//#define DEBUG_KVM
35
36#ifdef DEBUG_KVM
37#define DPRINTF(fmt, ...)do { } while (0) \
38 do { fprintf(stderrstderr, fmt, ## __VA_ARGS__); } while (0)
39#else
40#define DPRINTF(fmt, ...)do { } while (0) \
41 do { } while (0)
42#endif
43
44#define MSR_KVM_WALL_CLOCK0x11 0x11
45#define MSR_KVM_SYSTEM_TIME0x12 0x12
46
47#ifndef BUS_MCEERR_AR4
48#define BUS_MCEERR_AR4 4
49#endif
50#ifndef BUS_MCEERR_AO5
51#define BUS_MCEERR_AO5 5
52#endif
53
54const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
55 KVM_CAP_INFO(SET_TSS_ADDR){ "KVM_CAP_" "SET_TSS_ADDR", 4 },
56 KVM_CAP_INFO(EXT_CPUID){ "KVM_CAP_" "EXT_CPUID", 7 },
57 KVM_CAP_INFO(MP_STATE){ "KVM_CAP_" "MP_STATE", 14 },
58 KVM_CAP_LAST_INFO{ ((void *)0), 0 }
59};
60
61static bool_Bool has_msr_star;
62static bool_Bool has_msr_hsave_pa;
63static bool_Bool has_msr_tsc_deadline;
64static bool_Bool has_msr_async_pf_en;
65static bool_Bool has_msr_misc_enable;
66static int lm_capable_kernel;
67
68static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
69{
70 struct kvm_cpuid2 *cpuid;
71 int r, size;
72
73 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
74 cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
75 cpuid->nent = max;
76 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID(((2U|1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +
8)) | (((0x05)) << 0) | ((((sizeof(struct kvm_cpuid2)))
) << ((0 +8)+8))), cpuid);
77 if (r == 0 && cpuid->nent >= max) {
78 r = -E2BIG7;
79 }
80 if (r < 0) {
81 if (r == -E2BIG7) {
82 g_free(cpuid);
83 return NULL((void *)0);
84 } else {
85 fprintf(stderrstderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
86 strerror(-r));
87 exit(1);
88 }
89 }
90 return cpuid;
91}
92
93struct kvm_para_features {
94 int cap;
95 int feature;
96} para_features[] = {
97 { KVM_CAP_CLOCKSOURCE8, KVM_FEATURE_CLOCKSOURCE0 },
98 { KVM_CAP_NOP_IO_DELAY12, KVM_FEATURE_NOP_IO_DELAY1 },
99 { KVM_CAP_PV_MMU13, KVM_FEATURE_MMU_OP2 },
100 { KVM_CAP_ASYNC_PF59, KVM_FEATURE_ASYNC_PF4 },
101 { -1, -1 }
102};
103
104static int get_para_features(KVMState *s)
105{
106 int i, features = 0;
107
108 for (i = 0; i < ARRAY_SIZE(para_features)(sizeof(para_features) / sizeof((para_features)[0])) - 1; i++) {
109 if (kvm_check_extension(s, para_features[i].cap)) {
110 features |= (1 << para_features[i].feature);
111 }
112 }
113
114 return features;
115}
116
117
118uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
119 uint32_t index, int reg)
120{
121 struct kvm_cpuid2 *cpuid;
122 int i, max;
123 uint32_t ret = 0;
124 uint32_t cpuid_1_edx;
125 int has_kvm_features = 0;
126
127 max = 1;
128 while ((cpuid = try_get_cpuid(s, max)) == NULL((void *)0)) {
129 max *= 2;
130 }
131
132 for (i = 0; i < cpuid->nent; ++i) {
133 if (cpuid->entries[i].function == function &&
134 cpuid->entries[i].index == index) {
135 if (cpuid->entries[i].function == KVM_CPUID_FEATURES0x40000001) {
136 has_kvm_features = 1;
137 }
138 switch (reg) {
139 case R_EAX0:
140 ret = cpuid->entries[i].eax;
141 break;
142 case R_EBX3:
143 ret = cpuid->entries[i].ebx;
144 break;
145 case R_ECX1:
146 ret = cpuid->entries[i].ecx;
147 break;
148 case R_EDX2:
149 ret = cpuid->entries[i].edx;
150 switch (function) {
151 case 1:
152 /* KVM before 2.6.30 misreports the following features */
153 ret |= CPUID_MTRR(1 << 12) | CPUID_PAT(1 << 16) | CPUID_MCE(1 << 7) | CPUID_MCA(1 << 14);
154 break;
155 case 0x80000001:
156 /* On Intel, kvm returns cpuid according to the Intel spec,
157 * so add missing bits according to the AMD spec:
158 */
159 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX2);
160 ret |= cpuid_1_edx & 0x183f7ff;
161 break;
162 }
163 break;
164 }
165 }
166 }
167
168 g_free(cpuid);
169
170 /* fallback for older kernels */
171 if (!has_kvm_features && (function == KVM_CPUID_FEATURES0x40000001)) {
172 ret = get_para_features(s);
173 }
174
175 return ret;
176}
177
178typedef struct HWPoisonPage {
179 ram_addr_t ram_addr;
180 QLIST_ENTRY(HWPoisonPage)struct { struct HWPoisonPage *le_next; struct HWPoisonPage **
le_prev; } list;
181} HWPoisonPage;
182
183static QLIST_HEAD(, HWPoisonPage)struct { struct HWPoisonPage *lh_first; } hwpoison_page_list =
184 QLIST_HEAD_INITIALIZER(hwpoison_page_list){ ((void *)0) };
185
186static void kvm_unpoison_all(void *param)
187{
188 HWPoisonPage *page, *next_page;
189
190 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page)for ((page) = ((&hwpoison_page_list)->lh_first); (page
) && ((next_page) = ((page)->list.le_next), 1); (page
) = (next_page)) {
191 QLIST_REMOVE(page, list)do { if ((page)->list.le_next != ((void *)0)) (page)->list
.le_next->list.le_prev = (page)->list.le_prev; *(page)->
list.le_prev = (page)->list.le_next; } while ( 0);
192 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE(1 << 12));
193 g_free(page);
194 }
195}
196
197static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
198{
199 HWPoisonPage *page;
200
201 QLIST_FOREACH(page, &hwpoison_page_list, list)for ((page) = ((&hwpoison_page_list)->lh_first); (page
); (page) = ((page)->list.le_next)) {
202 if (page->ram_addr == ram_addr) {
203 return;
204 }
205 }
206 page = g_malloc(sizeof(HWPoisonPage));
207 page->ram_addr = ram_addr;
208 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list)do { if (((page)->list.le_next = (&hwpoison_page_list)
->lh_first) != ((void *)0)) (&hwpoison_page_list)->
lh_first->list.le_prev = &(page)->list.le_next; (&
hwpoison_page_list)->lh_first = (page); (page)->list.le_prev
= &(&hwpoison_page_list)->lh_first; } while ( 0);
209}
210
211static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
212 int *max_banks)
213{
214 int r;
215
216 r = kvm_check_extension(s, KVM_CAP_MCE31);
217 if (r > 0) {
218 *max_banks = r;
219 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED(((2U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x9d)) << 0) | ((((sizeof(__u64)))) << ((0 +
8)+8))), mce_cap);
220 }
221 return -ENOSYS38;
222}
223
224static void kvm_mce_inject(CPUX86State *env, target_phys_addr_t paddr, int code)
225{
226 uint64_t status = MCI_STATUS_VAL(1ULL<<63) | MCI_STATUS_UC(1ULL<<61) | MCI_STATUS_EN(1ULL<<60) |
227 MCI_STATUS_MISCV(1ULL<<59) | MCI_STATUS_ADDRV(1ULL<<58) | MCI_STATUS_S(1ULL<<56);
228 uint64_t mcg_status = MCG_STATUS_MCIP(1ULL<<2);
229
230 if (code == BUS_MCEERR_AR4) {
231 status |= MCI_STATUS_AR(1ULL<<55) | 0x134;
232 mcg_status |= MCG_STATUS_EIPV(1ULL<<1);
233 } else {
234 status |= 0xc0;
235 mcg_status |= MCG_STATUS_RIPV(1ULL<<0);
236 }
237 cpu_x86_inject_mce(NULL((void *)0), env, 9, status, mcg_status, paddr,
238 (MCM_ADDR_PHYS2 << 6) | 0xc,
239 cpu_x86_support_mca_broadcast(env) ?
240 MCE_INJECT_BROADCAST1 : 0);
241}
242
243static void hardware_memory_error(void)
244{
245 fprintf(stderrstderr, "Hardware memory error!\n");
246 exit(1);
247}
248
249int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr)
250{
251 ram_addr_t ram_addr;
252 target_phys_addr_t paddr;
1
Variable 'paddr' declared without an initial value
253
254 if ((env->mcg_cap & MCG_SER_P(1ULL<<24)) && addr
2
Taking true branch
255 && (code == BUS_MCEERR_AR4 || code == BUS_MCEERR_AO5)) {
256 if (qemu_ram_addr_from_host(addr, &ram_addr) ||
3
Taking true branch
257 !kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) {
258 fprintf(stderrstderr, "Hardware memory error for memory used by "
259 "QEMU itself instead of guest system!\n");
260 /* Hope we are lucky for AO MCE */
261 if (code == BUS_MCEERR_AO5) {
4
Taking false branch
262 return 0;
263 } else {
264 hardware_memory_error();
265 }
266 }
267 kvm_hwpoison_page_add(ram_addr);
268 kvm_mce_inject(env, paddr, code);
5
Pass-by-value argument in function call is undefined
269 } else {
270 if (code == BUS_MCEERR_AO5) {
271 return 0;
272 } else if (code == BUS_MCEERR_AR4) {
273 hardware_memory_error();
274 } else {
275 return 1;
276 }
277 }
278 return 0;
279}
280
281int kvm_arch_on_sigbus(int code, void *addr)
282{
283 if ((first_cpu->mcg_cap & MCG_SER_P(1ULL<<24)) && addr && code == BUS_MCEERR_AO5) {
284 ram_addr_t ram_addr;
285 target_phys_addr_t paddr;
286
287 /* Hope we are lucky for AO MCE */
288 if (qemu_ram_addr_from_host(addr, &ram_addr) ||
289 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr,
290 &paddr)) {
291 fprintf(stderrstderr, "Hardware memory error for memory used by "
292 "QEMU itself instead of guest system!: %p\n", addr);
293 return 0;
294 }
295 kvm_hwpoison_page_add(ram_addr);
296 kvm_mce_inject(first_cpu, paddr, code);
297 } else {
298 if (code == BUS_MCEERR_AO5) {
299 return 0;
300 } else if (code == BUS_MCEERR_AR4) {
301 hardware_memory_error();
302 } else {
303 return 1;
304 }
305 }
306 return 0;
307}
308
309static int kvm_inject_mce_oldstyle(CPUX86State *env)
310{
311 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK18) {
312 unsigned int bank, bank_num = env->mcg_cap & 0xff;
313 struct kvm_x86_mce mce;
314
315 env->exception_injected = -1;
316
317 /*
318 * There must be at least one bank in use if an MCE is pending.
319 * Find it and use its values for the event injection.
320 */
321 for (bank = 0; bank < bank_num; bank++) {
322 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL(1ULL<<63)) {
323 break;
324 }
325 }
326 assert(bank < bank_num)((bank < bank_num) ? (void) (0) : __assert_fail ("bank < bank_num"
, "/home/stefan/src/qemu/qemu.org/qemu/target-i386/kvm.c", 326
, __PRETTY_FUNCTION__));
327
328 mce.bank = bank;
329 mce.status = env->mce_banks[bank * 4 + 1];
330 mce.mcg_status = env->mcg_status;
331 mce.addr = env->mce_banks[bank * 4 + 2];
332 mce.misc = env->mce_banks[bank * 4 + 3];
333
334 return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x9e)) << 0) | ((((sizeof(struct kvm_x86_mce)))) <<
((0 +8)+8))), &mce);
335 }
336 return 0;
337}
338
339static void cpu_update_state(void *opaque, int running, RunState state)
340{
341 CPUX86State *env = opaque;
342
343 if (running) {
344 env->tsc_valid = false0;
345 }
346}
347
348int kvm_arch_init_vcpu(CPUX86State *env)
349{
350 struct {
351 struct kvm_cpuid2 cpuid;
352 struct kvm_cpuid_entry2 entries[100];
353 } QEMU_PACKED__attribute__((packed)) cpuid_data;
354 KVMState *s = env->kvm_state;
355 uint32_t limit, i, j, cpuid_i;
356 uint32_t unused;
357 struct kvm_cpuid_entry2 *c;
358 uint32_t signature[3];
359 int r;
360
361 env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX2);
362
363 i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR(1 << 31);
364 env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX1);
365 env->cpuid_ext_features |= i;
366
367 env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
368 0, R_EDX2);
369 env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
370 0, R_ECX1);
371 env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(s, 0x8000000A,
372 0, R_EDX2);
373
374 cpuid_i = 0;
375
376 /* Paravirtualization CPUIDs */
377 c = &cpuid_data.entries[cpuid_i++];
378 memset(c, 0, sizeof(*c));
379 c->function = KVM_CPUID_SIGNATURE0x40000000;
380 if (!hyperv_enabled()) {
381 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
382 c->eax = 0;
383 } else {
384 memcpy(signature, "Microsoft Hv", 12);
385 c->eax = HYPERV_CPUID_MIN0x40000005;
386 }
387 c->ebx = signature[0];
388 c->ecx = signature[1];
389 c->edx = signature[2];
390
391 c = &cpuid_data.entries[cpuid_i++];
392 memset(c, 0, sizeof(*c));
393 c->function = KVM_CPUID_FEATURES0x40000001;
394 c->eax = env->cpuid_kvm_features &
395 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES0x40000001, 0, R_EAX0);
396
397 if (hyperv_enabled()) {
398 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
399 c->eax = signature[0];
400
401 c = &cpuid_data.entries[cpuid_i++];
402 memset(c, 0, sizeof(*c));
403 c->function = HYPERV_CPUID_VERSION0x40000002;
404 c->eax = 0x00001bbc;
405 c->ebx = 0x00060001;
406
407 c = &cpuid_data.entries[cpuid_i++];
408 memset(c, 0, sizeof(*c));
409 c->function = HYPERV_CPUID_FEATURES0x40000003;
410 if (hyperv_relaxed_timing_enabled()) {
411 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE(1 << 5);
412 }
413 if (hyperv_vapic_recommended()) {
414 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE(1 << 5);
415 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE(1 << 4);
416 }
417
418 c = &cpuid_data.entries[cpuid_i++];
419 memset(c, 0, sizeof(*c));
420 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO0x40000004;
421 if (hyperv_relaxed_timing_enabled()) {
422 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED(1 << 5);
423 }
424 if (hyperv_vapic_recommended()) {
425 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED(1 << 3);
426 }
427 c->ebx = hyperv_get_spinlock_retries();
428
429 c = &cpuid_data.entries[cpuid_i++];
430 memset(c, 0, sizeof(*c));
431 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS0x40000005;
432 c->eax = 0x40;
433 c->ebx = 0x40;
434
435 c = &cpuid_data.entries[cpuid_i++];
436 memset(c, 0, sizeof(*c));
437 c->function = KVM_CPUID_SIGNATURE_NEXT0x40000100;
438 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
439 c->eax = 0;
440 c->ebx = signature[0];
441 c->ecx = signature[1];
442 c->edx = signature[2];
443 }
444
445 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF4);
446
447 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
448
449 for (i = 0; i <= limit; i++) {
450 c = &cpuid_data.entries[cpuid_i++];
451
452 switch (i) {
453 case 2: {
454 /* Keep reading function 2 till all the input is received */
455 int times;
456
457 c->function = i;
458 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC2 |
459 KVM_CPUID_FLAG_STATE_READ_NEXT4;
460 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
461 times = c->eax & 0xff;
462
463 for (j = 1; j < times; ++j) {
464 c = &cpuid_data.entries[cpuid_i++];
465 c->function = i;
466 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC2;
467 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
468 }
469 break;
470 }
471 case 4:
472 case 0xb:
473 case 0xd:
474 for (j = 0; ; j++) {
475 if (i == 0xd && j == 64) {
476 break;
477 }
478 c->function = i;
479 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX1;
480 c->index = j;
481 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
482
483 if (i == 4 && c->eax == 0) {
484 break;
485 }
486 if (i == 0xb && !(c->ecx & 0xff00)) {
487 break;
488 }
489 if (i == 0xd && c->eax == 0) {
490 continue;
491 }
492 c = &cpuid_data.entries[cpuid_i++];
493 }
494 break;
495 default:
496 c->function = i;
497 c->flags = 0;
498 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
499 break;
500 }
501 }
502 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
503
504 for (i = 0x80000000; i <= limit; i++) {
505 c = &cpuid_data.entries[cpuid_i++];
506
507 c->function = i;
508 c->flags = 0;
509 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
510 }
511
512 /* Call Centaur's CPUID instructions they are supported. */
513 if (env->cpuid_xlevel2 > 0) {
514 env->cpuid_ext4_features &=
515 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX2);
516 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
517
518 for (i = 0xC0000000; i <= limit; i++) {
519 c = &cpuid_data.entries[cpuid_i++];
520
521 c->function = i;
522 c->flags = 0;
523 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
524 }
525 }
526
527 cpuid_data.cpuid.nent = cpuid_i;
528
529 if (((env->cpuid_version >> 8)&0xF) >= 6
530 && (env->cpuid_features&(CPUID_MCE(1 << 7)|CPUID_MCA(1 << 14))) == (CPUID_MCE(1 << 7)|CPUID_MCA(1 << 14))
531 && kvm_check_extension(env->kvm_state, KVM_CAP_MCE31) > 0) {
532 uint64_t mcg_cap;
533 int banks;
534 int ret;
535
536 ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
537 if (ret < 0) {
538 fprintf(stderrstderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
539 return ret;
540 }
541
542 if (banks > MCE_BANKS_DEF10) {
543 banks = MCE_BANKS_DEF10;
544 }
545 mcg_cap &= MCE_CAP_DEF((1ULL<<8)|(1ULL<<24));
546 mcg_cap |= banks;
547 ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x9c)) << 0) | ((((sizeof(__u64)))) << ((0 +
8)+8))), &mcg_cap);
548 if (ret < 0) {
549 fprintf(stderrstderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
550 return ret;
551 }
552
553 env->mcg_cap = mcg_cap;
554 }
555
556 qemu_add_vm_change_state_handler(cpu_update_state, env);
557
558 cpuid_data.cpuid.padding = 0;
559 r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x90)) << 0) | ((((sizeof(struct kvm_cpuid2)))) <<
((0 +8)+8))), &cpuid_data);
560 if (r) {
561 return r;
562 }
563
564 r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL60);
565 if (r && env->tsc_khz) {
566 r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ(((0U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0xa2)) << 0) | ((0) << ((0 +8)+8))), env->tsc_khz);
567 if (r < 0) {
568 fprintf(stderrstderr, "KVM_SET_TSC_KHZ failed\n");
569 return r;
570 }
571 }
572
573 if (kvm_has_xsave()) {
574 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
575 }
576
577 return 0;
578}
579
580void kvm_arch_reset_vcpu(CPUX86State *env)
581{
582 env->exception_injected = -1;
583 env->interrupt_injected = -1;
584 env->xcr0 = 1;
585 if (kvm_irqchip_in_kernel()(kvm_kernel_irqchip)) {
586 env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE0 :
587 KVM_MP_STATE_UNINITIALIZED1;
588 } else {
589 env->mp_state = KVM_MP_STATE_RUNNABLE0;
590 }
591}
592
593static int kvm_get_supported_msrs(KVMState *s)
594{
595 static int kvm_supported_msrs;
596 int ret = 0;
597
598 /* first time */
599 if (kvm_supported_msrs == 0) {
600 struct kvm_msr_list msr_list, *kvm_msr_list;
601
602 kvm_supported_msrs = -1;
603
604 /* Obtain MSR list from KVM. These are the MSRs that we must
605 * save/restore */
606 msr_list.nmsrs = 0;
607 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST(((2U|1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +
8)) | (((0x02)) << 0) | ((((sizeof(struct kvm_msr_list)
))) << ((0 +8)+8))), &msr_list);
608 if (ret < 0 && ret != -E2BIG7) {
609 return ret;
610 }
611 /* Old kernel modules had a bug and could write beyond the provided
612 memory. Allocate at least a safe amount of 1K. */
613 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +(((1024) > (sizeof(msr_list) + msr_list.nmsrs * sizeof(msr_list
.indices[0]))) ? (1024) : (sizeof(msr_list) + msr_list.nmsrs *
sizeof(msr_list.indices[0])))
614 msr_list.nmsrs *(((1024) > (sizeof(msr_list) + msr_list.nmsrs * sizeof(msr_list
.indices[0]))) ? (1024) : (sizeof(msr_list) + msr_list.nmsrs *
sizeof(msr_list.indices[0])))
615 sizeof(msr_list.indices[0]))(((1024) > (sizeof(msr_list) + msr_list.nmsrs * sizeof(msr_list
.indices[0]))) ? (1024) : (sizeof(msr_list) + msr_list.nmsrs *
sizeof(msr_list.indices[0]))));
616
617 kvm_msr_list->nmsrs = msr_list.nmsrs;
618 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST(((2U|1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +
8)) | (((0x02)) << 0) | ((((sizeof(struct kvm_msr_list)
))) << ((0 +8)+8))), kvm_msr_list);
619 if (ret >= 0) {
620 int i;
621
622 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
623 if (kvm_msr_list->indices[i] == MSR_STAR0xc0000081) {
624 has_msr_star = true1;
625 continue;
626 }
627 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA0xc0010117) {
628 has_msr_hsave_pa = true1;
629 continue;
630 }
631 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE0x6e0) {
632 has_msr_tsc_deadline = true1;
633 continue;
634 }
635 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE0x1a0) {
636 has_msr_misc_enable = true1;
637 continue;
638 }
639 }
640 }
641
642 g_free(kvm_msr_list);
643 }
644
645 return ret;
646}
647
648int kvm_arch_init(KVMState *s)
649{
650 QemuOptsList *list = qemu_find_opts("machine");
651 uint64_t identity_base = 0xfffbc000;
652 uint64_t shadow_mem;
653 int ret;
654 struct utsname utsname;
655
656 ret = kvm_get_supported_msrs(s);
657 if (ret < 0) {
658 return ret;
659 }
660
661 uname(&utsname);
662 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
663
664 /*
665 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
666 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
667 * Since these must be part of guest physical memory, we need to allocate
668 * them, both by setting their start addresses in the kernel and by
669 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
670 *
671 * Older KVM versions may not support setting the identity map base. In
672 * that case we need to stick with the default, i.e. a 256K maximum BIOS
673 * size.
674 */
675 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR37)) {
676 /* Allows up to 16M BIOSes. */
677 identity_base = 0xfeffc000;
678
679 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x48)) << 0) | ((((sizeof(__u64)))) << ((0 +
8)+8))), &identity_base);
680 if (ret < 0) {
681 return ret;
682 }
683 }
684
685 /* Set TSS base one page after EPT identity map. */
686 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR(((0U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x47)) << 0) | ((0) << ((0 +8)+8))), identity_base + 0x1000);
687 if (ret < 0) {
688 return ret;
689 }
690
691 /* Tell fw_cfg to notify the BIOS to reserve the range. */
692 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED2);
693 if (ret < 0) {
694 fprintf(stderrstderr, "e820_add_entry() table is full\n");
695 return ret;
696 }
697 qemu_register_reset(kvm_unpoison_all, NULL((void *)0));
698
699 if (!QTAILQ_EMPTY(&list->head)((&list->head)->tqh_first == ((void *)0))) {
700 shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head)((&list->head)->tqh_first),
701 "kvm_shadow_mem", -1);
702 if (shadow_mem != -1) {
703 shadow_mem /= 4096;
704 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES(((0U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x44)) << 0) | ((0) << ((0 +8)+8))), shadow_mem);
705 if (ret < 0) {
706 return ret;
707 }
708 }
709 }
710 return 0;
711}
712
713static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
714{
715 lhs->selector = rhs->selector;
716 lhs->base = rhs->base;
717 lhs->limit = rhs->limit;
718 lhs->type = 3;
719 lhs->present = 1;
720 lhs->dpl = 3;
721 lhs->db = 0;
722 lhs->s = 1;
723 lhs->l = 0;
724 lhs->g = 0;
725 lhs->avl = 0;
726 lhs->unusable = 0;
727}
728
729static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
730{
731 unsigned flags = rhs->flags;
732 lhs->selector = rhs->selector;
733 lhs->base = rhs->base;
734 lhs->limit = rhs->limit;
735 lhs->type = (flags >> DESC_TYPE_SHIFT8) & 15;
736 lhs->present = (flags & DESC_P_MASK(1 << 15)) != 0;
737 lhs->dpl = (flags >> DESC_DPL_SHIFT13) & 3;
738 lhs->db = (flags >> DESC_B_SHIFT22) & 1;
739 lhs->s = (flags & DESC_S_MASK(1 << 12)) != 0;
740 lhs->l = (flags >> DESC_L_SHIFT21) & 1;
741 lhs->g = (flags & DESC_G_MASK(1 << 23)) != 0;
742 lhs->avl = (flags & DESC_AVL_MASK(1 << 20)) != 0;
743 lhs->unusable = 0;
744 lhs->padding = 0;
745}
746
747static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
748{
749 lhs->selector = rhs->selector;
750 lhs->base = rhs->base;
751 lhs->limit = rhs->limit;
752 lhs->flags = (rhs->type << DESC_TYPE_SHIFT8) |
753 (rhs->present * DESC_P_MASK(1 << 15)) |
754 (rhs->dpl << DESC_DPL_SHIFT13) |
755 (rhs->db << DESC_B_SHIFT22) |
756 (rhs->s * DESC_S_MASK(1 << 12)) |
757 (rhs->l << DESC_L_SHIFT21) |
758 (rhs->g * DESC_G_MASK(1 << 23)) |
759 (rhs->avl * DESC_AVL_MASK(1 << 20));
760}
761
762static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
763{
764 if (set) {
765 *kvm_reg = *qemu_reg;
766 } else {
767 *qemu_reg = *kvm_reg;
768 }
769}
770
771static int kvm_getput_regs(CPUX86State *env, int set)
772{
773 struct kvm_regs regs;
774 int ret = 0;
775
776 if (!set) {
777 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS(((2U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x81)) << 0) | ((((sizeof(struct kvm_regs)))) <<
((0 +8)+8))), &regs);
778 if (ret < 0) {
779 return ret;
780 }
781 }
782
783 kvm_getput_reg(&regs.rax, &env->regs[R_EAX0], set);
784 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX3], set);
785 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX1], set);
786 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX2], set);
787 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI6], set);
788 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI7], set);
789 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP4], set);
790 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP5], set);
791#ifdef TARGET_X86_641
792 kvm_getput_reg(&regs.r8, &env->regs[8], set);
793 kvm_getput_reg(&regs.r9, &env->regs[9], set);
794 kvm_getput_reg(&regs.r10, &env->regs[10], set);
795 kvm_getput_reg(&regs.r11, &env->regs[11], set);
796 kvm_getput_reg(&regs.r12, &env->regs[12], set);
797 kvm_getput_reg(&regs.r13, &env->regs[13], set);
798 kvm_getput_reg(&regs.r14, &env->regs[14], set);
799 kvm_getput_reg(&regs.r15, &env->regs[15], set);
800#endif
801
802 kvm_getput_reg(&regs.rflags, &env->eflags, set);
803 kvm_getput_reg(&regs.rip, &env->eip, set);
804
805 if (set) {
806 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x82)) << 0) | ((((sizeof(struct kvm_regs)))) <<
((0 +8)+8))), &regs);
807 }
808
809 return ret;
810}
811
812static int kvm_put_fpu(CPUX86State *env)
813{
814 struct kvm_fpu fpu;
815 int i;
816
817 memset(&fpu, 0, sizeof fpu);
818 fpu.fsw = env->fpus & ~(7 << 11);
819 fpu.fsw |= (env->fpstt & 7) << 11;
820 fpu.fcw = env->fpuc;
821 fpu.last_opcode = env->fpop;
822 fpu.last_ip = env->fpip;
823 fpu.last_dp = env->fpdp;
824 for (i = 0; i < 8; ++i) {
825 fpu.ftwx |= (!env->fptags[i]) << i;
826 }
827 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
828 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
829 fpu.mxcsr = env->mxcsr;
830
831 return kvm_vcpu_ioctl(env, KVM_SET_FPU(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x8d)) << 0) | ((((sizeof(struct kvm_fpu)))) <<
((0 +8)+8))), &fpu);
832}
833
834#define XSAVE_FCW_FSW0 0
835#define XSAVE_FTW_FOP1 1
836#define XSAVE_CWD_RIP2 2
837#define XSAVE_CWD_RDP4 4
838#define XSAVE_MXCSR6 6
839#define XSAVE_ST_SPACE8 8
840#define XSAVE_XMM_SPACE40 40
841#define XSAVE_XSTATE_BV128 128
842#define XSAVE_YMMH_SPACE144 144
843
844static int kvm_put_xsave(CPUX86State *env)
845{
846 struct kvm_xsave* xsave = env->kvm_xsave_buf;
847 uint16_t cwd, swd, twd;
848 int i, r;
849
850 if (!kvm_has_xsave()) {
851 return kvm_put_fpu(env);
852 }
853
854 memset(xsave, 0, sizeof(struct kvm_xsave));
855 twd = 0;
856 swd = env->fpus & ~(7 << 11);
857 swd |= (env->fpstt & 7) << 11;
858 cwd = env->fpuc;
859 for (i = 0; i < 8; ++i) {
860 twd |= (!env->fptags[i]) << i;
861 }
862 xsave->region[XSAVE_FCW_FSW0] = (uint32_t)(swd << 16) + cwd;
863 xsave->region[XSAVE_FTW_FOP1] = (uint32_t)(env->fpop << 16) + twd;
864 memcpy(&xsave->region[XSAVE_CWD_RIP2], &env->fpip, sizeof(env->fpip));
865 memcpy(&xsave->region[XSAVE_CWD_RDP4], &env->fpdp, sizeof(env->fpdp));
866 memcpy(&xsave->region[XSAVE_ST_SPACE8], env->fpregs,
867 sizeof env->fpregs);
868 memcpy(&xsave->region[XSAVE_XMM_SPACE40], env->xmm_regs,
869 sizeof env->xmm_regs);
870 xsave->region[XSAVE_MXCSR6] = env->mxcsr;
871 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV128] = env->xstate_bv;
872 memcpy(&xsave->region[XSAVE_YMMH_SPACE144], env->ymmh_regs,
873 sizeof env->ymmh_regs);
874 r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0xa5)) << 0) | ((((sizeof(struct kvm_xsave)))) <<
((0 +8)+8))), xsave);
875 return r;
876}
877
878static int kvm_put_xcrs(CPUX86State *env)
879{
880 struct kvm_xcrs xcrs;
881
882 if (!kvm_has_xcrs()) {
883 return 0;
884 }
885
886 xcrs.nr_xcrs = 1;
887 xcrs.flags = 0;
888 xcrs.xcrs[0].xcr = 0;
889 xcrs.xcrs[0].value = env->xcr0;
890 return kvm_vcpu_ioctl(env, KVM_SET_XCRS(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0xa7)) << 0) | ((((sizeof(struct kvm_xcrs)))) <<
((0 +8)+8))), &xcrs);
891}
892
893static int kvm_put_sregs(CPUX86State *env)
894{
895 struct kvm_sregs sregs;
896
897 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
898 if (env->interrupt_injected >= 0) {
899 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
900 (uint64_t)1 << (env->interrupt_injected % 64);
901 }
902
903 if ((env->eflags & VM_MASK0x00020000)) {
904 set_v8086_seg(&sregs.cs, &env->segs[R_CS1]);
905 set_v8086_seg(&sregs.ds, &env->segs[R_DS3]);
906 set_v8086_seg(&sregs.es, &env->segs[R_ES0]);
907 set_v8086_seg(&sregs.fs, &env->segs[R_FS4]);
908 set_v8086_seg(&sregs.gs, &env->segs[R_GS5]);
909 set_v8086_seg(&sregs.ss, &env->segs[R_SS2]);
910 } else {
911 set_seg(&sregs.cs, &env->segs[R_CS1]);
912 set_seg(&sregs.ds, &env->segs[R_DS3]);
913 set_seg(&sregs.es, &env->segs[R_ES0]);
914 set_seg(&sregs.fs, &env->segs[R_FS4]);
915 set_seg(&sregs.gs, &env->segs[R_GS5]);
916 set_seg(&sregs.ss, &env->segs[R_SS2]);
917 }
918
919 set_seg(&sregs.tr, &env->tr);
920 set_seg(&sregs.ldt, &env->ldt);
921
922 sregs.idt.limit = env->idt.limit;
923 sregs.idt.base = env->idt.base;
924 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
925 sregs.gdt.limit = env->gdt.limit;
926 sregs.gdt.base = env->gdt.base;
927 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
928
929 sregs.cr0 = env->cr[0];
930 sregs.cr2 = env->cr[2];
931 sregs.cr3 = env->cr[3];
932 sregs.cr4 = env->cr[4];
933
934 sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
935 sregs.apic_base = cpu_get_apic_base(env->apic_state);
936
937 sregs.efer = env->efer;
938
939 return kvm_vcpu_ioctl(env, KVM_SET_SREGS(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x84)) << 0) | ((((sizeof(struct kvm_sregs)))) <<
((0 +8)+8))), &sregs);
940}
941
942static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
943 uint32_t index, uint64_t value)
944{
945 entry->index = index;
946 entry->data = value;
947}
948
949static int kvm_put_msrs(CPUX86State *env, int level)
950{
951 struct {
952 struct kvm_msrs info;
953 struct kvm_msr_entry entries[100];
954 } msr_data;
955 struct kvm_msr_entry *msrs = msr_data.entries;
956 int n = 0;
957
958 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS0x174, env->sysenter_cs);
959 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP0x175, env->sysenter_esp);
960 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP0x176, env->sysenter_eip);
961 kvm_msr_entry_set(&msrs[n++], MSR_PAT0x277, env->pat);
962 if (has_msr_star) {
963 kvm_msr_entry_set(&msrs[n++], MSR_STAR0xc0000081, env->star);
964 }
965 if (has_msr_hsave_pa) {
966 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA0xc0010117, env->vm_hsave);
967 }
968 if (has_msr_tsc_deadline) {
969 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE0x6e0, env->tsc_deadline);
970 }
971 if (has_msr_misc_enable) {
972 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE0x1a0,
973 env->msr_ia32_misc_enable);
974 }
975#ifdef TARGET_X86_641
976 if (lm_capable_kernel) {
977 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR0xc0000083, env->cstar);
978 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE0xc0000102, env->kernelgsbase);
979 kvm_msr_entry_set(&msrs[n++], MSR_FMASK0xc0000084, env->fmask);
980 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR0xc0000082, env->lstar);
981 }
982#endif
983 if (level == KVM_PUT_FULL_STATE3) {
984 /*
985 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
986 * writeback. Until this is fixed, we only write the offset to SMP
987 * guests after migration, desynchronizing the VCPUs, but avoiding
988 * huge jump-backs that would occur without any writeback at all.
989 */
990 if (smp_cpus == 1 || env->tsc != 0) {
991 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC0x10, env->tsc);
992 }
993 }
994 /*
995 * The following paravirtual MSRs have side effects on the guest or are
996 * too heavy for normal writeback. Limit them to reset or full state
997 * updates.
998 */
999 if (level >= KVM_PUT_RESET_STATE2) {
1000 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME0x12,
1001 env->system_time_msr);
1002 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK0x11, env->wall_clock_msr);
1003 if (has_msr_async_pf_en) {
1004 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN0x4b564d02,
1005 env->async_pf_en_msr);
1006 }
1007 if (hyperv_hypercall_available()) {
1008 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID0x40000000, 0);
1009 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL0x40000001, 0);
1010 }
1011 if (hyperv_vapic_recommended()) {
1012 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE0x40000073, 0);
1013 }
1014 }
1015 if (env->mcg_cap) {
1016 int i;
1017
1018 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS0x17a, env->mcg_status);
1019 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL0x17b, env->mcg_ctl);
1020 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1021 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL0x400 + i, env->mce_banks[i]);
1022 }
1023 }
1024
1025 msr_data.info.nmsrs = n;
1026
1027 return kvm_vcpu_ioctl(env, KVM_SET_MSRS(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x89)) << 0) | ((((sizeof(struct kvm_msrs)))) <<
((0 +8)+8))), &msr_data);
1028
1029}
1030
1031
1032static int kvm_get_fpu(CPUX86State *env)
1033{
1034 struct kvm_fpu fpu;
1035 int i, ret;
1036
1037 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU(((2U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x8c)) << 0) | ((((sizeof(struct kvm_fpu)))) <<
((0 +8)+8))), &fpu);
1038 if (ret < 0) {
1039 return ret;
1040 }
1041
1042 env->fpstt = (fpu.fsw >> 11) & 7;
1043 env->fpus = fpu.fsw;
1044 env->fpuc = fpu.fcw;
1045 env->fpop = fpu.last_opcode;
1046 env->fpip = fpu.last_ip;
1047 env->fpdp = fpu.last_dp;
1048 for (i = 0; i < 8; ++i) {
1049 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1050 }
1051 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1052 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1053 env->mxcsr = fpu.mxcsr;
1054
1055 return 0;
1056}
1057
1058static int kvm_get_xsave(CPUX86State *env)
1059{
1060 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1061 int ret, i;
1062 uint16_t cwd, swd, twd;
1063
1064 if (!kvm_has_xsave()) {
1065 return kvm_get_fpu(env);
1066 }
1067
1068 ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE(((2U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0xa4)) << 0) | ((((sizeof(struct kvm_xsave)))) <<
((0 +8)+8))), xsave);
1069 if (ret < 0) {
1070 return ret;
1071 }
1072
1073 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW0];
1074 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW0] >> 16);
1075 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP1];
1076 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP1] >> 16);
1077 env->fpstt = (swd >> 11) & 7;
1078 env->fpus = swd;
1079 env->fpuc = cwd;
1080 for (i = 0; i < 8; ++i) {
1081 env->fptags[i] = !((twd >> i) & 1);
1082 }
1083 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP2], sizeof(env->fpip));
1084 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP4], sizeof(env->fpdp));
1085 env->mxcsr = xsave->region[XSAVE_MXCSR6];
1086 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE8],
1087 sizeof env->fpregs);
1088 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE40],
1089 sizeof env->xmm_regs);
1090 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV128];
1091 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE144],
1092 sizeof env->ymmh_regs);
1093 return 0;
1094}
1095
1096static int kvm_get_xcrs(CPUX86State *env)
1097{
1098 int i, ret;
1099 struct kvm_xcrs xcrs;
1100
1101 if (!kvm_has_xcrs()) {
1102 return 0;
1103 }
1104
1105 ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS(((2U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0xa6)) << 0) | ((((sizeof(struct kvm_xcrs)))) <<
((0 +8)+8))), &xcrs);
1106 if (ret < 0) {
1107 return ret;
1108 }
1109
1110 for (i = 0; i < xcrs.nr_xcrs; i++) {
1111 /* Only support xcr0 now */
1112 if (xcrs.xcrs[0].xcr == 0) {
1113 env->xcr0 = xcrs.xcrs[0].value;
1114 break;
1115 }
1116 }
1117 return 0;
1118}
1119
1120static int kvm_get_sregs(CPUX86State *env)
1121{
1122 struct kvm_sregs sregs;
1123 uint32_t hflags;
1124 int bit, i, ret;
1125
1126 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS(((2U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x83)) << 0) | ((((sizeof(struct kvm_sregs)))) <<
((0 +8)+8))), &sregs);
1127 if (ret < 0) {
1128 return ret;
1129 }
1130
1131 /* There can only be one pending IRQ set in the bitmap at a time, so try
1132 to find it and save its number instead (-1 for none). */
1133 env->interrupt_injected = -1;
1134 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap)(sizeof(sregs.interrupt_bitmap) / sizeof((sregs.interrupt_bitmap
)[0])); i++) {
1135 if (sregs.interrupt_bitmap[i]) {
1136 bit = ctz64(sregs.interrupt_bitmap[i]);
1137 env->interrupt_injected = i * 64 + bit;
1138 break;
1139 }
1140 }
1141
1142 get_seg(&env->segs[R_CS1], &sregs.cs);
1143 get_seg(&env->segs[R_DS3], &sregs.ds);
1144 get_seg(&env->segs[R_ES0], &sregs.es);
1145 get_seg(&env->segs[R_FS4], &sregs.fs);
1146 get_seg(&env->segs[R_GS5], &sregs.gs);
1147 get_seg(&env->segs[R_SS2], &sregs.ss);
1148
1149 get_seg(&env->tr, &sregs.tr);
1150 get_seg(&env->ldt, &sregs.ldt);
1151
1152 env->idt.limit = sregs.idt.limit;
1153 env->idt.base = sregs.idt.base;
1154 env->gdt.limit = sregs.gdt.limit;
1155 env->gdt.base = sregs.gdt.base;
1156
1157 env->cr[0] = sregs.cr0;
1158 env->cr[2] = sregs.cr2;
1159 env->cr[3] = sregs.cr3;
1160 env->cr[4] = sregs.cr4;
1161
1162 env->efer = sregs.efer;
1163
1164 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1165
1166#define HFLAG_COPY_MASK~( (3 << 0) | (1 << 7) | (1 << 9) | (1 <<
10) | (1 << 11) | (1 << 8) | (1 << 17) | (
3 << 12) | (1 << 22) | (1 << 14) | (1 <<
4) | (1 << 5) | (1 << 15) | (1 << 6)) \
1167 ~( HF_CPL_MASK(3 << 0) | HF_PE_MASK(1 << 7) | HF_MP_MASK(1 << 9) | HF_EM_MASK(1 << 10) | \
1168 HF_TS_MASK(1 << 11) | HF_TF_MASK(1 << 8) | HF_VM_MASK(1 << 17) | HF_IOPL_MASK(3 << 12) | \
1169 HF_OSFXSR_MASK(1 << 22) | HF_LMA_MASK(1 << 14) | HF_CS32_MASK(1 << 4) | \
1170 HF_SS32_MASK(1 << 5) | HF_CS64_MASK(1 << 15) | HF_ADDSEG_MASK(1 << 6))
1171
1172 hflags = (env->segs[R_CS1].flags >> DESC_DPL_SHIFT13) & HF_CPL_MASK(3 << 0);
1173 hflags |= (env->cr[0] & CR0_PE_MASK(1 << 0)) << (HF_PE_SHIFT7 - CR0_PE_SHIFT0);
1174 hflags |= (env->cr[0] << (HF_MP_SHIFT9 - CR0_MP_SHIFT1)) &
1175 (HF_MP_MASK(1 << 9) | HF_EM_MASK(1 << 10) | HF_TS_MASK(1 << 11));
1176 hflags |= (env->eflags & (HF_TF_MASK(1 << 8) | HF_VM_MASK(1 << 17) | HF_IOPL_MASK(3 << 12)));
1177 hflags |= (env->cr[4] & CR4_OSFXSR_MASK(1 << 9)) <<
1178 (HF_OSFXSR_SHIFT22 - CR4_OSFXSR_SHIFT9);
1179
1180 if (env->efer & MSR_EFER_LMA(1 << 10)) {
1181 hflags |= HF_LMA_MASK(1 << 14);
1182 }
1183
1184 if ((hflags & HF_LMA_MASK(1 << 14)) && (env->segs[R_CS1].flags & DESC_L_MASK(1 << 21))) {
1185 hflags |= HF_CS32_MASK(1 << 4) | HF_SS32_MASK(1 << 5) | HF_CS64_MASK(1 << 15);
1186 } else {
1187 hflags |= (env->segs[R_CS1].flags & DESC_B_MASK(1 << 22)) >>
1188 (DESC_B_SHIFT22 - HF_CS32_SHIFT4);
1189 hflags |= (env->segs[R_SS2].flags & DESC_B_MASK(1 << 22)) >>
1190 (DESC_B_SHIFT22 - HF_SS32_SHIFT5);
1191 if (!(env->cr[0] & CR0_PE_MASK(1 << 0)) || (env->eflags & VM_MASK0x00020000) ||
1192 !(hflags & HF_CS32_MASK(1 << 4))) {
1193 hflags |= HF_ADDSEG_MASK(1 << 6);
1194 } else {
1195 hflags |= ((env->segs[R_DS3].base | env->segs[R_ES0].base |
1196 env->segs[R_SS2].base) != 0) << HF_ADDSEG_SHIFT6;
1197 }
1198 }
1199 env->hflags = (env->hflags & HFLAG_COPY_MASK~( (3 << 0) | (1 << 7) | (1 << 9) | (1 <<
10) | (1 << 11) | (1 << 8) | (1 << 17) | (
3 << 12) | (1 << 22) | (1 << 14) | (1 <<
4) | (1 << 5) | (1 << 15) | (1 << 6))) | hflags;
1200
1201 return 0;
1202}
1203
1204static int kvm_get_msrs(CPUX86State *env)
1205{
1206 struct {
1207 struct kvm_msrs info;
1208 struct kvm_msr_entry entries[100];
1209 } msr_data;
1210 struct kvm_msr_entry *msrs = msr_data.entries;
1211 int ret, i, n;
1212
1213 n = 0;
1214 msrs[n++].index = MSR_IA32_SYSENTER_CS0x174;
1215 msrs[n++].index = MSR_IA32_SYSENTER_ESP0x175;
1216 msrs[n++].index = MSR_IA32_SYSENTER_EIP0x176;
1217 msrs[n++].index = MSR_PAT0x277;
1218 if (has_msr_star) {
1219 msrs[n++].index = MSR_STAR0xc0000081;
1220 }
1221 if (has_msr_hsave_pa) {
1222 msrs[n++].index = MSR_VM_HSAVE_PA0xc0010117;
1223 }
1224 if (has_msr_tsc_deadline) {
1225 msrs[n++].index = MSR_IA32_TSCDEADLINE0x6e0;
1226 }
1227 if (has_msr_misc_enable) {
1228 msrs[n++].index = MSR_IA32_MISC_ENABLE0x1a0;
1229 }
1230
1231 if (!env->tsc_valid) {
1232 msrs[n++].index = MSR_IA32_TSC0x10;
1233 env->tsc_valid = !runstate_is_running();
1234 }
1235
1236#ifdef TARGET_X86_641
1237 if (lm_capable_kernel) {
1238 msrs[n++].index = MSR_CSTAR0xc0000083;
1239 msrs[n++].index = MSR_KERNELGSBASE0xc0000102;
1240 msrs[n++].index = MSR_FMASK0xc0000084;
1241 msrs[n++].index = MSR_LSTAR0xc0000082;
1242 }
1243#endif
1244 msrs[n++].index = MSR_KVM_SYSTEM_TIME0x12;
1245 msrs[n++].index = MSR_KVM_WALL_CLOCK0x11;
1246 if (has_msr_async_pf_en) {
1247 msrs[n++].index = MSR_KVM_ASYNC_PF_EN0x4b564d02;
1248 }
1249
1250 if (env->mcg_cap) {
1251 msrs[n++].index = MSR_MCG_STATUS0x17a;
1252 msrs[n++].index = MSR_MCG_CTL0x17b;
1253 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1254 msrs[n++].index = MSR_MC0_CTL0x400 + i;
1255 }
1256 }
1257
1258 msr_data.info.nmsrs = n;
1259 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS(((2U|1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +
8)) | (((0x88)) << 0) | ((((sizeof(struct kvm_msrs)))) <<
((0 +8)+8))), &msr_data);
1260 if (ret < 0) {
1261 return ret;
1262 }
1263
1264 for (i = 0; i < ret; i++) {
1265 switch (msrs[i].index) {
1266 case MSR_IA32_SYSENTER_CS0x174:
1267 env->sysenter_cs = msrs[i].data;
1268 break;
1269 case MSR_IA32_SYSENTER_ESP0x175:
1270 env->sysenter_esp = msrs[i].data;
1271 break;
1272 case MSR_IA32_SYSENTER_EIP0x176:
1273 env->sysenter_eip = msrs[i].data;
1274 break;
1275 case MSR_PAT0x277:
1276 env->pat = msrs[i].data;
1277 break;
1278 case MSR_STAR0xc0000081:
1279 env->star = msrs[i].data;
1280 break;
1281#ifdef TARGET_X86_641
1282 case MSR_CSTAR0xc0000083:
1283 env->cstar = msrs[i].data;
1284 break;
1285 case MSR_KERNELGSBASE0xc0000102:
1286 env->kernelgsbase = msrs[i].data;
1287 break;
1288 case MSR_FMASK0xc0000084:
1289 env->fmask = msrs[i].data;
1290 break;
1291 case MSR_LSTAR0xc0000082:
1292 env->lstar = msrs[i].data;
1293 break;
1294#endif
1295 case MSR_IA32_TSC0x10:
1296 env->tsc = msrs[i].data;
1297 break;
1298 case MSR_IA32_TSCDEADLINE0x6e0:
1299 env->tsc_deadline = msrs[i].data;
1300 break;
1301 case MSR_VM_HSAVE_PA0xc0010117:
1302 env->vm_hsave = msrs[i].data;
1303 break;
1304 case MSR_KVM_SYSTEM_TIME0x12:
1305 env->system_time_msr = msrs[i].data;
1306 break;
1307 case MSR_KVM_WALL_CLOCK0x11:
1308 env->wall_clock_msr = msrs[i].data;
1309 break;
1310 case MSR_MCG_STATUS0x17a:
1311 env->mcg_status = msrs[i].data;
1312 break;
1313 case MSR_MCG_CTL0x17b:
1314 env->mcg_ctl = msrs[i].data;
1315 break;
1316 case MSR_IA32_MISC_ENABLE0x1a0:
1317 env->msr_ia32_misc_enable = msrs[i].data;
1318 break;
1319 default:
1320 if (msrs[i].index >= MSR_MC0_CTL0x400 &&
1321 msrs[i].index < MSR_MC0_CTL0x400 + (env->mcg_cap & 0xff) * 4) {
1322 env->mce_banks[msrs[i].index - MSR_MC0_CTL0x400] = msrs[i].data;
1323 }
1324 break;
1325 case MSR_KVM_ASYNC_PF_EN0x4b564d02:
1326 env->async_pf_en_msr = msrs[i].data;
1327 break;
1328 }
1329 }
1330
1331 return 0;
1332}
1333
1334static int kvm_put_mp_state(CPUX86State *env)
1335{
1336 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1337
1338 return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x99)) << 0) | ((((sizeof(struct kvm_mp_state))))
<< ((0 +8)+8))), &mp_state);
1339}
1340
1341static int kvm_get_mp_state(CPUX86State *env)
1342{
1343 struct kvm_mp_state mp_state;
1344 int ret;
1345
1346 ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE(((2U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x98)) << 0) | ((((sizeof(struct kvm_mp_state))))
<< ((0 +8)+8))), &mp_state);
1347 if (ret < 0) {
1348 return ret;
1349 }
1350 env->mp_state = mp_state.mp_state;
1351 if (kvm_irqchip_in_kernel()(kvm_kernel_irqchip)) {
1352 env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED3);
1353 }
1354 return 0;
1355}
1356
1357static int kvm_get_apic(CPUX86State *env)
1358{
1359 DeviceState *apic = env->apic_state;
1360 struct kvm_lapic_state kapic;
1361 int ret;
1362
1363 if (apic && kvm_irqchip_in_kernel()(kvm_kernel_irqchip)) {
1364 ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC(((2U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x8e)) << 0) | ((((sizeof(struct kvm_lapic_state)
))) << ((0 +8)+8))), &kapic);
1365 if (ret < 0) {
1366 return ret;
1367 }
1368
1369 kvm_get_apic_state(apic, &kapic);
1370 }
1371 return 0;
1372}
1373
1374static int kvm_put_apic(CPUX86State *env)
1375{
1376 DeviceState *apic = env->apic_state;
1377 struct kvm_lapic_state kapic;
1378
1379 if (apic && kvm_irqchip_in_kernel()(kvm_kernel_irqchip)) {
1380 kvm_put_apic_state(apic, &kapic);
1381
1382 return kvm_vcpu_ioctl(env, KVM_SET_LAPIC(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x8f)) << 0) | ((((sizeof(struct kvm_lapic_state)
))) << ((0 +8)+8))), &kapic);
1383 }
1384 return 0;
1385}
1386
1387static int kvm_put_vcpu_events(CPUX86State *env, int level)
1388{
1389 struct kvm_vcpu_events events;
1390
1391 if (!kvm_has_vcpu_events()) {
1392 return 0;
1393 }
1394
1395 events.exception.injected = (env->exception_injected >= 0);
1396 events.exception.nr = env->exception_injected;
1397 events.exception.has_error_code = env->has_error_code;
1398 events.exception.error_code = env->error_code;
1399 events.exception.pad = 0;
1400
1401 events.interrupt.injected = (env->interrupt_injected >= 0);
1402 events.interrupt.nr = env->interrupt_injected;
1403 events.interrupt.soft = env->soft_interrupt;
1404
1405 events.nmi.injected = env->nmi_injected;
1406 events.nmi.pending = env->nmi_pending;
1407 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK(1 << 2));
1408 events.nmi.pad = 0;
1409
1410 events.sipi_vector = env->sipi_vector;
1411
1412 events.flags = 0;
1413 if (level >= KVM_PUT_RESET_STATE2) {
1414 events.flags |=
1415 KVM_VCPUEVENT_VALID_NMI_PENDING0x00000001 | KVM_VCPUEVENT_VALID_SIPI_VECTOR0x00000002;
1416 }
1417
1418 return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0xa0)) << 0) | ((((sizeof(struct kvm_vcpu_events)
))) << ((0 +8)+8))), &events);
1419}
1420
1421static int kvm_get_vcpu_events(CPUX86State *env)
1422{
1423 struct kvm_vcpu_events events;
1424 int ret;
1425
1426 if (!kvm_has_vcpu_events()) {
1427 return 0;
1428 }
1429
1430 ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS(((2U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x9f)) << 0) | ((((sizeof(struct kvm_vcpu_events)
))) << ((0 +8)+8))), &events);
1431 if (ret < 0) {
1432 return ret;
1433 }
1434 env->exception_injected =
1435 events.exception.injected ? events.exception.nr : -1;
1436 env->has_error_code = events.exception.has_error_code;
1437 env->error_code = events.exception.error_code;
1438
1439 env->interrupt_injected =
1440 events.interrupt.injected ? events.interrupt.nr : -1;
1441 env->soft_interrupt = events.interrupt.soft;
1442
1443 env->nmi_injected = events.nmi.injected;
1444 env->nmi_pending = events.nmi.pending;
1445 if (events.nmi.masked) {
1446 env->hflags2 |= HF2_NMI_MASK(1 << 2);
1447 } else {
1448 env->hflags2 &= ~HF2_NMI_MASK(1 << 2);
1449 }
1450
1451 env->sipi_vector = events.sipi_vector;
1452
1453 return 0;
1454}
1455
1456static int kvm_guest_debug_workarounds(CPUX86State *env)
1457{
1458 int ret = 0;
1459 unsigned long reinject_trap = 0;
1460
1461 if (!kvm_has_vcpu_events()) {
1462 if (env->exception_injected == 1) {
1463 reinject_trap = KVM_GUESTDBG_INJECT_DB0x00040000;
1464 } else if (env->exception_injected == 3) {
1465 reinject_trap = KVM_GUESTDBG_INJECT_BP0x00080000;
1466 }
1467 env->exception_injected = -1;
1468 }
1469
1470 /*
1471 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1472 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1473 * by updating the debug state once again if single-stepping is on.
1474 * Another reason to call kvm_update_guest_debug here is a pending debug
1475 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1476 * reinject them via SET_GUEST_DEBUG.
1477 */
1478 if (reinject_trap ||
1479 (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1480 ret = kvm_update_guest_debug(env, reinject_trap);
1481 }
1482 return ret;
1483}
1484
1485static int kvm_put_debugregs(CPUX86State *env)
1486{
1487 struct kvm_debugregs dbgregs;
1488 int i;
1489
1490 if (!kvm_has_debugregs()) {
1491 return 0;
1492 }
1493
1494 for (i = 0; i < 4; i++) {
1495 dbgregs.db[i] = env->dr[i];
1496 }
1497 dbgregs.dr6 = env->dr[6];
1498 dbgregs.dr7 = env->dr[7];
1499 dbgregs.flags = 0;
1500
1501 return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0xa2)) << 0) | ((((sizeof(struct kvm_debugregs)))
) << ((0 +8)+8))), &dbgregs);
1502}
1503
1504static int kvm_get_debugregs(CPUX86State *env)
1505{
1506 struct kvm_debugregs dbgregs;
1507 int i, ret;
1508
1509 if (!kvm_has_debugregs()) {
1510 return 0;
1511 }
1512
1513 ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS(((2U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0xa1)) << 0) | ((((sizeof(struct kvm_debugregs)))
) << ((0 +8)+8))), &dbgregs);
1514 if (ret < 0) {
1515 return ret;
1516 }
1517 for (i = 0; i < 4; i++) {
1518 env->dr[i] = dbgregs.db[i];
1519 }
1520 env->dr[4] = env->dr[6] = dbgregs.dr6;
1521 env->dr[5] = env->dr[7] = dbgregs.dr7;
1522
1523 return 0;
1524}
1525
1526int kvm_arch_put_registers(CPUX86State *env, int level)
1527{
1528 int ret;
1529
1530 assert(cpu_is_stopped(env) || qemu_cpu_is_self(env))((cpu_is_stopped(env) || qemu_cpu_is_self(env)) ? (void) (0) :
__assert_fail ("cpu_is_stopped(env) || qemu_cpu_is_self(env)"
, "/home/stefan/src/qemu/qemu.org/qemu/target-i386/kvm.c", 1530
, __PRETTY_FUNCTION__));
1531
1532 ret = kvm_getput_regs(env, 1);
1533 if (ret < 0) {
1534 return ret;
1535 }
1536 ret = kvm_put_xsave(env);
1537 if (ret < 0) {
1538 return ret;
1539 }
1540 ret = kvm_put_xcrs(env);
1541 if (ret < 0) {
1542 return ret;
1543 }
1544 ret = kvm_put_sregs(env);
1545 if (ret < 0) {
1546 return ret;
1547 }
1548 /* must be before kvm_put_msrs */
1549 ret = kvm_inject_mce_oldstyle(env);
1550 if (ret < 0) {
1551 return ret;
1552 }
1553 ret = kvm_put_msrs(env, level);
1554 if (ret < 0) {
1555 return ret;
1556 }
1557 if (level >= KVM_PUT_RESET_STATE2) {
1558 ret = kvm_put_mp_state(env);
1559 if (ret < 0) {
1560 return ret;
1561 }
1562 ret = kvm_put_apic(env);
1563 if (ret < 0) {
1564 return ret;
1565 }
1566 }
1567 ret = kvm_put_vcpu_events(env, level);
1568 if (ret < 0) {
1569 return ret;
1570 }
1571 ret = kvm_put_debugregs(env);
1572 if (ret < 0) {
1573 return ret;
1574 }
1575 /* must be last */
1576 ret = kvm_guest_debug_workarounds(env);
1577 if (ret < 0) {
1578 return ret;
1579 }
1580 return 0;
1581}
1582
1583int kvm_arch_get_registers(CPUX86State *env)
1584{
1585 int ret;
1586
1587 assert(cpu_is_stopped(env) || qemu_cpu_is_self(env))((cpu_is_stopped(env) || qemu_cpu_is_self(env)) ? (void) (0) :
__assert_fail ("cpu_is_stopped(env) || qemu_cpu_is_self(env)"
, "/home/stefan/src/qemu/qemu.org/qemu/target-i386/kvm.c", 1587
, __PRETTY_FUNCTION__));
1588
1589 ret = kvm_getput_regs(env, 0);
1590 if (ret < 0) {
1591 return ret;
1592 }
1593 ret = kvm_get_xsave(env);
1594 if (ret < 0) {
1595 return ret;
1596 }
1597 ret = kvm_get_xcrs(env);
1598 if (ret < 0) {
1599 return ret;
1600 }
1601 ret = kvm_get_sregs(env);
1602 if (ret < 0) {
1603 return ret;
1604 }
1605 ret = kvm_get_msrs(env);
1606 if (ret < 0) {
1607 return ret;
1608 }
1609 ret = kvm_get_mp_state(env);
1610 if (ret < 0) {
1611 return ret;
1612 }
1613 ret = kvm_get_apic(env);
1614 if (ret < 0) {
1615 return ret;
1616 }
1617 ret = kvm_get_vcpu_events(env);
1618 if (ret < 0) {
1619 return ret;
1620 }
1621 ret = kvm_get_debugregs(env);
1622 if (ret < 0) {
1623 return ret;
1624 }
1625 return 0;
1626}
1627
1628void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run)
1629{
1630 int ret;
1631
1632 /* Inject NMI */
1633 if (env->interrupt_request & CPU_INTERRUPT_NMI0x0200) {
1634 env->interrupt_request &= ~CPU_INTERRUPT_NMI0x0200;
1635 DPRINTF("injected NMI\n")do { } while (0);
1636 ret = kvm_vcpu_ioctl(env, KVM_NMI(((0U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x9a)) << 0) | ((0) << ((0 +8)+8))));
1637 if (ret < 0) {
1638 fprintf(stderrstderr, "KVM: injection failed, NMI lost (%s)\n",
1639 strerror(-ret));
1640 }
1641 }
1642
1643 if (!kvm_irqchip_in_kernel()(kvm_kernel_irqchip)) {
1644 /* Force the VCPU out of its inner loop to process any INIT requests
1645 * or pending TPR access reports. */
1646 if (env->interrupt_request &
1647 (CPU_INTERRUPT_INIT0x0400 | CPU_INTERRUPT_TPR0x2000)) {
1648 env->exit_request = 1;
1649 }
1650
1651 /* Try to inject an interrupt if the guest can accept it */
1652 if (run->ready_for_interrupt_injection &&
1653 (env->interrupt_request & CPU_INTERRUPT_HARD0x0002) &&
1654 (env->eflags & IF_MASK0x00000200)) {
1655 int irq;
1656
1657 env->interrupt_request &= ~CPU_INTERRUPT_HARD0x0002;
1658 irq = cpu_get_pic_interrupt(env);
1659 if (irq >= 0) {
1660 struct kvm_interrupt intr;
1661
1662 intr.irq = irq;
1663 DPRINTF("injected interrupt %d\n", irq)do { } while (0);
1664 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT(((1U) << (((0 +8)+8)+14)) | (((0xAE)) << (0 +8))
| (((0x86)) << 0) | ((((sizeof(struct kvm_interrupt)))
) << ((0 +8)+8))), &intr);
1665 if (ret < 0) {
1666 fprintf(stderrstderr,
1667 "KVM: injection failed, interrupt lost (%s)\n",
1668 strerror(-ret));
1669 }
1670 }
1671 }
1672
1673 /* If we have an interrupt but the guest is not ready to receive an
1674 * interrupt, request an interrupt window exit. This will
1675 * cause a return to userspace as soon as the guest is ready to
1676 * receive interrupts. */
1677 if ((env->interrupt_request & CPU_INTERRUPT_HARD0x0002)) {
1678 run->request_interrupt_window = 1;
1679 } else {
1680 run->request_interrupt_window = 0;
1681 }
1682
1683 DPRINTF("setting tpr\n")do { } while (0);
1684 run->cr8 = cpu_get_apic_tpr(env->apic_state);
1685 }
1686}
1687
1688void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run)
1689{
1690 if (run->if_flag) {
1691 env->eflags |= IF_MASK0x00000200;
1692 } else {
1693 env->eflags &= ~IF_MASK0x00000200;
1694 }
1695 cpu_set_apic_tpr(env->apic_state, run->cr8);
1696 cpu_set_apic_base(env->apic_state, run->apic_base);
1697}
1698
1699int kvm_arch_process_async_events(CPUX86State *env)
1700{
1701 X86CPU *cpu = x86_env_get_cpu(env);
1702
1703 if (env->interrupt_request & CPU_INTERRUPT_MCE0x1000) {
1704 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1705 assert(env->mcg_cap)((env->mcg_cap) ? (void) (0) : __assert_fail ("env->mcg_cap"
, "/home/stefan/src/qemu/qemu.org/qemu/target-i386/kvm.c", 1705
, __PRETTY_FUNCTION__));
1706
1707 env->interrupt_request &= ~CPU_INTERRUPT_MCE0x1000;
1708
1709 kvm_cpu_synchronize_state(env);
1710
1711 if (env->exception_injected == EXCP08_DBLE8) {
1712 /* this means triple fault */
1713 qemu_system_reset_request();
1714 env->exit_request = 1;
1715 return 0;
1716 }
1717 env->exception_injected = EXCP12_MCHK18;
1718 env->has_error_code = 0;
1719
1720 env->halted = 0;
1721 if (kvm_irqchip_in_kernel()(kvm_kernel_irqchip) && env->mp_state == KVM_MP_STATE_HALTED3) {
1722 env->mp_state = KVM_MP_STATE_RUNNABLE0;
1723 }
1724 }
1725
1726 if (kvm_irqchip_in_kernel()(kvm_kernel_irqchip)) {
1727 return 0;
1728 }
1729
1730 if (((env->interrupt_request & CPU_INTERRUPT_HARD0x0002) &&
1731 (env->eflags & IF_MASK0x00000200)) ||
1732 (env->interrupt_request & CPU_INTERRUPT_NMI0x0200)) {
1733 env->halted = 0;
1734 }
1735 if (env->interrupt_request & CPU_INTERRUPT_INIT0x0400) {
1736 kvm_cpu_synchronize_state(env);
1737 do_cpu_init(cpu);
1738 }
1739 if (env->interrupt_request & CPU_INTERRUPT_SIPI0x0800) {
1740 kvm_cpu_synchronize_state(env);
1741 do_cpu_sipi(cpu);
1742 }
1743 if (env->interrupt_request & CPU_INTERRUPT_TPR0x2000) {
1744 env->interrupt_request &= ~CPU_INTERRUPT_TPR0x2000;
1745 kvm_cpu_synchronize_state(env);
1746 apic_handle_tpr_access_report(env->apic_state, env->eip,
1747 env->tpr_access_type);
1748 }
1749
1750 return env->halted;
1751}
1752
1753static int kvm_handle_halt(CPUX86State *env)
1754{
1755 if (!((env->interrupt_request & CPU_INTERRUPT_HARD0x0002) &&
1756 (env->eflags & IF_MASK0x00000200)) &&
1757 !(env->interrupt_request & CPU_INTERRUPT_NMI0x0200)) {
1758 env->halted = 1;
1759 return EXCP_HLT0x10001;
1760 }
1761
1762 return 0;
1763}
1764
1765static int kvm_handle_tpr_access(CPUX86State *env)
1766{
1767 struct kvm_run *run = env->kvm_run;
1768
1769 apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1770 run->tpr_access.is_write ? TPR_ACCESS_WRITE
1771 : TPR_ACCESS_READ);
1772 return 1;
1773}
1774
1775int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1776{
1777 static const uint8_t int3 = 0xcc;
1778
1779 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1780 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1781 return -EINVAL22;
1782 }
1783 return 0;
1784}
1785
1786int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1787{
1788 uint8_t int3;
1789
1790 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1791 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1792 return -EINVAL22;
1793 }
1794 return 0;
1795}
1796
1797static struct {
1798 target_ulong addr;
1799 int len;
1800 int type;
1801} hw_breakpoint[4];
1802
1803static int nb_hw_breakpoint;
1804
1805static int find_hw_breakpoint(target_ulong addr, int len, int type)
1806{
1807 int n;
1808
1809 for (n = 0; n < nb_hw_breakpoint; n++) {
1810 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1811 (hw_breakpoint[n].len == len || len == -1)) {
1812 return n;
1813 }
1814 }
1815 return -1;
1816}
1817
1818int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1819 target_ulong len, int type)
1820{
1821 switch (type) {
1822 case GDB_BREAKPOINT_HW1:
1823 len = 1;
1824 break;
1825 case GDB_WATCHPOINT_WRITE2:
1826 case GDB_WATCHPOINT_ACCESS4:
1827 switch (len) {
1828 case 1:
1829 break;
1830 case 2:
1831 case 4:
1832 case 8:
1833 if (addr & (len - 1)) {
1834 return -EINVAL22;
1835 }
1836 break;
1837 default:
1838 return -EINVAL22;
1839 }
1840 break;
1841 default:
1842 return -ENOSYS38;
1843 }
1844
1845 if (nb_hw_breakpoint == 4) {
1846 return -ENOBUFS105;
1847 }
1848 if (find_hw_breakpoint(addr, len, type) >= 0) {
1849 return -EEXIST17;
1850 }
1851 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1852 hw_breakpoint[nb_hw_breakpoint].len = len;
1853 hw_breakpoint[nb_hw_breakpoint].type = type;
1854 nb_hw_breakpoint++;
1855
1856 return 0;
1857}
1858
1859int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1860 target_ulong len, int type)
1861{
1862 int n;
1863
1864 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW1) ? 1 : len, type);
1865 if (n < 0) {
1866 return -ENOENT2;
1867 }
1868 nb_hw_breakpoint--;
1869 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1870
1871 return 0;
1872}
1873
1874void kvm_arch_remove_all_hw_breakpoints(void)
1875{
1876 nb_hw_breakpoint = 0;
1877}
1878
1879static CPUWatchpoint hw_watchpoint;
1880
1881static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1882{
1883 int ret = 0;
1884 int n;
1885
1886 if (arch_info->exception == 1) {
1887 if (arch_info->dr6 & (1 << 14)) {
1888 if (cpu_single_envtls__cpu_single_env->singlestep_enabled) {
1889 ret = EXCP_DEBUG0x10002;
1890 }
1891 } else {
1892 for (n = 0; n < 4; n++) {
1893 if (arch_info->dr6 & (1 << n)) {
1894 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1895 case 0x0:
1896 ret = EXCP_DEBUG0x10002;
1897 break;
1898 case 0x1:
1899 ret = EXCP_DEBUG0x10002;
1900 cpu_single_envtls__cpu_single_env->watchpoint_hit = &hw_watchpoint;
1901 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1902 hw_watchpoint.flags = BP_MEM_WRITE0x02;
1903 break;
1904 case 0x3:
1905 ret = EXCP_DEBUG0x10002;
1906 cpu_single_envtls__cpu_single_env->watchpoint_hit = &hw_watchpoint;
1907 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1908 hw_watchpoint.flags = BP_MEM_ACCESS(0x01 | 0x02);
1909 break;
1910 }
1911 }
1912 }
1913 }
1914 } else if (kvm_find_sw_breakpoint(cpu_single_envtls__cpu_single_env, arch_info->pc)) {
1915 ret = EXCP_DEBUG0x10002;
1916 }
1917 if (ret == 0) {
1918 cpu_synchronize_state(cpu_single_envtls__cpu_single_env);
1919 assert(cpu_single_env->exception_injected == -1)((tls__cpu_single_env->exception_injected == -1) ? (void) (
0) : __assert_fail ("tls__cpu_single_env->exception_injected == -1"
, "/home/stefan/src/qemu/qemu.org/qemu/target-i386/kvm.c", 1919
, __PRETTY_FUNCTION__));
1920
1921 /* pass to guest */
1922 cpu_single_envtls__cpu_single_env->exception_injected = arch_info->exception;
1923 cpu_single_envtls__cpu_single_env->has_error_code = 0;
1924 }
1925
1926 return ret;
1927}
1928
1929void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debug *dbg)
1930{
1931 const uint8_t type_code[] = {
1932 [GDB_BREAKPOINT_HW1] = 0x0,
1933 [GDB_WATCHPOINT_WRITE2] = 0x1,
1934 [GDB_WATCHPOINT_ACCESS4] = 0x3
1935 };
1936 const uint8_t len_code[] = {
1937 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1938 };
1939 int n;
1940
1941 if (kvm_sw_breakpoints_active(env)) {
1942 dbg->control |= KVM_GUESTDBG_ENABLE0x00000001 | KVM_GUESTDBG_USE_SW_BP0x00010000;
1943 }
1944 if (nb_hw_breakpoint > 0) {
1945 dbg->control |= KVM_GUESTDBG_ENABLE0x00000001 | KVM_GUESTDBG_USE_HW_BP0x00020000;
1946 dbg->arch.debugreg[7] = 0x0600;
1947 for (n = 0; n < nb_hw_breakpoint; n++) {
1948 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1949 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1950 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1951 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1952 }
1953 }
1954}
1955
1956static bool_Bool host_supports_vmx(void)
1957{
1958 uint32_t ecx, unused;
1959
1960 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1961 return ecx & CPUID_EXT_VMX(1 << 5);
1962}
1963
1964#define VMX_INVALID_GUEST_STATE0x80000021 0x80000021
1965
1966int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run)
1967{
1968 uint64_t code;
1969 int ret;
1970
1971 switch (run->exit_reason) {
1972 case KVM_EXIT_HLT5:
1973 DPRINTF("handle_hlt\n")do { } while (0);
1974 ret = kvm_handle_halt(env);
1975 break;
1976 case KVM_EXIT_SET_TPR11:
1977 ret = 0;
1978 break;
1979 case KVM_EXIT_TPR_ACCESS12:
1980 ret = kvm_handle_tpr_access(env);
1981 break;
1982 case KVM_EXIT_FAIL_ENTRY9:
1983 code = run->fail_entry.hardware_entry_failure_reason;
1984 fprintf(stderrstderr, "KVM: entry failed, hardware error 0x%" PRIx64"l" "x" "\n",
1985 code);
1986 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE0x80000021) {
1987 fprintf(stderrstderr,
1988 "\nIf you're running a guest on an Intel machine without "
1989 "unrestricted mode\n"
1990 "support, the failure can be most likely due to the guest "
1991 "entering an invalid\n"
1992 "state for Intel VT. For example, the guest maybe running "
1993 "in big real mode\n"
1994 "which is not supported on less recent Intel processors."
1995 "\n\n");
1996 }
1997 ret = -1;
1998 break;
1999 case KVM_EXIT_EXCEPTION1:
2000 fprintf(stderrstderr, "KVM: exception %d exit (error code 0x%x)\n",
2001 run->ex.exception, run->ex.error_code);
2002 ret = -1;
2003 break;
2004 case KVM_EXIT_DEBUG4:
2005 DPRINTF("kvm_exit_debug\n")do { } while (0);
2006 ret = kvm_handle_debug(&run->debug.arch);
2007 break;
2008 default:
2009 fprintf(stderrstderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2010 ret = -1;
2011 break;
2012 }
2013
2014 return ret;
2015}
2016
2017bool_Bool kvm_arch_stop_on_emulation_error(CPUX86State *env)
2018{
2019 kvm_cpu_synchronize_state(env);
2020 return !(env->cr[0] & CR0_PE_MASK(1 << 0)) ||
2021 ((env->segs[R_CS1].selector & 3) != 3);
2022}
2023
2024void kvm_arch_init_irq_routing(KVMState *s)
2025{
2026 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING25)) {
2027 /* If kernel can't do irq routing, interrupt source
2028 * override 0->2 cannot be set up as required by HPET.
2029 * So we have to disable it.
2030 */
2031 no_hpet = 1;
2032 }
2033}