Bug Summary

File:hw/display/qxl.c
Location:line 1476, column 14
Description:Value stored to 'orig_io_port' during its initialization is never read

Annotated Source Code

1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <zlib.h>
22
23#include "qemu-common.h"
24#include "qemu/timer.h"
25#include "qemu/queue.h"
26#include "qemu/atomic.h"
27#include "monitor/monitor.h"
28#include "sysemu/sysemu.h"
29#include "trace.h"
30
31#include "qxl.h"
32
33/*
34 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
35 * such can be changed by the guest, so to avoid a guest trigerrable
36 * abort we just qxl_set_guest_bug and set the return to NULL. Still
37 * it may happen as a result of emulator bug as well.
38 */
39#undef SPICE_RING_PROD_ITEM
40#define SPICE_RING_PROD_ITEM(qxl, r, ret){ uint32_t prod = (r)->prod & ((r)->num_items - 1);
if (prod >= (sizeof((r)->items) / sizeof(((r)->items
)[0]))) { qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch "
"%u >= %zu", prod, (sizeof((r)->items) / sizeof(((r)->
items)[0]))); ret = ((void*)0); } else { ret = &(r)->items
[prod].el; } } { \
41 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r)((r)->num_items - 1); \
42 if (prod >= ARRAY_SIZE((r)->items)(sizeof((r)->items) / sizeof(((r)->items)[0]))) { \
43 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
44 "%u >= %zu", prod, ARRAY_SIZE((r)->items)(sizeof((r)->items) / sizeof(((r)->items)[0]))); \
45 ret = NULL((void*)0); \
46 } else { \
47 ret = &(r)->items[prod].el; \
48 } \
49 }
50
51#undef SPICE_RING_CONS_ITEM
52#define SPICE_RING_CONS_ITEM(qxl, r, ret){ uint32_t cons = (r)->cons & ((r)->num_items - 1);
if (cons >= (sizeof((r)->items) / sizeof(((r)->items
)[0]))) { qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch "
"%u >= %zu", cons, (sizeof((r)->items) / sizeof(((r)->
items)[0]))); ret = ((void*)0); } else { ret = &(r)->items
[cons].el; } } { \
53 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r)((r)->num_items - 1); \
54 if (cons >= ARRAY_SIZE((r)->items)(sizeof((r)->items) / sizeof(((r)->items)[0]))) { \
55 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
56 "%u >= %zu", cons, ARRAY_SIZE((r)->items)(sizeof((r)->items) / sizeof(((r)->items)[0]))); \
57 ret = NULL((void*)0); \
58 } else { \
59 ret = &(r)->items[cons].el; \
60 } \
61 }
62
63#undef ALIGN
64#define ALIGN(a, b)(((a) + ((b) - 1)) & ~((b) - 1)) (((a) + ((b) - 1)) & ~((b) - 1))
65
66#define PIXEL_SIZE0.2936875 0.2936875 //1280x1024 is 14.8" x 11.9"
67
68#define QXL_MODE(_x, _y, _b, _o){ .x_res = _x, .y_res = _y, .bits = _b, .stride = (_x) * (_b)
/ 8, .x_mili = 0.2936875 * (_x), .y_mili = 0.2936875 * (_y),
.orientation = _o, } \
69 { .x_res = _x, \
70 .y_res = _y, \
71 .bits = _b, \
72 .stride = (_x) * (_b) / 8, \
73 .x_mili = PIXEL_SIZE0.2936875 * (_x), \
74 .y_mili = PIXEL_SIZE0.2936875 * (_y), \
75 .orientation = _o, \
76 }
77
78#define QXL_MODE_16_32(x_res, y_res, orientation){ .x_res = x_res, .y_res = y_res, .bits = 16, .stride = (x_res
) * (16) / 8, .x_mili = 0.2936875 * (x_res), .y_mili = 0.2936875
* (y_res), .orientation = orientation, }, { .x_res = x_res, .
y_res = y_res, .bits = 32, .stride = (x_res) * (32) / 8, .x_mili
= 0.2936875 * (x_res), .y_mili = 0.2936875 * (y_res), .orientation
= orientation, } \
79 QXL_MODE(x_res, y_res, 16, orientation){ .x_res = x_res, .y_res = y_res, .bits = 16, .stride = (x_res
) * (16) / 8, .x_mili = 0.2936875 * (x_res), .y_mili = 0.2936875
* (y_res), .orientation = orientation, }, \
80 QXL_MODE(x_res, y_res, 32, orientation){ .x_res = x_res, .y_res = y_res, .bits = 32, .stride = (x_res
) * (32) / 8, .x_mili = 0.2936875 * (x_res), .y_mili = 0.2936875
* (y_res), .orientation = orientation, }
81
82#define QXL_MODE_EX(x_res, y_res){ .x_res = x_res, .y_res = y_res, .bits = 16, .stride = (x_res
) * (16) / 8, .x_mili = 0.2936875 * (x_res), .y_mili = 0.2936875
* (y_res), .orientation = 0, }, { .x_res = x_res, .y_res = y_res
, .bits = 32, .stride = (x_res) * (32) / 8, .x_mili = 0.2936875
* (x_res), .y_mili = 0.2936875 * (y_res), .orientation = 0, }
, { .x_res = x_res, .y_res = y_res, .bits = 16, .stride = (x_res
) * (16) / 8, .x_mili = 0.2936875 * (x_res), .y_mili = 0.2936875
* (y_res), .orientation = 1, }, { .x_res = x_res, .y_res = y_res
, .bits = 32, .stride = (x_res) * (32) / 8, .x_mili = 0.2936875
* (x_res), .y_mili = 0.2936875 * (y_res), .orientation = 1, } \
83 QXL_MODE_16_32(x_res, y_res, 0){ .x_res = x_res, .y_res = y_res, .bits = 16, .stride = (x_res
) * (16) / 8, .x_mili = 0.2936875 * (x_res), .y_mili = 0.2936875
* (y_res), .orientation = 0, }, { .x_res = x_res, .y_res = y_res
, .bits = 32, .stride = (x_res) * (32) / 8, .x_mili = 0.2936875
* (x_res), .y_mili = 0.2936875 * (y_res), .orientation = 0, }, \
84 QXL_MODE_16_32(x_res, y_res, 1){ .x_res = x_res, .y_res = y_res, .bits = 16, .stride = (x_res
) * (16) / 8, .x_mili = 0.2936875 * (x_res), .y_mili = 0.2936875
* (y_res), .orientation = 1, }, { .x_res = x_res, .y_res = y_res
, .bits = 32, .stride = (x_res) * (32) / 8, .x_mili = 0.2936875
* (x_res), .y_mili = 0.2936875 * (y_res), .orientation = 1, }
85
86static QXLMode qxl_modes[] = {
87 QXL_MODE_EX(640, 480){ .x_res = 640, .y_res = 480, .bits = 16, .stride = (640) * (
16) / 8, .x_mili = 0.2936875 * (640), .y_mili = 0.2936875 * (
480), .orientation = 0, }, { .x_res = 640, .y_res = 480, .bits
= 32, .stride = (640) * (32) / 8, .x_mili = 0.2936875 * (640
), .y_mili = 0.2936875 * (480), .orientation = 0, }, { .x_res
= 640, .y_res = 480, .bits = 16, .stride = (640) * (16) / 8,
.x_mili = 0.2936875 * (640), .y_mili = 0.2936875 * (480), .orientation
= 1, }, { .x_res = 640, .y_res = 480, .bits = 32, .stride = (
640) * (32) / 8, .x_mili = 0.2936875 * (640), .y_mili = 0.2936875
* (480), .orientation = 1, },
88 QXL_MODE_EX(800, 480){ .x_res = 800, .y_res = 480, .bits = 16, .stride = (800) * (
16) / 8, .x_mili = 0.2936875 * (800), .y_mili = 0.2936875 * (
480), .orientation = 0, }, { .x_res = 800, .y_res = 480, .bits
= 32, .stride = (800) * (32) / 8, .x_mili = 0.2936875 * (800
), .y_mili = 0.2936875 * (480), .orientation = 0, }, { .x_res
= 800, .y_res = 480, .bits = 16, .stride = (800) * (16) / 8,
.x_mili = 0.2936875 * (800), .y_mili = 0.2936875 * (480), .orientation
= 1, }, { .x_res = 800, .y_res = 480, .bits = 32, .stride = (
800) * (32) / 8, .x_mili = 0.2936875 * (800), .y_mili = 0.2936875
* (480), .orientation = 1, },
89 QXL_MODE_EX(800, 600){ .x_res = 800, .y_res = 600, .bits = 16, .stride = (800) * (
16) / 8, .x_mili = 0.2936875 * (800), .y_mili = 0.2936875 * (
600), .orientation = 0, }, { .x_res = 800, .y_res = 600, .bits
= 32, .stride = (800) * (32) / 8, .x_mili = 0.2936875 * (800
), .y_mili = 0.2936875 * (600), .orientation = 0, }, { .x_res
= 800, .y_res = 600, .bits = 16, .stride = (800) * (16) / 8,
.x_mili = 0.2936875 * (800), .y_mili = 0.2936875 * (600), .orientation
= 1, }, { .x_res = 800, .y_res = 600, .bits = 32, .stride = (
800) * (32) / 8, .x_mili = 0.2936875 * (800), .y_mili = 0.2936875
* (600), .orientation = 1, },
90 QXL_MODE_EX(832, 624){ .x_res = 832, .y_res = 624, .bits = 16, .stride = (832) * (
16) / 8, .x_mili = 0.2936875 * (832), .y_mili = 0.2936875 * (
624), .orientation = 0, }, { .x_res = 832, .y_res = 624, .bits
= 32, .stride = (832) * (32) / 8, .x_mili = 0.2936875 * (832
), .y_mili = 0.2936875 * (624), .orientation = 0, }, { .x_res
= 832, .y_res = 624, .bits = 16, .stride = (832) * (16) / 8,
.x_mili = 0.2936875 * (832), .y_mili = 0.2936875 * (624), .orientation
= 1, }, { .x_res = 832, .y_res = 624, .bits = 32, .stride = (
832) * (32) / 8, .x_mili = 0.2936875 * (832), .y_mili = 0.2936875
* (624), .orientation = 1, },
91 QXL_MODE_EX(960, 640){ .x_res = 960, .y_res = 640, .bits = 16, .stride = (960) * (
16) / 8, .x_mili = 0.2936875 * (960), .y_mili = 0.2936875 * (
640), .orientation = 0, }, { .x_res = 960, .y_res = 640, .bits
= 32, .stride = (960) * (32) / 8, .x_mili = 0.2936875 * (960
), .y_mili = 0.2936875 * (640), .orientation = 0, }, { .x_res
= 960, .y_res = 640, .bits = 16, .stride = (960) * (16) / 8,
.x_mili = 0.2936875 * (960), .y_mili = 0.2936875 * (640), .orientation
= 1, }, { .x_res = 960, .y_res = 640, .bits = 32, .stride = (
960) * (32) / 8, .x_mili = 0.2936875 * (960), .y_mili = 0.2936875
* (640), .orientation = 1, },
92 QXL_MODE_EX(1024, 600){ .x_res = 1024, .y_res = 600, .bits = 16, .stride = (1024) *
(16) / 8, .x_mili = 0.2936875 * (1024), .y_mili = 0.2936875 *
(600), .orientation = 0, }, { .x_res = 1024, .y_res = 600, .
bits = 32, .stride = (1024) * (32) / 8, .x_mili = 0.2936875 *
(1024), .y_mili = 0.2936875 * (600), .orientation = 0, }, { .
x_res = 1024, .y_res = 600, .bits = 16, .stride = (1024) * (16
) / 8, .x_mili = 0.2936875 * (1024), .y_mili = 0.2936875 * (600
), .orientation = 1, }, { .x_res = 1024, .y_res = 600, .bits =
32, .stride = (1024) * (32) / 8, .x_mili = 0.2936875 * (1024
), .y_mili = 0.2936875 * (600), .orientation = 1, },
93 QXL_MODE_EX(1024, 768){ .x_res = 1024, .y_res = 768, .bits = 16, .stride = (1024) *
(16) / 8, .x_mili = 0.2936875 * (1024), .y_mili = 0.2936875 *
(768), .orientation = 0, }, { .x_res = 1024, .y_res = 768, .
bits = 32, .stride = (1024) * (32) / 8, .x_mili = 0.2936875 *
(1024), .y_mili = 0.2936875 * (768), .orientation = 0, }, { .
x_res = 1024, .y_res = 768, .bits = 16, .stride = (1024) * (16
) / 8, .x_mili = 0.2936875 * (1024), .y_mili = 0.2936875 * (768
), .orientation = 1, }, { .x_res = 1024, .y_res = 768, .bits =
32, .stride = (1024) * (32) / 8, .x_mili = 0.2936875 * (1024
), .y_mili = 0.2936875 * (768), .orientation = 1, },
94 QXL_MODE_EX(1152, 864){ .x_res = 1152, .y_res = 864, .bits = 16, .stride = (1152) *
(16) / 8, .x_mili = 0.2936875 * (1152), .y_mili = 0.2936875 *
(864), .orientation = 0, }, { .x_res = 1152, .y_res = 864, .
bits = 32, .stride = (1152) * (32) / 8, .x_mili = 0.2936875 *
(1152), .y_mili = 0.2936875 * (864), .orientation = 0, }, { .
x_res = 1152, .y_res = 864, .bits = 16, .stride = (1152) * (16
) / 8, .x_mili = 0.2936875 * (1152), .y_mili = 0.2936875 * (864
), .orientation = 1, }, { .x_res = 1152, .y_res = 864, .bits =
32, .stride = (1152) * (32) / 8, .x_mili = 0.2936875 * (1152
), .y_mili = 0.2936875 * (864), .orientation = 1, },
95 QXL_MODE_EX(1152, 870){ .x_res = 1152, .y_res = 870, .bits = 16, .stride = (1152) *
(16) / 8, .x_mili = 0.2936875 * (1152), .y_mili = 0.2936875 *
(870), .orientation = 0, }, { .x_res = 1152, .y_res = 870, .
bits = 32, .stride = (1152) * (32) / 8, .x_mili = 0.2936875 *
(1152), .y_mili = 0.2936875 * (870), .orientation = 0, }, { .
x_res = 1152, .y_res = 870, .bits = 16, .stride = (1152) * (16
) / 8, .x_mili = 0.2936875 * (1152), .y_mili = 0.2936875 * (870
), .orientation = 1, }, { .x_res = 1152, .y_res = 870, .bits =
32, .stride = (1152) * (32) / 8, .x_mili = 0.2936875 * (1152
), .y_mili = 0.2936875 * (870), .orientation = 1, },
96 QXL_MODE_EX(1280, 720){ .x_res = 1280, .y_res = 720, .bits = 16, .stride = (1280) *
(16) / 8, .x_mili = 0.2936875 * (1280), .y_mili = 0.2936875 *
(720), .orientation = 0, }, { .x_res = 1280, .y_res = 720, .
bits = 32, .stride = (1280) * (32) / 8, .x_mili = 0.2936875 *
(1280), .y_mili = 0.2936875 * (720), .orientation = 0, }, { .
x_res = 1280, .y_res = 720, .bits = 16, .stride = (1280) * (16
) / 8, .x_mili = 0.2936875 * (1280), .y_mili = 0.2936875 * (720
), .orientation = 1, }, { .x_res = 1280, .y_res = 720, .bits =
32, .stride = (1280) * (32) / 8, .x_mili = 0.2936875 * (1280
), .y_mili = 0.2936875 * (720), .orientation = 1, },
97 QXL_MODE_EX(1280, 760){ .x_res = 1280, .y_res = 760, .bits = 16, .stride = (1280) *
(16) / 8, .x_mili = 0.2936875 * (1280), .y_mili = 0.2936875 *
(760), .orientation = 0, }, { .x_res = 1280, .y_res = 760, .
bits = 32, .stride = (1280) * (32) / 8, .x_mili = 0.2936875 *
(1280), .y_mili = 0.2936875 * (760), .orientation = 0, }, { .
x_res = 1280, .y_res = 760, .bits = 16, .stride = (1280) * (16
) / 8, .x_mili = 0.2936875 * (1280), .y_mili = 0.2936875 * (760
), .orientation = 1, }, { .x_res = 1280, .y_res = 760, .bits =
32, .stride = (1280) * (32) / 8, .x_mili = 0.2936875 * (1280
), .y_mili = 0.2936875 * (760), .orientation = 1, },
98 QXL_MODE_EX(1280, 768){ .x_res = 1280, .y_res = 768, .bits = 16, .stride = (1280) *
(16) / 8, .x_mili = 0.2936875 * (1280), .y_mili = 0.2936875 *
(768), .orientation = 0, }, { .x_res = 1280, .y_res = 768, .
bits = 32, .stride = (1280) * (32) / 8, .x_mili = 0.2936875 *
(1280), .y_mili = 0.2936875 * (768), .orientation = 0, }, { .
x_res = 1280, .y_res = 768, .bits = 16, .stride = (1280) * (16
) / 8, .x_mili = 0.2936875 * (1280), .y_mili = 0.2936875 * (768
), .orientation = 1, }, { .x_res = 1280, .y_res = 768, .bits =
32, .stride = (1280) * (32) / 8, .x_mili = 0.2936875 * (1280
), .y_mili = 0.2936875 * (768), .orientation = 1, },
99 QXL_MODE_EX(1280, 800){ .x_res = 1280, .y_res = 800, .bits = 16, .stride = (1280) *
(16) / 8, .x_mili = 0.2936875 * (1280), .y_mili = 0.2936875 *
(800), .orientation = 0, }, { .x_res = 1280, .y_res = 800, .
bits = 32, .stride = (1280) * (32) / 8, .x_mili = 0.2936875 *
(1280), .y_mili = 0.2936875 * (800), .orientation = 0, }, { .
x_res = 1280, .y_res = 800, .bits = 16, .stride = (1280) * (16
) / 8, .x_mili = 0.2936875 * (1280), .y_mili = 0.2936875 * (800
), .orientation = 1, }, { .x_res = 1280, .y_res = 800, .bits =
32, .stride = (1280) * (32) / 8, .x_mili = 0.2936875 * (1280
), .y_mili = 0.2936875 * (800), .orientation = 1, },
100 QXL_MODE_EX(1280, 960){ .x_res = 1280, .y_res = 960, .bits = 16, .stride = (1280) *
(16) / 8, .x_mili = 0.2936875 * (1280), .y_mili = 0.2936875 *
(960), .orientation = 0, }, { .x_res = 1280, .y_res = 960, .
bits = 32, .stride = (1280) * (32) / 8, .x_mili = 0.2936875 *
(1280), .y_mili = 0.2936875 * (960), .orientation = 0, }, { .
x_res = 1280, .y_res = 960, .bits = 16, .stride = (1280) * (16
) / 8, .x_mili = 0.2936875 * (1280), .y_mili = 0.2936875 * (960
), .orientation = 1, }, { .x_res = 1280, .y_res = 960, .bits =
32, .stride = (1280) * (32) / 8, .x_mili = 0.2936875 * (1280
), .y_mili = 0.2936875 * (960), .orientation = 1, },
101 QXL_MODE_EX(1280, 1024){ .x_res = 1280, .y_res = 1024, .bits = 16, .stride = (1280) *
(16) / 8, .x_mili = 0.2936875 * (1280), .y_mili = 0.2936875 *
(1024), .orientation = 0, }, { .x_res = 1280, .y_res = 1024,
.bits = 32, .stride = (1280) * (32) / 8, .x_mili = 0.2936875
* (1280), .y_mili = 0.2936875 * (1024), .orientation = 0, },
{ .x_res = 1280, .y_res = 1024, .bits = 16, .stride = (1280)
* (16) / 8, .x_mili = 0.2936875 * (1280), .y_mili = 0.2936875
* (1024), .orientation = 1, }, { .x_res = 1280, .y_res = 1024
, .bits = 32, .stride = (1280) * (32) / 8, .x_mili = 0.2936875
* (1280), .y_mili = 0.2936875 * (1024), .orientation = 1, },
102 QXL_MODE_EX(1360, 768){ .x_res = 1360, .y_res = 768, .bits = 16, .stride = (1360) *
(16) / 8, .x_mili = 0.2936875 * (1360), .y_mili = 0.2936875 *
(768), .orientation = 0, }, { .x_res = 1360, .y_res = 768, .
bits = 32, .stride = (1360) * (32) / 8, .x_mili = 0.2936875 *
(1360), .y_mili = 0.2936875 * (768), .orientation = 0, }, { .
x_res = 1360, .y_res = 768, .bits = 16, .stride = (1360) * (16
) / 8, .x_mili = 0.2936875 * (1360), .y_mili = 0.2936875 * (768
), .orientation = 1, }, { .x_res = 1360, .y_res = 768, .bits =
32, .stride = (1360) * (32) / 8, .x_mili = 0.2936875 * (1360
), .y_mili = 0.2936875 * (768), .orientation = 1, },
103 QXL_MODE_EX(1366, 768){ .x_res = 1366, .y_res = 768, .bits = 16, .stride = (1366) *
(16) / 8, .x_mili = 0.2936875 * (1366), .y_mili = 0.2936875 *
(768), .orientation = 0, }, { .x_res = 1366, .y_res = 768, .
bits = 32, .stride = (1366) * (32) / 8, .x_mili = 0.2936875 *
(1366), .y_mili = 0.2936875 * (768), .orientation = 0, }, { .
x_res = 1366, .y_res = 768, .bits = 16, .stride = (1366) * (16
) / 8, .x_mili = 0.2936875 * (1366), .y_mili = 0.2936875 * (768
), .orientation = 1, }, { .x_res = 1366, .y_res = 768, .bits =
32, .stride = (1366) * (32) / 8, .x_mili = 0.2936875 * (1366
), .y_mili = 0.2936875 * (768), .orientation = 1, },
104 QXL_MODE_EX(1400, 1050){ .x_res = 1400, .y_res = 1050, .bits = 16, .stride = (1400) *
(16) / 8, .x_mili = 0.2936875 * (1400), .y_mili = 0.2936875 *
(1050), .orientation = 0, }, { .x_res = 1400, .y_res = 1050,
.bits = 32, .stride = (1400) * (32) / 8, .x_mili = 0.2936875
* (1400), .y_mili = 0.2936875 * (1050), .orientation = 0, },
{ .x_res = 1400, .y_res = 1050, .bits = 16, .stride = (1400)
* (16) / 8, .x_mili = 0.2936875 * (1400), .y_mili = 0.2936875
* (1050), .orientation = 1, }, { .x_res = 1400, .y_res = 1050
, .bits = 32, .stride = (1400) * (32) / 8, .x_mili = 0.2936875
* (1400), .y_mili = 0.2936875 * (1050), .orientation = 1, },
105 QXL_MODE_EX(1440, 900){ .x_res = 1440, .y_res = 900, .bits = 16, .stride = (1440) *
(16) / 8, .x_mili = 0.2936875 * (1440), .y_mili = 0.2936875 *
(900), .orientation = 0, }, { .x_res = 1440, .y_res = 900, .
bits = 32, .stride = (1440) * (32) / 8, .x_mili = 0.2936875 *
(1440), .y_mili = 0.2936875 * (900), .orientation = 0, }, { .
x_res = 1440, .y_res = 900, .bits = 16, .stride = (1440) * (16
) / 8, .x_mili = 0.2936875 * (1440), .y_mili = 0.2936875 * (900
), .orientation = 1, }, { .x_res = 1440, .y_res = 900, .bits =
32, .stride = (1440) * (32) / 8, .x_mili = 0.2936875 * (1440
), .y_mili = 0.2936875 * (900), .orientation = 1, },
106 QXL_MODE_EX(1600, 900){ .x_res = 1600, .y_res = 900, .bits = 16, .stride = (1600) *
(16) / 8, .x_mili = 0.2936875 * (1600), .y_mili = 0.2936875 *
(900), .orientation = 0, }, { .x_res = 1600, .y_res = 900, .
bits = 32, .stride = (1600) * (32) / 8, .x_mili = 0.2936875 *
(1600), .y_mili = 0.2936875 * (900), .orientation = 0, }, { .
x_res = 1600, .y_res = 900, .bits = 16, .stride = (1600) * (16
) / 8, .x_mili = 0.2936875 * (1600), .y_mili = 0.2936875 * (900
), .orientation = 1, }, { .x_res = 1600, .y_res = 900, .bits =
32, .stride = (1600) * (32) / 8, .x_mili = 0.2936875 * (1600
), .y_mili = 0.2936875 * (900), .orientation = 1, },
107 QXL_MODE_EX(1600, 1200){ .x_res = 1600, .y_res = 1200, .bits = 16, .stride = (1600) *
(16) / 8, .x_mili = 0.2936875 * (1600), .y_mili = 0.2936875 *
(1200), .orientation = 0, }, { .x_res = 1600, .y_res = 1200,
.bits = 32, .stride = (1600) * (32) / 8, .x_mili = 0.2936875
* (1600), .y_mili = 0.2936875 * (1200), .orientation = 0, },
{ .x_res = 1600, .y_res = 1200, .bits = 16, .stride = (1600)
* (16) / 8, .x_mili = 0.2936875 * (1600), .y_mili = 0.2936875
* (1200), .orientation = 1, }, { .x_res = 1600, .y_res = 1200
, .bits = 32, .stride = (1600) * (32) / 8, .x_mili = 0.2936875
* (1600), .y_mili = 0.2936875 * (1200), .orientation = 1, },
108 QXL_MODE_EX(1680, 1050){ .x_res = 1680, .y_res = 1050, .bits = 16, .stride = (1680) *
(16) / 8, .x_mili = 0.2936875 * (1680), .y_mili = 0.2936875 *
(1050), .orientation = 0, }, { .x_res = 1680, .y_res = 1050,
.bits = 32, .stride = (1680) * (32) / 8, .x_mili = 0.2936875
* (1680), .y_mili = 0.2936875 * (1050), .orientation = 0, },
{ .x_res = 1680, .y_res = 1050, .bits = 16, .stride = (1680)
* (16) / 8, .x_mili = 0.2936875 * (1680), .y_mili = 0.2936875
* (1050), .orientation = 1, }, { .x_res = 1680, .y_res = 1050
, .bits = 32, .stride = (1680) * (32) / 8, .x_mili = 0.2936875
* (1680), .y_mili = 0.2936875 * (1050), .orientation = 1, },
109 QXL_MODE_EX(1920, 1080){ .x_res = 1920, .y_res = 1080, .bits = 16, .stride = (1920) *
(16) / 8, .x_mili = 0.2936875 * (1920), .y_mili = 0.2936875 *
(1080), .orientation = 0, }, { .x_res = 1920, .y_res = 1080,
.bits = 32, .stride = (1920) * (32) / 8, .x_mili = 0.2936875
* (1920), .y_mili = 0.2936875 * (1080), .orientation = 0, },
{ .x_res = 1920, .y_res = 1080, .bits = 16, .stride = (1920)
* (16) / 8, .x_mili = 0.2936875 * (1920), .y_mili = 0.2936875
* (1080), .orientation = 1, }, { .x_res = 1920, .y_res = 1080
, .bits = 32, .stride = (1920) * (32) / 8, .x_mili = 0.2936875
* (1920), .y_mili = 0.2936875 * (1080), .orientation = 1, },
110 /* these modes need more than 8 MB video memory */
111 QXL_MODE_EX(1920, 1200){ .x_res = 1920, .y_res = 1200, .bits = 16, .stride = (1920) *
(16) / 8, .x_mili = 0.2936875 * (1920), .y_mili = 0.2936875 *
(1200), .orientation = 0, }, { .x_res = 1920, .y_res = 1200,
.bits = 32, .stride = (1920) * (32) / 8, .x_mili = 0.2936875
* (1920), .y_mili = 0.2936875 * (1200), .orientation = 0, },
{ .x_res = 1920, .y_res = 1200, .bits = 16, .stride = (1920)
* (16) / 8, .x_mili = 0.2936875 * (1920), .y_mili = 0.2936875
* (1200), .orientation = 1, }, { .x_res = 1920, .y_res = 1200
, .bits = 32, .stride = (1920) * (32) / 8, .x_mili = 0.2936875
* (1920), .y_mili = 0.2936875 * (1200), .orientation = 1, },
112 QXL_MODE_EX(1920, 1440){ .x_res = 1920, .y_res = 1440, .bits = 16, .stride = (1920) *
(16) / 8, .x_mili = 0.2936875 * (1920), .y_mili = 0.2936875 *
(1440), .orientation = 0, }, { .x_res = 1920, .y_res = 1440,
.bits = 32, .stride = (1920) * (32) / 8, .x_mili = 0.2936875
* (1920), .y_mili = 0.2936875 * (1440), .orientation = 0, },
{ .x_res = 1920, .y_res = 1440, .bits = 16, .stride = (1920)
* (16) / 8, .x_mili = 0.2936875 * (1920), .y_mili = 0.2936875
* (1440), .orientation = 1, }, { .x_res = 1920, .y_res = 1440
, .bits = 32, .stride = (1920) * (32) / 8, .x_mili = 0.2936875
* (1920), .y_mili = 0.2936875 * (1440), .orientation = 1, },
113 QXL_MODE_EX(2000, 2000){ .x_res = 2000, .y_res = 2000, .bits = 16, .stride = (2000) *
(16) / 8, .x_mili = 0.2936875 * (2000), .y_mili = 0.2936875 *
(2000), .orientation = 0, }, { .x_res = 2000, .y_res = 2000,
.bits = 32, .stride = (2000) * (32) / 8, .x_mili = 0.2936875
* (2000), .y_mili = 0.2936875 * (2000), .orientation = 0, },
{ .x_res = 2000, .y_res = 2000, .bits = 16, .stride = (2000)
* (16) / 8, .x_mili = 0.2936875 * (2000), .y_mili = 0.2936875
* (2000), .orientation = 1, }, { .x_res = 2000, .y_res = 2000
, .bits = 32, .stride = (2000) * (32) / 8, .x_mili = 0.2936875
* (2000), .y_mili = 0.2936875 * (2000), .orientation = 1, },
114 QXL_MODE_EX(2048, 1536){ .x_res = 2048, .y_res = 1536, .bits = 16, .stride = (2048) *
(16) / 8, .x_mili = 0.2936875 * (2048), .y_mili = 0.2936875 *
(1536), .orientation = 0, }, { .x_res = 2048, .y_res = 1536,
.bits = 32, .stride = (2048) * (32) / 8, .x_mili = 0.2936875
* (2048), .y_mili = 0.2936875 * (1536), .orientation = 0, },
{ .x_res = 2048, .y_res = 1536, .bits = 16, .stride = (2048)
* (16) / 8, .x_mili = 0.2936875 * (2048), .y_mili = 0.2936875
* (1536), .orientation = 1, }, { .x_res = 2048, .y_res = 1536
, .bits = 32, .stride = (2048) * (32) / 8, .x_mili = 0.2936875
* (2048), .y_mili = 0.2936875 * (1536), .orientation = 1, },
115 QXL_MODE_EX(2048, 2048){ .x_res = 2048, .y_res = 2048, .bits = 16, .stride = (2048) *
(16) / 8, .x_mili = 0.2936875 * (2048), .y_mili = 0.2936875 *
(2048), .orientation = 0, }, { .x_res = 2048, .y_res = 2048,
.bits = 32, .stride = (2048) * (32) / 8, .x_mili = 0.2936875
* (2048), .y_mili = 0.2936875 * (2048), .orientation = 0, },
{ .x_res = 2048, .y_res = 2048, .bits = 16, .stride = (2048)
* (16) / 8, .x_mili = 0.2936875 * (2048), .y_mili = 0.2936875
* (2048), .orientation = 1, }, { .x_res = 2048, .y_res = 2048
, .bits = 32, .stride = (2048) * (32) / 8, .x_mili = 0.2936875
* (2048), .y_mili = 0.2936875 * (2048), .orientation = 1, },
116 QXL_MODE_EX(2560, 1440){ .x_res = 2560, .y_res = 1440, .bits = 16, .stride = (2560) *
(16) / 8, .x_mili = 0.2936875 * (2560), .y_mili = 0.2936875 *
(1440), .orientation = 0, }, { .x_res = 2560, .y_res = 1440,
.bits = 32, .stride = (2560) * (32) / 8, .x_mili = 0.2936875
* (2560), .y_mili = 0.2936875 * (1440), .orientation = 0, },
{ .x_res = 2560, .y_res = 1440, .bits = 16, .stride = (2560)
* (16) / 8, .x_mili = 0.2936875 * (2560), .y_mili = 0.2936875
* (1440), .orientation = 1, }, { .x_res = 2560, .y_res = 1440
, .bits = 32, .stride = (2560) * (32) / 8, .x_mili = 0.2936875
* (2560), .y_mili = 0.2936875 * (1440), .orientation = 1, },
117 QXL_MODE_EX(2560, 1600){ .x_res = 2560, .y_res = 1600, .bits = 16, .stride = (2560) *
(16) / 8, .x_mili = 0.2936875 * (2560), .y_mili = 0.2936875 *
(1600), .orientation = 0, }, { .x_res = 2560, .y_res = 1600,
.bits = 32, .stride = (2560) * (32) / 8, .x_mili = 0.2936875
* (2560), .y_mili = 0.2936875 * (1600), .orientation = 0, },
{ .x_res = 2560, .y_res = 1600, .bits = 16, .stride = (2560)
* (16) / 8, .x_mili = 0.2936875 * (2560), .y_mili = 0.2936875
* (1600), .orientation = 1, }, { .x_res = 2560, .y_res = 1600
, .bits = 32, .stride = (2560) * (32) / 8, .x_mili = 0.2936875
* (2560), .y_mili = 0.2936875 * (1600), .orientation = 1, },
118 /* these modes need more than 16 MB video memory */
119 QXL_MODE_EX(2560, 2048){ .x_res = 2560, .y_res = 2048, .bits = 16, .stride = (2560) *
(16) / 8, .x_mili = 0.2936875 * (2560), .y_mili = 0.2936875 *
(2048), .orientation = 0, }, { .x_res = 2560, .y_res = 2048,
.bits = 32, .stride = (2560) * (32) / 8, .x_mili = 0.2936875
* (2560), .y_mili = 0.2936875 * (2048), .orientation = 0, },
{ .x_res = 2560, .y_res = 2048, .bits = 16, .stride = (2560)
* (16) / 8, .x_mili = 0.2936875 * (2560), .y_mili = 0.2936875
* (2048), .orientation = 1, }, { .x_res = 2560, .y_res = 2048
, .bits = 32, .stride = (2560) * (32) / 8, .x_mili = 0.2936875
* (2560), .y_mili = 0.2936875 * (2048), .orientation = 1, },
120 QXL_MODE_EX(2800, 2100){ .x_res = 2800, .y_res = 2100, .bits = 16, .stride = (2800) *
(16) / 8, .x_mili = 0.2936875 * (2800), .y_mili = 0.2936875 *
(2100), .orientation = 0, }, { .x_res = 2800, .y_res = 2100,
.bits = 32, .stride = (2800) * (32) / 8, .x_mili = 0.2936875
* (2800), .y_mili = 0.2936875 * (2100), .orientation = 0, },
{ .x_res = 2800, .y_res = 2100, .bits = 16, .stride = (2800)
* (16) / 8, .x_mili = 0.2936875 * (2800), .y_mili = 0.2936875
* (2100), .orientation = 1, }, { .x_res = 2800, .y_res = 2100
, .bits = 32, .stride = (2800) * (32) / 8, .x_mili = 0.2936875
* (2800), .y_mili = 0.2936875 * (2100), .orientation = 1, },
121 QXL_MODE_EX(3200, 2400){ .x_res = 3200, .y_res = 2400, .bits = 16, .stride = (3200) *
(16) / 8, .x_mili = 0.2936875 * (3200), .y_mili = 0.2936875 *
(2400), .orientation = 0, }, { .x_res = 3200, .y_res = 2400,
.bits = 32, .stride = (3200) * (32) / 8, .x_mili = 0.2936875
* (3200), .y_mili = 0.2936875 * (2400), .orientation = 0, },
{ .x_res = 3200, .y_res = 2400, .bits = 16, .stride = (3200)
* (16) / 8, .x_mili = 0.2936875 * (3200), .y_mili = 0.2936875
* (2400), .orientation = 1, }, { .x_res = 3200, .y_res = 2400
, .bits = 32, .stride = (3200) * (32) / 8, .x_mili = 0.2936875
* (3200), .y_mili = 0.2936875 * (2400), .orientation = 1, },
122 QXL_MODE_EX(3840, 2160){ .x_res = 3840, .y_res = 2160, .bits = 16, .stride = (3840) *
(16) / 8, .x_mili = 0.2936875 * (3840), .y_mili = 0.2936875 *
(2160), .orientation = 0, }, { .x_res = 3840, .y_res = 2160,
.bits = 32, .stride = (3840) * (32) / 8, .x_mili = 0.2936875
* (3840), .y_mili = 0.2936875 * (2160), .orientation = 0, },
{ .x_res = 3840, .y_res = 2160, .bits = 16, .stride = (3840)
* (16) / 8, .x_mili = 0.2936875 * (3840), .y_mili = 0.2936875
* (2160), .orientation = 1, }, { .x_res = 3840, .y_res = 2160
, .bits = 32, .stride = (3840) * (32) / 8, .x_mili = 0.2936875
* (3840), .y_mili = 0.2936875 * (2160), .orientation = 1, }, /* 4k mainstream */
123 QXL_MODE_EX(4096, 2160){ .x_res = 4096, .y_res = 2160, .bits = 16, .stride = (4096) *
(16) / 8, .x_mili = 0.2936875 * (4096), .y_mili = 0.2936875 *
(2160), .orientation = 0, }, { .x_res = 4096, .y_res = 2160,
.bits = 32, .stride = (4096) * (32) / 8, .x_mili = 0.2936875
* (4096), .y_mili = 0.2936875 * (2160), .orientation = 0, },
{ .x_res = 4096, .y_res = 2160, .bits = 16, .stride = (4096)
* (16) / 8, .x_mili = 0.2936875 * (4096), .y_mili = 0.2936875
* (2160), .orientation = 1, }, { .x_res = 4096, .y_res = 2160
, .bits = 32, .stride = (4096) * (32) / 8, .x_mili = 0.2936875
* (4096), .y_mili = 0.2936875 * (2160), .orientation = 1, }, /* 4k */
124 QXL_MODE_EX(7680, 4320){ .x_res = 7680, .y_res = 4320, .bits = 16, .stride = (7680) *
(16) / 8, .x_mili = 0.2936875 * (7680), .y_mili = 0.2936875 *
(4320), .orientation = 0, }, { .x_res = 7680, .y_res = 4320,
.bits = 32, .stride = (7680) * (32) / 8, .x_mili = 0.2936875
* (7680), .y_mili = 0.2936875 * (4320), .orientation = 0, },
{ .x_res = 7680, .y_res = 4320, .bits = 16, .stride = (7680)
* (16) / 8, .x_mili = 0.2936875 * (7680), .y_mili = 0.2936875
* (4320), .orientation = 1, }, { .x_res = 7680, .y_res = 4320
, .bits = 32, .stride = (7680) * (32) / 8, .x_mili = 0.2936875
* (7680), .y_mili = 0.2936875 * (4320), .orientation = 1, }, /* 8k mainstream */
125 QXL_MODE_EX(8192, 4320){ .x_res = 8192, .y_res = 4320, .bits = 16, .stride = (8192) *
(16) / 8, .x_mili = 0.2936875 * (8192), .y_mili = 0.2936875 *
(4320), .orientation = 0, }, { .x_res = 8192, .y_res = 4320,
.bits = 32, .stride = (8192) * (32) / 8, .x_mili = 0.2936875
* (8192), .y_mili = 0.2936875 * (4320), .orientation = 0, },
{ .x_res = 8192, .y_res = 4320, .bits = 16, .stride = (8192)
* (16) / 8, .x_mili = 0.2936875 * (8192), .y_mili = 0.2936875
* (4320), .orientation = 1, }, { .x_res = 8192, .y_res = 4320
, .bits = 32, .stride = (8192) * (32) / 8, .x_mili = 0.2936875
* (8192), .y_mili = 0.2936875 * (4320), .orientation = 1, }, /* 8k */
126};
127
128static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
129static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
130static void qxl_reset_memslots(PCIQXLDevice *d);
131static void qxl_reset_surfaces(PCIQXLDevice *d);
132static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
133
134void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
135{
136 trace_qxl_set_guest_bug(qxl->id);
137 qxl_send_events(qxl, QXL_INTERRUPT_ERROR(1 << 3));
138 qxl->guest_bug = 1;
139 if (qxl->guestdebug) {
140 va_list ap;
141 va_start(ap, msg)__builtin_va_start(ap, msg);
142 fprintf(stderrstderr, "qxl-%d: guest bug: ", qxl->id);
143 vfprintf(stderrstderr, msg, ap);
144 fprintf(stderrstderr, "\n");
145 va_end(ap)__builtin_va_end(ap);
146 }
147}
148
149static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
150{
151 qxl->guest_bug = 0;
152}
153
154void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
155 struct QXLRect *area, struct QXLRect *dirty_rects,
156 uint32_t num_dirty_rects,
157 uint32_t clear_dirty_region,
158 qxl_async_io async, struct QXLCookie *cookie)
159{
160 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
161 area->top, area->bottom);
162 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
163 clear_dirty_region);
164 if (async == QXL_SYNC) {
165 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
166 dirty_rects, num_dirty_rects, clear_dirty_region);
167 } else {
168 assert(cookie != NULL)((cookie != ((void*)0)) ? (void) (0) : __assert_fail ("cookie != ((void*)0)"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c", 168
, __PRETTY_FUNCTION__));
169 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
170 clear_dirty_region, (uintptr_t)cookie);
171 }
172}
173
174static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
175 uint32_t id)
176{
177 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
178 qemu_mutex_lock(&qxl->track_lock);
179 qxl->guest_surfaces.cmds[id] = 0;
180 qxl->guest_surfaces.count--;
181 qemu_mutex_unlock(&qxl->track_lock);
182}
183
184static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
185 qxl_async_io async)
186{
187 QXLCookie *cookie;
188
189 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
190 if (async) {
191 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
192 QXL_IO_DESTROY_SURFACE_ASYNC);
193 cookie->u.surface_id = id;
194 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
195 } else {
196 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
197 qxl_spice_destroy_surface_wait_complete(qxl, id);
198 }
199}
200
201static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
202{
203 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
204 qxl->num_free_res);
205 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
206 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
207 QXL_IO_FLUSH_SURFACES_ASYNC));
208}
209
210void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
211 uint32_t count)
212{
213 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
214 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
215}
216
217void qxl_spice_oom(PCIQXLDevice *qxl)
218{
219 trace_qxl_spice_oom(qxl->id);
220 spice_qxl_oom(&qxl->ssd.qxl);
221}
222
223void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
224{
225 trace_qxl_spice_reset_memslots(qxl->id);
226 spice_qxl_reset_memslots(&qxl->ssd.qxl);
227}
228
229static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
230{
231 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
232 qemu_mutex_lock(&qxl->track_lock);
233 memset(qxl->guest_surfaces.cmds, 0,
234 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
235 qxl->guest_surfaces.count = 0;
236 qemu_mutex_unlock(&qxl->track_lock);
237}
238
239static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
240{
241 trace_qxl_spice_destroy_surfaces(qxl->id, async);
242 if (async) {
243 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
244 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
245 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
246 } else {
247 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
248 qxl_spice_destroy_surfaces_complete(qxl);
249 }
250}
251
252static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
253{
254 trace_qxl_spice_monitors_config(qxl->id);
255 if (replay) {
256 /*
257 * don't use QXL_COOKIE_TYPE_IO:
258 * - we are not running yet (post_load), we will assert
259 * in send_events
260 * - this is not a guest io, but a reply, so async_io isn't set.
261 */
262 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
263 qxl->guest_monitors_config,
264 MEMSLOT_GROUP_GUEST1,
265 (uintptr_t)qxl_cookie_new(
266 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
267 0));
268 } else {
269 qxl->guest_monitors_config = qxl->ram->monitors_config;
270 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
271 qxl->ram->monitors_config,
272 MEMSLOT_GROUP_GUEST1,
273 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
274 QXL_IO_MONITORS_CONFIG_ASYNC));
275 }
276}
277
278void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
279{
280 trace_qxl_spice_reset_image_cache(qxl->id);
281 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
282}
283
284void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
285{
286 trace_qxl_spice_reset_cursor(qxl->id);
287 spice_qxl_reset_cursor(&qxl->ssd.qxl);
288 qemu_mutex_lock(&qxl->track_lock);
289 qxl->guest_cursor = 0;
290 qemu_mutex_unlock(&qxl->track_lock);
291 if (qxl->ssd.cursor) {
292 cursor_put(qxl->ssd.cursor);
293 }
294 qxl->ssd.cursor = cursor_builtin_hidden();
295}
296
297
298static inline uint32_t msb_mask(uint32_t val)
299{
300 uint32_t mask;
301
302 do {
303 mask = ~(val - 1) & val;
304 val &= ~mask;
305 } while (mask < val);
306
307 return mask;
308}
309
310static ram_addr_t qxl_rom_size(void)
311{
312 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) +
313 sizeof(qxl_modes);
314 uint32_t rom_size = 8192; /* two pages */
315
316 QEMU_BUILD_BUG_ON(required_rom_size > rom_size)typedef char qemu_build_bug_on__316[(required_rom_size > rom_size
)?-1:1] __attribute__((unused));;
317 return rom_size;
318}
319
320static void init_qxl_rom(PCIQXLDevice *d)
321{
322 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
323 QXLModes *modes = (QXLModes *)(rom + 1);
324 uint32_t ram_header_size;
325 uint32_t surface0_area_size;
326 uint32_t num_pages;
327 uint32_t fb;
328 int i, n;
329
330 memset(rom, 0, d->rom_size);
331
332 rom->magic = cpu_to_le32(QXL_ROM_MAGIC(*(const uint32_t*)"QXRO"));
333 rom->id = cpu_to_le32(d->id);
334 rom->log_level = cpu_to_le32(d->guestdebug);
335 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
336
337 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS8;
338 rom->slot_id_bits = MEMSLOT_SLOT_BITS8;
339 rom->slots_start = 1;
340 rom->slots_end = NUM_MEMSLOTS8 - 1;
341 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
342
343 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes)(sizeof(qxl_modes) / sizeof((qxl_modes)[0])); i++) {
344 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
345 if (fb > d->vgamem_size) {
346 continue;
347 }
348 modes->modes[n].id = cpu_to_le32(i);
349 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
350 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
351 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
352 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
353 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
354 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
355 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
356 n++;
357 }
358 modes->n_modes = cpu_to_le32(n);
359
360 ram_header_size = ALIGN(sizeof(QXLRam), 4096)(((sizeof(QXLRam)) + ((4096) - 1)) & ~((4096) - 1));
361 surface0_area_size = ALIGN(d->vgamem_size, 4096)(((d->vgamem_size) + ((4096) - 1)) & ~((4096) - 1));
362 num_pages = d->vga.vram_size;
363 num_pages -= ram_header_size;
364 num_pages -= surface0_area_size;
365 num_pages = num_pages / QXL_PAGE_SIZE(1 << 12);;
366
367 rom->draw_area_offset = cpu_to_le32(0);
368 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
369 rom->pages_offset = cpu_to_le32(surface0_area_size);
370 rom->num_pages = cpu_to_le32(num_pages);
371 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
372
373 d->shadow_rom = *rom;
374 d->rom = rom;
375 d->modes = modes;
376}
377
378static void init_qxl_ram(PCIQXLDevice *d)
379{
380 uint8_t *buf;
381 uint64_t *item;
382
383 buf = d->vga.vram_ptr;
384 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
385 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC(*(const uint32_t*)"QXRA"));
386 d->ram->int_pending = cpu_to_le32(0);
387 d->ram->int_mask = cpu_to_le32(0);
388 d->ram->update_surface = 0;
389 d->ram->monitors_config = 0;
390 SPICE_RING_INIT(&d->ram->cmd_ring)(&d->ram->cmd_ring)->num_items = sizeof((&d->
ram->cmd_ring)->items) >> (((sizeof((&d->ram
->cmd_ring)->items[0])) & 0xffff0000) ? ((((sizeof(
(&d->ram->cmd_ring)->items[0])) >> 16) &
0xff00) ? (((((sizeof((&d->ram->cmd_ring)->items
[0])) >> 16) >> 8) & 0xf0) ? ((((((sizeof((&
d->ram->cmd_ring)->items[0])) >> 16) >> 8
) >> 4) & 0x8) ? 3 : (((((sizeof((&d->ram->
cmd_ring)->items[0])) >> 16) >> 8) >> 4)
& 0x4) ? 2 : (((((sizeof((&d->ram->cmd_ring)->
items[0])) >> 16) >> 8) >> 4) & 0x2) ? 1
: 0) + 4 : (((((sizeof((&d->ram->cmd_ring)->items
[0])) >> 16) >> 8) & 0x8) ? 3 : ((((sizeof((&
d->ram->cmd_ring)->items[0])) >> 16) >> 8
) & 0x4) ? 2 : ((((sizeof((&d->ram->cmd_ring)->
items[0])) >> 16) >> 8) & 0x2) ? 1 : 0)) + 8 :
((((sizeof((&d->ram->cmd_ring)->items[0])) >>
16) & 0xf0) ? (((((sizeof((&d->ram->cmd_ring)->
items[0])) >> 16) >> 4) & 0x8) ? 3 : ((((sizeof
((&d->ram->cmd_ring)->items[0])) >> 16) >>
4) & 0x4) ? 2 : ((((sizeof((&d->ram->cmd_ring)
->items[0])) >> 16) >> 4) & 0x2) ? 1 : 0) +
4 : ((((sizeof((&d->ram->cmd_ring)->items[0])) >>
16) & 0x8) ? 3 : (((sizeof((&d->ram->cmd_ring)
->items[0])) >> 16) & 0x4) ? 2 : (((sizeof((&
d->ram->cmd_ring)->items[0])) >> 16) & 0x2
) ? 1 : 0))) + 16 : (((sizeof((&d->ram->cmd_ring)->
items[0])) & 0xff00) ? ((((sizeof((&d->ram->cmd_ring
)->items[0])) >> 8) & 0xf0) ? (((((sizeof((&
d->ram->cmd_ring)->items[0])) >> 8) >> 4
) & 0x8) ? 3 : ((((sizeof((&d->ram->cmd_ring)->
items[0])) >> 8) >> 4) & 0x4) ? 2 : ((((sizeof
((&d->ram->cmd_ring)->items[0])) >> 8) >>
4) & 0x2) ? 1 : 0) + 4 : ((((sizeof((&d->ram->
cmd_ring)->items[0])) >> 8) & 0x8) ? 3 : (((sizeof
((&d->ram->cmd_ring)->items[0])) >> 8) &
0x4) ? 2 : (((sizeof((&d->ram->cmd_ring)->items
[0])) >> 8) & 0x2) ? 1 : 0)) + 8 : (((sizeof((&
d->ram->cmd_ring)->items[0])) & 0xf0) ? ((((sizeof
((&d->ram->cmd_ring)->items[0])) >> 4) &
0x8) ? 3 : (((sizeof((&d->ram->cmd_ring)->items
[0])) >> 4) & 0x4) ? 2 : (((sizeof((&d->ram->
cmd_ring)->items[0])) >> 4) & 0x2) ? 1 : 0) + 4 :
(((sizeof((&d->ram->cmd_ring)->items[0])) &
0x8) ? 3 : ((sizeof((&d->ram->cmd_ring)->items[
0])) & 0x4) ? 2 : ((sizeof((&d->ram->cmd_ring)->
items[0])) & 0x2) ? 1 : 0)))); (&d->ram->cmd_ring
)->prod = (&d->ram->cmd_ring)->cons = 0; (&
d->ram->cmd_ring)->notify_on_prod = 1; (&d->ram
->cmd_ring)->notify_on_cons = 0;;
391 SPICE_RING_INIT(&d->ram->cursor_ring)(&d->ram->cursor_ring)->num_items = sizeof((&
d->ram->cursor_ring)->items) >> (((sizeof((&
d->ram->cursor_ring)->items[0])) & 0xffff0000) ?
((((sizeof((&d->ram->cursor_ring)->items[0])) >>
16) & 0xff00) ? (((((sizeof((&d->ram->cursor_ring
)->items[0])) >> 16) >> 8) & 0xf0) ? (((((
(sizeof((&d->ram->cursor_ring)->items[0])) >>
16) >> 8) >> 4) & 0x8) ? 3 : (((((sizeof((&
d->ram->cursor_ring)->items[0])) >> 16) >>
8) >> 4) & 0x4) ? 2 : (((((sizeof((&d->ram->
cursor_ring)->items[0])) >> 16) >> 8) >>
4) & 0x2) ? 1 : 0) + 4 : (((((sizeof((&d->ram->
cursor_ring)->items[0])) >> 16) >> 8) & 0x8
) ? 3 : ((((sizeof((&d->ram->cursor_ring)->items
[0])) >> 16) >> 8) & 0x4) ? 2 : ((((sizeof((&
d->ram->cursor_ring)->items[0])) >> 16) >>
8) & 0x2) ? 1 : 0)) + 8 : ((((sizeof((&d->ram->
cursor_ring)->items[0])) >> 16) & 0xf0) ? (((((sizeof
((&d->ram->cursor_ring)->items[0])) >> 16)
>> 4) & 0x8) ? 3 : ((((sizeof((&d->ram->
cursor_ring)->items[0])) >> 16) >> 4) & 0x4
) ? 2 : ((((sizeof((&d->ram->cursor_ring)->items
[0])) >> 16) >> 4) & 0x2) ? 1 : 0) + 4 : ((((
sizeof((&d->ram->cursor_ring)->items[0])) >>
16) & 0x8) ? 3 : (((sizeof((&d->ram->cursor_ring
)->items[0])) >> 16) & 0x4) ? 2 : (((sizeof((&
d->ram->cursor_ring)->items[0])) >> 16) & 0x2
) ? 1 : 0))) + 16 : (((sizeof((&d->ram->cursor_ring
)->items[0])) & 0xff00) ? ((((sizeof((&d->ram->
cursor_ring)->items[0])) >> 8) & 0xf0) ? (((((sizeof
((&d->ram->cursor_ring)->items[0])) >> 8) >>
4) & 0x8) ? 3 : ((((sizeof((&d->ram->cursor_ring
)->items[0])) >> 8) >> 4) & 0x4) ? 2 : (((
(sizeof((&d->ram->cursor_ring)->items[0])) >>
8) >> 4) & 0x2) ? 1 : 0) + 4 : ((((sizeof((&d->
ram->cursor_ring)->items[0])) >> 8) & 0x8) ? 3
: (((sizeof((&d->ram->cursor_ring)->items[0])) >>
8) & 0x4) ? 2 : (((sizeof((&d->ram->cursor_ring
)->items[0])) >> 8) & 0x2) ? 1 : 0)) + 8 : (((sizeof
((&d->ram->cursor_ring)->items[0])) & 0xf0) ?
((((sizeof((&d->ram->cursor_ring)->items[0])) >>
4) & 0x8) ? 3 : (((sizeof((&d->ram->cursor_ring
)->items[0])) >> 4) & 0x4) ? 2 : (((sizeof((&
d->ram->cursor_ring)->items[0])) >> 4) & 0x2
) ? 1 : 0) + 4 : (((sizeof((&d->ram->cursor_ring)->
items[0])) & 0x8) ? 3 : ((sizeof((&d->ram->cursor_ring
)->items[0])) & 0x4) ? 2 : ((sizeof((&d->ram->
cursor_ring)->items[0])) & 0x2) ? 1 : 0)))); (&d->
ram->cursor_ring)->prod = (&d->ram->cursor_ring
)->cons = 0; (&d->ram->cursor_ring)->notify_on_prod
= 1; (&d->ram->cursor_ring)->notify_on_cons = 0
;;
392 SPICE_RING_INIT(&d->ram->release_ring)(&d->ram->release_ring)->num_items = sizeof((&
d->ram->release_ring)->items) >> (((sizeof((&
d->ram->release_ring)->items[0])) & 0xffff0000) ?
((((sizeof((&d->ram->release_ring)->items[0])) >>
16) & 0xff00) ? (((((sizeof((&d->ram->release_ring
)->items[0])) >> 16) >> 8) & 0xf0) ? (((((
(sizeof((&d->ram->release_ring)->items[0])) >>
16) >> 8) >> 4) & 0x8) ? 3 : (((((sizeof((&
d->ram->release_ring)->items[0])) >> 16) >>
8) >> 4) & 0x4) ? 2 : (((((sizeof((&d->ram->
release_ring)->items[0])) >> 16) >> 8) >>
4) & 0x2) ? 1 : 0) + 4 : (((((sizeof((&d->ram->
release_ring)->items[0])) >> 16) >> 8) & 0x8
) ? 3 : ((((sizeof((&d->ram->release_ring)->items
[0])) >> 16) >> 8) & 0x4) ? 2 : ((((sizeof((&
d->ram->release_ring)->items[0])) >> 16) >>
8) & 0x2) ? 1 : 0)) + 8 : ((((sizeof((&d->ram->
release_ring)->items[0])) >> 16) & 0xf0) ? (((((
sizeof((&d->ram->release_ring)->items[0])) >>
16) >> 4) & 0x8) ? 3 : ((((sizeof((&d->ram->
release_ring)->items[0])) >> 16) >> 4) & 0x4
) ? 2 : ((((sizeof((&d->ram->release_ring)->items
[0])) >> 16) >> 4) & 0x2) ? 1 : 0) + 4 : ((((
sizeof((&d->ram->release_ring)->items[0])) >>
16) & 0x8) ? 3 : (((sizeof((&d->ram->release_ring
)->items[0])) >> 16) & 0x4) ? 2 : (((sizeof((&
d->ram->release_ring)->items[0])) >> 16) &
0x2) ? 1 : 0))) + 16 : (((sizeof((&d->ram->release_ring
)->items[0])) & 0xff00) ? ((((sizeof((&d->ram->
release_ring)->items[0])) >> 8) & 0xf0) ? (((((sizeof
((&d->ram->release_ring)->items[0])) >> 8)
>> 4) & 0x8) ? 3 : ((((sizeof((&d->ram->
release_ring)->items[0])) >> 8) >> 4) & 0x4
) ? 2 : ((((sizeof((&d->ram->release_ring)->items
[0])) >> 8) >> 4) & 0x2) ? 1 : 0) + 4 : ((((sizeof
((&d->ram->release_ring)->items[0])) >> 8)
& 0x8) ? 3 : (((sizeof((&d->ram->release_ring)
->items[0])) >> 8) & 0x4) ? 2 : (((sizeof((&
d->ram->release_ring)->items[0])) >> 8) & 0x2
) ? 1 : 0)) + 8 : (((sizeof((&d->ram->release_ring)
->items[0])) & 0xf0) ? ((((sizeof((&d->ram->
release_ring)->items[0])) >> 4) & 0x8) ? 3 : (((
sizeof((&d->ram->release_ring)->items[0])) >>
4) & 0x4) ? 2 : (((sizeof((&d->ram->release_ring
)->items[0])) >> 4) & 0x2) ? 1 : 0) + 4 : (((sizeof
((&d->ram->release_ring)->items[0])) & 0x8) ?
3 : ((sizeof((&d->ram->release_ring)->items[0])
) & 0x4) ? 2 : ((sizeof((&d->ram->release_ring)
->items[0])) & 0x2) ? 1 : 0)))); (&d->ram->release_ring
)->prod = (&d->ram->release_ring)->cons = 0; (
&d->ram->release_ring)->notify_on_prod = 1; (&
d->ram->release_ring)->notify_on_cons = 0;;
393 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item){ uint32_t prod = (&d->ram->release_ring)->prod &
((&d->ram->release_ring)->num_items - 1); if (prod
>= (sizeof((&d->ram->release_ring)->items) /
sizeof(((&d->ram->release_ring)->items)[0]))) {
qxl_set_guest_bug(d, "SPICE_RING_PROD_ITEM indices mismatch "
"%u >= %zu", prod, (sizeof((&d->ram->release_ring
)->items) / sizeof(((&d->ram->release_ring)->
items)[0]))); item = ((void*)0); } else { item = &(&d
->ram->release_ring)->items[prod].el; } };
394 assert(item)((item) ? (void) (0) : __assert_fail ("item", "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c"
, 394, __PRETTY_FUNCTION__));
395 *item = 0;
396 qxl_ring_set_dirty(d);
397}
398
399/* can be called from spice server thread context */
400static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
401{
402 memory_region_set_dirty(mr, addr, end - addr);
403}
404
405static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
406{
407 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
408}
409
410/* called from spice server thread context only */
411static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
412{
413 void *base = qxl->vga.vram_ptr;
414 intptr_t offset;
415
416 offset = ptr - base;
417 assert(offset < qxl->vga.vram_size)((offset < qxl->vga.vram_size) ? (void) (0) : __assert_fail
("offset < qxl->vga.vram_size", "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c"
, 417, __PRETTY_FUNCTION__));
418 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
419}
420
421/* can be called from spice server thread context */
422static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
423{
424 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
425 ram_addr_t end = qxl->vga.vram_size;
426 qxl_set_dirty(&qxl->vga.vram, addr, end);
427}
428
429/*
430 * keep track of some command state, for savevm/loadvm.
431 * called from spice server thread context only
432 */
433static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
434{
435 switch (le32_to_cpu(ext->cmd.type)) {
436 case QXL_CMD_SURFACE:
437 {
438 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
439
440 if (!cmd) {
441 return 1;
442 }
443 uint32_t id = le32_to_cpu(cmd->surface_id);
444
445 if (id >= qxl->ssd.num_surfaces) {
446 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
447 qxl->ssd.num_surfaces);
448 return 1;
449 }
450 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
451 (cmd->u.surface_create.stride & 0x03) != 0) {
452 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
453 cmd->u.surface_create.stride);
454 return 1;
455 }
456 qemu_mutex_lock(&qxl->track_lock);
457 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
458 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
459 qxl->guest_surfaces.count++;
460 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
461 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
462 }
463 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
464 qxl->guest_surfaces.cmds[id] = 0;
465 qxl->guest_surfaces.count--;
466 }
467 qemu_mutex_unlock(&qxl->track_lock);
468 break;
469 }
470 case QXL_CMD_CURSOR:
471 {
472 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
473
474 if (!cmd) {
475 return 1;
476 }
477 if (cmd->type == QXL_CURSOR_SET) {
478 qemu_mutex_lock(&qxl->track_lock);
479 qxl->guest_cursor = ext->cmd.data;
480 qemu_mutex_unlock(&qxl->track_lock);
481 }
482 break;
483 }
484 }
485 return 0;
486}
487
488/* spice display interface callbacks */
489
490static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
491{
492 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
493
494 trace_qxl_interface_attach_worker(qxl->id);
495 qxl->ssd.worker = qxl_worker;
496}
497
498static void interface_set_compression_level(QXLInstance *sin, int level)
499{
500 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
501
502 trace_qxl_interface_set_compression_level(qxl->id, level);
503 qxl->shadow_rom.compression_level = cpu_to_le32(level);
504 qxl->rom->compression_level = cpu_to_le32(level);
505 qxl_rom_set_dirty(qxl);
506}
507
508static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
509{
510 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
511
512 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
513 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
514 qxl->rom->mm_clock = cpu_to_le32(mm_time);
515 qxl_rom_set_dirty(qxl);
516}
517
518static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
519{
520 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
521
522 trace_qxl_interface_get_init_info(qxl->id);
523 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS8;
524 info->memslot_id_bits = MEMSLOT_SLOT_BITS8;
525 info->num_memslots = NUM_MEMSLOTS8;
526 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS2;
527 info->internal_groupslot_id = 0;
528 info->qxl_ram_size =
529 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS12;
530 info->n_surfaces = qxl->ssd.num_surfaces;
531}
532
533static const char *qxl_mode_to_string(int mode)
534{
535 switch (mode) {
536 case QXL_MODE_COMPAT:
537 return "compat";
538 case QXL_MODE_NATIVE:
539 return "native";
540 case QXL_MODE_UNDEFINED:
541 return "undefined";
542 case QXL_MODE_VGA:
543 return "vga";
544 }
545 return "INVALID";
546}
547
548static const char *io_port_to_string(uint32_t io_port)
549{
550 if (io_port >= QXL_IO_RANGE_SIZE) {
551 return "out of range";
552 }
553 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
554 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
555 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
556 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
557 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
558 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
559 [QXL_IO_RESET] = "QXL_IO_RESET",
560 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
561 [QXL_IO_LOG] = "QXL_IO_LOG",
562 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
563 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
564 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
565 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
566 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
567 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
568 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
569 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
570 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
571 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
572 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
573 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
574 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
575 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
576 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
577 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
578 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
579 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
580 };
581 return io_port_to_string[io_port];
582}
583
584/* called from spice server thread context only */
585static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
586{
587 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
588 SimpleSpiceUpdate *update;
589 QXLCommandRing *ring;
590 QXLCommand *cmd;
591 int notify, ret;
592
593 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
594
595 switch (qxl->mode) {
596 case QXL_MODE_VGA:
597 ret = false0;
598 qemu_mutex_lock(&qxl->ssd.lock);
599 update = QTAILQ_FIRST(&qxl->ssd.updates)((&qxl->ssd.updates)->tqh_first);
600 if (update != NULL((void*)0)) {
601 QTAILQ_REMOVE(&qxl->ssd.updates, update, next)do { if (((update)->next.tqe_next) != ((void*)0)) (update)
->next.tqe_next->next.tqe_prev = (update)->next.tqe_prev
; else (&qxl->ssd.updates)->tqh_last = (update)->
next.tqe_prev; *(update)->next.tqe_prev = (update)->next
.tqe_next; } while ( 0);
602 *ext = update->ext;
603 ret = true1;
604 }
605 qemu_mutex_unlock(&qxl->ssd.lock);
606 if (ret) {
607 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
608 qxl_log_command(qxl, "vga", ext);
609 }
610 return ret;
611 case QXL_MODE_COMPAT:
612 case QXL_MODE_NATIVE:
613 case QXL_MODE_UNDEFINED:
614 ring = &qxl->ram->cmd_ring;
615 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)((ring)->cons == (ring)->prod)) {
616 return false0;
617 }
618 SPICE_RING_CONS_ITEM(qxl, ring, cmd){ uint32_t cons = (ring)->cons & ((ring)->num_items
- 1); if (cons >= (sizeof((ring)->items) / sizeof(((ring
)->items)[0]))) { qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch "
"%u >= %zu", cons, (sizeof((ring)->items) / sizeof(((ring
)->items)[0]))); cmd = ((void*)0); } else { cmd = &(ring
)->items[cons].el; } };
619 if (!cmd) {
620 return false0;
621 }
622 ext->cmd = *cmd;
623 ext->group_id = MEMSLOT_GROUP_GUEST1;
624 ext->flags = qxl->cmdflags;
625 SPICE_RING_POP(ring, notify)(ring)->cons++; __asm__ __volatile__ ("lock; addl $0,0(%%rsp)"
: : :"memory"); (notify) = (ring)->cons == (ring)->notify_on_cons
;;
626 qxl_ring_set_dirty(qxl);
627 if (notify) {
628 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY(1 << 0));
629 }
630 qxl->guest_primary.commands++;
631 qxl_track_command(qxl, ext);
632 qxl_log_command(qxl, "cmd", ext);
633 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
634 return true1;
635 default:
636 return false0;
637 }
638}
639
640/* called from spice server thread context only */
641static int interface_req_cmd_notification(QXLInstance *sin)
642{
643 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
644 int wait = 1;
645
646 trace_qxl_ring_command_req_notification(qxl->id);
647 switch (qxl->mode) {
648 case QXL_MODE_COMPAT:
649 case QXL_MODE_NATIVE:
650 case QXL_MODE_UNDEFINED:
651 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait)if (((wait) = ((&qxl->ram->cmd_ring)->cons == (&
qxl->ram->cmd_ring)->prod))) { (&qxl->ram->
cmd_ring)->notify_on_prod = (&qxl->ram->cmd_ring
)->prod + 1; __asm__ __volatile__ ("lock; addl $0,0(%%rsp)"
: : :"memory"); (wait) = ((&qxl->ram->cmd_ring)->
cons == (&qxl->ram->cmd_ring)->prod); };
652 qxl_ring_set_dirty(qxl);
653 break;
654 default:
655 /* nothing */
656 break;
657 }
658 return wait;
659}
660
661/* called from spice server thread context only */
662static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
663{
664 QXLReleaseRing *ring = &d->ram->release_ring;
665 uint64_t *item;
666 int notify;
667
668#define QXL_FREE_BUNCH_SIZE32 32
669
670 if (ring->prod - ring->cons + 1 == ring->num_items) {
671 /* ring full -- can't push */
672 return;
673 }
674 if (!flush && d->oom_running) {
675 /* collect everything from oom handler before pushing */
676 return;
677 }
678 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE32) {
679 /* collect a bit more before pushing */
680 return;
681 }
682
683 SPICE_RING_PUSH(ring, notify)(ring)->prod++; __asm__ __volatile__ ("lock; addl $0,0(%%rsp)"
: : :"memory"); (notify) = (ring)->prod == (ring)->notify_on_prod
;;
684 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
685 d->guest_surfaces.count, d->num_free_res,
686 d->last_release, notify ? "yes" : "no");
687 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
688 ring->num_items, ring->prod, ring->cons);
689 if (notify) {
690 qxl_send_events(d, QXL_INTERRUPT_DISPLAY(1 << 0));
691 }
692 SPICE_RING_PROD_ITEM(d, ring, item){ uint32_t prod = (ring)->prod & ((ring)->num_items
- 1); if (prod >= (sizeof((ring)->items) / sizeof(((ring
)->items)[0]))) { qxl_set_guest_bug(d, "SPICE_RING_PROD_ITEM indices mismatch "
"%u >= %zu", prod, (sizeof((ring)->items) / sizeof(((ring
)->items)[0]))); item = ((void*)0); } else { item = &(
ring)->items[prod].el; } };
693 if (!item) {
694 return;
695 }
696 *item = 0;
697 d->num_free_res = 0;
698 d->last_release = NULL((void*)0);
699 qxl_ring_set_dirty(d);
700}
701
702/* called from spice server thread context only */
703static void interface_release_resource(QXLInstance *sin,
704 struct QXLReleaseInfoExt ext)
705{
706 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
707 QXLReleaseRing *ring;
708 uint64_t *item, id;
709
710 if (ext.group_id == MEMSLOT_GROUP_HOST0) {
711 /* host group -> vga mode update request */
712 qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
713 return;
714 }
715
716 /*
717 * ext->info points into guest-visible memory
718 * pci bar 0, $command.release_info
719 */
720 ring = &qxl->ram->release_ring;
721 SPICE_RING_PROD_ITEM(qxl, ring, item){ uint32_t prod = (ring)->prod & ((ring)->num_items
- 1); if (prod >= (sizeof((ring)->items) / sizeof(((ring
)->items)[0]))) { qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch "
"%u >= %zu", prod, (sizeof((ring)->items) / sizeof(((ring
)->items)[0]))); item = ((void*)0); } else { item = &(
ring)->items[prod].el; } };
722 if (!item) {
723 return;
724 }
725 if (*item == 0) {
726 /* stick head into the ring */
727 id = ext.info->id;
728 ext.info->next = 0;
729 qxl_ram_set_dirty(qxl, &ext.info->next);
730 *item = id;
731 qxl_ring_set_dirty(qxl);
732 } else {
733 /* append item to the list */
734 qxl->last_release->next = ext.info->id;
735 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
736 ext.info->next = 0;
737 qxl_ram_set_dirty(qxl, &ext.info->next);
738 }
739 qxl->last_release = ext.info;
740 qxl->num_free_res++;
741 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
742 qxl_push_free_res(qxl, 0);
743}
744
745/* called from spice server thread context only */
746static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
747{
748 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
749 QXLCursorRing *ring;
750 QXLCommand *cmd;
751 int notify;
752
753 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
754
755 switch (qxl->mode) {
756 case QXL_MODE_COMPAT:
757 case QXL_MODE_NATIVE:
758 case QXL_MODE_UNDEFINED:
759 ring = &qxl->ram->cursor_ring;
760 if (SPICE_RING_IS_EMPTY(ring)((ring)->cons == (ring)->prod)) {
761 return false0;
762 }
763 SPICE_RING_CONS_ITEM(qxl, ring, cmd){ uint32_t cons = (ring)->cons & ((ring)->num_items
- 1); if (cons >= (sizeof((ring)->items) / sizeof(((ring
)->items)[0]))) { qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch "
"%u >= %zu", cons, (sizeof((ring)->items) / sizeof(((ring
)->items)[0]))); cmd = ((void*)0); } else { cmd = &(ring
)->items[cons].el; } };
764 if (!cmd) {
765 return false0;
766 }
767 ext->cmd = *cmd;
768 ext->group_id = MEMSLOT_GROUP_GUEST1;
769 ext->flags = qxl->cmdflags;
770 SPICE_RING_POP(ring, notify)(ring)->cons++; __asm__ __volatile__ ("lock; addl $0,0(%%rsp)"
: : :"memory"); (notify) = (ring)->cons == (ring)->notify_on_cons
;;
771 qxl_ring_set_dirty(qxl);
772 if (notify) {
773 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR(1 << 1));
774 }
775 qxl->guest_primary.commands++;
776 qxl_track_command(qxl, ext);
777 qxl_log_command(qxl, "csr", ext);
778 if (qxl->id == 0) {
779 qxl_render_cursor(qxl, ext);
780 }
781 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
782 return true1;
783 default:
784 return false0;
785 }
786}
787
788/* called from spice server thread context only */
789static int interface_req_cursor_notification(QXLInstance *sin)
790{
791 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
792 int wait = 1;
793
794 trace_qxl_ring_cursor_req_notification(qxl->id);
795 switch (qxl->mode) {
796 case QXL_MODE_COMPAT:
797 case QXL_MODE_NATIVE:
798 case QXL_MODE_UNDEFINED:
799 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait)if (((wait) = ((&qxl->ram->cursor_ring)->cons ==
(&qxl->ram->cursor_ring)->prod))) { (&qxl->
ram->cursor_ring)->notify_on_prod = (&qxl->ram->
cursor_ring)->prod + 1; __asm__ __volatile__ ("lock; addl $0,0(%%rsp)"
: : :"memory"); (wait) = ((&qxl->ram->cursor_ring)->
cons == (&qxl->ram->cursor_ring)->prod); };
800 qxl_ring_set_dirty(qxl);
801 break;
802 default:
803 /* nothing */
804 break;
805 }
806 return wait;
807}
808
809/* called from spice server thread context */
810static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
811{
812 /*
813 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
814 * use by xf86-video-qxl and is defined out in the qxl windows driver.
815 * Probably was at some earlier version that is prior to git start (2009),
816 * and is still guest trigerrable.
817 */
818 fprintf(stderrstderr, "%s: deprecated\n", __func__);
819}
820
821/* called from spice server thread context only */
822static int interface_flush_resources(QXLInstance *sin)
823{
824 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
825 int ret;
826
827 ret = qxl->num_free_res;
828 if (ret) {
829 qxl_push_free_res(qxl, 1);
830 }
831 return ret;
832}
833
834static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
835
836/* called from spice server thread context only */
837static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
838{
839 uint32_t current_async;
840
841 qemu_mutex_lock(&qxl->async_lock);
842 current_async = qxl->current_async;
843 qxl->current_async = QXL_UNDEFINED_IO(4294967295U);
844 qemu_mutex_unlock(&qxl->async_lock);
845
846 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
847 if (!cookie) {
848 fprintf(stderrstderr, "qxl: %s: error, cookie is NULL\n", __func__);
849 return;
850 }
851 if (cookie && current_async != cookie->io) {
852 fprintf(stderrstderr,
853 "qxl: %s: error: current_async = %d != %"
854 PRId64"l" "d" " = cookie->io\n", __func__, current_async, cookie->io);
855 }
856 switch (current_async) {
857 case QXL_IO_MEMSLOT_ADD_ASYNC:
858 case QXL_IO_DESTROY_PRIMARY_ASYNC:
859 case QXL_IO_UPDATE_AREA_ASYNC:
860 case QXL_IO_FLUSH_SURFACES_ASYNC:
861 case QXL_IO_MONITORS_CONFIG_ASYNC:
862 break;
863 case QXL_IO_CREATE_PRIMARY_ASYNC:
864 qxl_create_guest_primary_complete(qxl);
865 break;
866 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
867 qxl_spice_destroy_surfaces_complete(qxl);
868 break;
869 case QXL_IO_DESTROY_SURFACE_ASYNC:
870 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
871 break;
872 default:
873 fprintf(stderrstderr, "qxl: %s: unexpected current_async %d\n", __func__,
874 current_async);
875 }
876 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD(1 << 2));
877}
878
879/* called from spice server thread context only */
880static void interface_update_area_complete(QXLInstance *sin,
881 uint32_t surface_id,
882 QXLRect *dirty, uint32_t num_updated_rects)
883{
884 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
885 int i;
886 int qxl_i;
887
888 qemu_mutex_lock(&qxl->ssd.lock);
889 if (surface_id != 0 || !qxl->render_update_cookie_num) {
890 qemu_mutex_unlock(&qxl->ssd.lock);
891 return;
892 }
893 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
894 dirty->right, dirty->top, dirty->bottom);
895 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
896 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS64) {
897 /*
898 * overflow - treat this as a full update. Not expected to be common.
899 */
900 trace_qxl_interface_update_area_complete_overflow(qxl->id,
901 QXL_NUM_DIRTY_RECTS64);
902 qxl->guest_primary.resized = 1;
903 }
904 if (qxl->guest_primary.resized) {
905 /*
906 * Don't bother copying or scheduling the bh since we will flip
907 * the whole area anyway on completion of the update_area async call
908 */
909 qemu_mutex_unlock(&qxl->ssd.lock);
910 return;
911 }
912 qxl_i = qxl->num_dirty_rects;
913 for (i = 0; i < num_updated_rects; i++) {
914 qxl->dirty[qxl_i++] = dirty[i];
915 }
916 qxl->num_dirty_rects += num_updated_rects;
917 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
918 qxl->num_dirty_rects);
919 qemu_bh_schedule(qxl->update_area_bh);
920 qemu_mutex_unlock(&qxl->ssd.lock);
921}
922
923/* called from spice server thread context only */
924static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
925{
926 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
927 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
928
929 switch (cookie->type) {
930 case QXL_COOKIE_TYPE_IO:
931 interface_async_complete_io(qxl, cookie);
932 g_free(cookie);
933 break;
934 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
935 qxl_render_update_area_done(qxl, cookie);
936 break;
937 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
938 break;
939 default:
940 fprintf(stderrstderr, "qxl: %s: unexpected cookie type %d\n",
941 __func__, cookie->type);
942 g_free(cookie);
943 }
944}
945
946/* called from spice server thread context only */
947static void interface_set_client_capabilities(QXLInstance *sin,
948 uint8_t client_present,
949 uint8_t caps[58])
950{
951 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
952
953 if (qxl->revision < 4) {
954 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
955 qxl->revision);
956 return;
957 }
958
959 if (runstate_check(RUN_STATE_INMIGRATE) ||
960 runstate_check(RUN_STATE_POSTMIGRATE)) {
961 return;
962 }
963
964 qxl->shadow_rom.client_present = client_present;
965 memcpy(qxl->shadow_rom.client_capabilities, caps,
966 sizeof(qxl->shadow_rom.client_capabilities));
967 qxl->rom->client_present = client_present;
968 memcpy(qxl->rom->client_capabilities, caps,
969 sizeof(qxl->rom->client_capabilities));
970 qxl_rom_set_dirty(qxl);
971
972 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT(1 << 4));
973}
974
975static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
976{
977 /*
978 * zlib xors the seed with 0xffffffff, and xors the result
979 * again with 0xffffffff; Both are not done with linux's crc32,
980 * which we want to be compatible with, so undo that.
981 */
982 return crc32(0xffffffff, p, len) ^ 0xffffffff;
983}
984
985/* called from main context only */
986static int interface_client_monitors_config(QXLInstance *sin,
987 VDAgentMonitorsConfig *monitors_config)
988{
989 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl)({ const typeof(((PCIQXLDevice *) 0)->ssd.qxl) *__mptr = (
sin); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.qxl));});
990 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
991 int i;
992
993 if (qxl->revision < 4) {
994 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
995 qxl->revision);
996 return 0;
997 }
998 /*
999 * Older windows drivers set int_mask to 0 when their ISR is called,
1000 * then later set it to ~0. So it doesn't relate to the actual interrupts
1001 * handled. However, they are old, so clearly they don't support this
1002 * interrupt
1003 */
1004 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1005 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG(1 << 5))) {
1006 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1007 qxl->ram->int_mask,
1008 monitors_config);
1009 return 0;
1010 }
1011 if (!monitors_config) {
1012 return 1;
1013 }
1014 memset(&rom->client_monitors_config, 0,
1015 sizeof(rom->client_monitors_config));
1016 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1017 /* monitors_config->flags ignored */
1018 if (rom->client_monitors_config.count >=
1019 ARRAY_SIZE(rom->client_monitors_config.heads)(sizeof(rom->client_monitors_config.heads) / sizeof((rom->
client_monitors_config.heads)[0]))) {
1020 trace_qxl_client_monitors_config_capped(qxl->id,
1021 monitors_config->num_of_monitors,
1022 ARRAY_SIZE(rom->client_monitors_config.heads)(sizeof(rom->client_monitors_config.heads) / sizeof((rom->
client_monitors_config.heads)[0])));
1023 rom->client_monitors_config.count =
1024 ARRAY_SIZE(rom->client_monitors_config.heads)(sizeof(rom->client_monitors_config.heads) / sizeof((rom->
client_monitors_config.heads)[0]));
1025 }
1026 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1027 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1028 QXLURect *rect = &rom->client_monitors_config.heads[i];
1029 /* monitor->depth ignored */
1030 rect->left = monitor->x;
1031 rect->top = monitor->y;
1032 rect->right = monitor->x + monitor->width;
1033 rect->bottom = monitor->y + monitor->height;
1034 }
1035 rom->client_monitors_config_crc = qxl_crc32(
1036 (const uint8_t *)&rom->client_monitors_config,
1037 sizeof(rom->client_monitors_config));
1038 trace_qxl_client_monitors_config_crc(qxl->id,
1039 sizeof(rom->client_monitors_config),
1040 rom->client_monitors_config_crc);
1041
1042 trace_qxl_interrupt_client_monitors_config(qxl->id,
1043 rom->client_monitors_config.count,
1044 rom->client_monitors_config.heads);
1045 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG(1 << 5));
1046 return 1;
1047}
1048
1049static const QXLInterface qxl_interface = {
1050 .base.type = SPICE_INTERFACE_QXL"qxl",
1051 .base.description = "qxl gpu",
1052 .base.major_version = SPICE_INTERFACE_QXL_MAJOR3,
1053 .base.minor_version = SPICE_INTERFACE_QXL_MINOR3,
1054
1055 .attache_worker = interface_attach_worker,
1056 .set_compression_level = interface_set_compression_level,
1057 .set_mm_time = interface_set_mm_time,
1058 .get_init_info = interface_get_init_info,
1059
1060 /* the callbacks below are called from spice server thread context */
1061 .get_command = interface_get_command,
1062 .req_cmd_notification = interface_req_cmd_notification,
1063 .release_resource = interface_release_resource,
1064 .get_cursor_command = interface_get_cursor_command,
1065 .req_cursor_notification = interface_req_cursor_notification,
1066 .notify_update = interface_notify_update,
1067 .flush_resources = interface_flush_resources,
1068 .async_complete = interface_async_complete,
1069 .update_area_complete = interface_update_area_complete,
1070 .set_client_capabilities = interface_set_client_capabilities,
1071 .client_monitors_config = interface_client_monitors_config,
1072};
1073
1074static void qxl_enter_vga_mode(PCIQXLDevice *d)
1075{
1076 if (d->mode == QXL_MODE_VGA) {
1077 return;
1078 }
1079 trace_qxl_enter_vga_mode(d->id);
1080#if SPICE_SERVER_VERSION0x000c04 >= 0x000c03 /* release 0.12.3 */
1081 spice_qxl_driver_unload(&d->ssd.qxl);
1082#endif
1083 qemu_spice_create_host_primary(&d->ssd);
1084 d->mode = QXL_MODE_VGA;
1085 vga_dirty_log_start(&d->vga);
1086 graphic_hw_update(d->vga.con);
1087}
1088
1089static void qxl_exit_vga_mode(PCIQXLDevice *d)
1090{
1091 if (d->mode != QXL_MODE_VGA) {
1092 return;
1093 }
1094 trace_qxl_exit_vga_mode(d->id);
1095 vga_dirty_log_stop(&d->vga);
1096 qxl_destroy_primary(d, QXL_SYNC);
1097}
1098
1099static void qxl_update_irq(PCIQXLDevice *d)
1100{
1101 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1102 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1103 int level = !!(pending & mask);
1104 pci_set_irq(&d->pci, level);
1105 qxl_ring_set_dirty(d);
1106}
1107
1108static void qxl_check_state(PCIQXLDevice *d)
1109{
1110 QXLRam *ram = d->ram;
1111 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
1112
1113 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring))((!spice_display_running || ((&ram->cmd_ring)->cons
== (&ram->cmd_ring)->prod)) ? (void) (0) : __assert_fail
("!spice_display_running || ((&ram->cmd_ring)->cons == (&ram->cmd_ring)->prod)"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c", 1113
, __PRETTY_FUNCTION__));
1114 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring))((!spice_display_running || ((&ram->cursor_ring)->cons
== (&ram->cursor_ring)->prod)) ? (void) (0) : __assert_fail
("!spice_display_running || ((&ram->cursor_ring)->cons == (&ram->cursor_ring)->prod)"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c", 1114
, __PRETTY_FUNCTION__));
1115}
1116
1117static void qxl_reset_state(PCIQXLDevice *d)
1118{
1119 QXLRom *rom = d->rom;
1120
1121 qxl_check_state(d);
1122 d->shadow_rom.update_id = cpu_to_le32(0);
1123 *rom = d->shadow_rom;
1124 qxl_rom_set_dirty(d);
1125 init_qxl_ram(d);
1126 d->num_free_res = 0;
1127 d->last_release = NULL((void*)0);
1128 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1129}
1130
1131static void qxl_soft_reset(PCIQXLDevice *d)
1132{
1133 trace_qxl_soft_reset(d->id);
1134 qxl_check_state(d);
1135 qxl_clear_guest_bug(d);
1136 d->current_async = QXL_UNDEFINED_IO(4294967295U);
1137
1138 if (d->id == 0) {
1139 qxl_enter_vga_mode(d);
1140 } else {
1141 d->mode = QXL_MODE_UNDEFINED;
1142 }
1143}
1144
1145static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1146{
1147 bool_Bool startstop = qemu_spice_display_is_running(&d->ssd);
1148
1149 trace_qxl_hard_reset(d->id, loadvm);
1150
1151 if (startstop) {
1152 qemu_spice_display_stop();
1153 }
1154
1155 qxl_spice_reset_cursor(d);
1156 qxl_spice_reset_image_cache(d);
1157 qxl_reset_surfaces(d);
1158 qxl_reset_memslots(d);
1159
1160 /* pre loadvm reset must not touch QXLRam. This lives in
1161 * device memory, is migrated together with RAM and thus
1162 * already loaded at this point */
1163 if (!loadvm) {
1164 qxl_reset_state(d);
1165 }
1166 qemu_spice_create_host_memslot(&d->ssd);
1167 qxl_soft_reset(d);
1168
1169 if (startstop) {
1170 qemu_spice_display_start();
1171 }
1172}
1173
1174static void qxl_reset_handler(DeviceState *dev)
1175{
1176 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(PCIQXLDevice, pci.qdev)]; ({ const typeof
(((PCIQXLDevice *) 0)->pci.qdev) *__mptr = (dev); (PCIQXLDevice
*) ((char *) __mptr - __builtin_offsetof(PCIQXLDevice, pci.qdev
));});}));
1177
1178 qxl_hard_reset(d, 0);
1179}
1180
1181static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1182{
1183 VGACommonState *vga = opaque;
1184 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga)({ const typeof(((PCIQXLDevice *) 0)->vga) *__mptr = (vga)
; (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(PCIQXLDevice
, vga));});
1185
1186 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1187 if (qxl->mode != QXL_MODE_VGA) {
1188 qxl_destroy_primary(qxl, QXL_SYNC);
1189 qxl_soft_reset(qxl);
1190 }
1191 vga_ioport_write(opaque, addr, val);
1192}
1193
1194static const MemoryRegionPortio qxl_vga_portio_list[] = {
1195 { 0x04, 2, 1, .read = vga_ioport_read,
1196 .write = qxl_vga_ioport_write }, /* 3b4 */
1197 { 0x0a, 1, 1, .read = vga_ioport_read,
1198 .write = qxl_vga_ioport_write }, /* 3ba */
1199 { 0x10, 16, 1, .read = vga_ioport_read,
1200 .write = qxl_vga_ioport_write }, /* 3c0 */
1201 { 0x24, 2, 1, .read = vga_ioport_read,
1202 .write = qxl_vga_ioport_write }, /* 3d4 */
1203 { 0x2a, 1, 1, .read = vga_ioport_read,
1204 .write = qxl_vga_ioport_write }, /* 3da */
1205 PORTIO_END_OF_LIST(){ },
1206};
1207
1208static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1209 qxl_async_io async)
1210{
1211 static const int regions[] = {
1212 QXL_RAM_RANGE_INDEX,
1213 QXL_VRAM_RANGE_INDEX,
1214 QXL_VRAM64_RANGE_INDEX4,
1215 };
1216 uint64_t guest_start;
1217 uint64_t guest_end;
1218 int pci_region;
1219 pcibus_t pci_start;
1220 pcibus_t pci_end;
1221 intptr_t virt_start;
1222 QXLDevMemSlot memslot;
1223 int i;
1224
1225 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1226 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1227
1228 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1229
1230 if (slot_id >= NUM_MEMSLOTS8) {
1231 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1232 slot_id, NUM_MEMSLOTS8);
1233 return 1;
1234 }
1235 if (guest_start > guest_end) {
1236 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64"l" "x"
1237 " > 0x%" PRIx64"l" "x", __func__, guest_start, guest_end);
1238 return 1;
1239 }
1240
1241 for (i = 0; i < ARRAY_SIZE(regions)(sizeof(regions) / sizeof((regions)[0])); i++) {
1242 pci_region = regions[i];
1243 pci_start = d->pci.io_regions[pci_region].addr;
1244 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1245 /* mapped? */
1246 if (pci_start == -1) {
1247 continue;
1248 }
1249 /* start address in range ? */
1250 if (guest_start < pci_start || guest_start > pci_end) {
1251 continue;
1252 }
1253 /* end address in range ? */
1254 if (guest_end > pci_end) {
1255 continue;
1256 }
1257 /* passed */
1258 break;
1259 }
1260 if (i == ARRAY_SIZE(regions)(sizeof(regions) / sizeof((regions)[0]))) {
1261 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1262 return 1;
1263 }
1264
1265 switch (pci_region) {
1266 case QXL_RAM_RANGE_INDEX:
1267 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
1268 break;
1269 case QXL_VRAM_RANGE_INDEX:
1270 case 4 /* vram 64bit */:
1271 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
1272 break;
1273 default:
1274 /* should not happen */
1275 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1276 return 1;
1277 }
1278
1279 memslot.slot_id = slot_id;
1280 memslot.slot_group_id = MEMSLOT_GROUP_GUEST1; /* guest group */
1281 memslot.virt_start = virt_start + (guest_start - pci_start);
1282 memslot.virt_end = virt_start + (guest_end - pci_start);
1283 memslot.addr_delta = memslot.virt_start - delta;
1284 memslot.generation = d->rom->slot_generation = 0;
1285 qxl_rom_set_dirty(d);
1286
1287 qemu_spice_add_memslot(&d->ssd, &memslot, async);
1288 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1289 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1290 d->guest_slots[slot_id].delta = delta;
1291 d->guest_slots[slot_id].active = 1;
1292 return 0;
1293}
1294
1295static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1296{
1297 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST0, slot_id);
1298 d->guest_slots[slot_id].active = 0;
1299}
1300
1301static void qxl_reset_memslots(PCIQXLDevice *d)
1302{
1303 qxl_spice_reset_memslots(d);
1304 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1305}
1306
1307static void qxl_reset_surfaces(PCIQXLDevice *d)
1308{
1309 trace_qxl_reset_surfaces(d->id);
1310 d->mode = QXL_MODE_UNDEFINED;
1311 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1312}
1313
1314/* can be also called from spice server thread context */
1315void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1316{
1317 uint64_t phys = le64_to_cpu(pqxl);
1318 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1319 uint64_t offset = phys & 0xffffffffffff;
1320
1321 switch (group_id) {
1322 case MEMSLOT_GROUP_HOST0:
1323 return (void *)(intptr_t)offset;
1324 case MEMSLOT_GROUP_GUEST1:
1325 if (slot >= NUM_MEMSLOTS8) {
1326 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1327 NUM_MEMSLOTS8);
1328 return NULL((void*)0);
1329 }
1330 if (!qxl->guest_slots[slot].active) {
1331 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1332 return NULL((void*)0);
1333 }
1334 if (offset < qxl->guest_slots[slot].delta) {
1335 qxl_set_guest_bug(qxl,
1336 "slot %d offset %"PRIu64"l" "u"" < delta %"PRIu64"l" "u""\n",
1337 slot, offset, qxl->guest_slots[slot].delta);
1338 return NULL((void*)0);
1339 }
1340 offset -= qxl->guest_slots[slot].delta;
1341 if (offset > qxl->guest_slots[slot].size) {
1342 qxl_set_guest_bug(qxl,
1343 "slot %d offset %"PRIu64"l" "u"" > size %"PRIu64"l" "u""\n",
1344 slot, offset, qxl->guest_slots[slot].size);
1345 return NULL((void*)0);
1346 }
1347 return qxl->guest_slots[slot].ptr + offset;
1348 }
1349 return NULL((void*)0);
1350}
1351
1352static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1353{
1354 /* for local rendering */
1355 qxl_render_resize(qxl);
1356}
1357
1358static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1359 qxl_async_io async)
1360{
1361 QXLDevSurfaceCreate surface;
1362 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1363 int size;
1364 int requested_height = le32_to_cpu(sc->height);
1365 int requested_stride = le32_to_cpu(sc->stride);
1366
1367 size = abs(requested_stride) * requested_height;
1368 if (size > qxl->vgamem_size) {
1369 qxl_set_guest_bug(qxl, "%s: requested primary larger then framebuffer"
1370 " size", __func__);
1371 return;
1372 }
1373
1374 if (qxl->mode == QXL_MODE_NATIVE) {
1375 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1376 __func__);
1377 }
1378 qxl_exit_vga_mode(qxl);
1379
1380 surface.format = le32_to_cpu(sc->format);
1381 surface.height = le32_to_cpu(sc->height);
1382 surface.mem = le64_to_cpu(sc->mem);
1383 surface.position = le32_to_cpu(sc->position);
1384 surface.stride = le32_to_cpu(sc->stride);
1385 surface.width = le32_to_cpu(sc->width);
1386 surface.type = le32_to_cpu(sc->type);
1387 surface.flags = le32_to_cpu(sc->flags);
1388 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1389 sc->format, sc->position);
1390 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1391 sc->flags);
1392
1393 if ((surface.stride & 0x3) != 0) {
1394 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1395 surface.stride);
1396 return;
1397 }
1398
1399 surface.mouse_mode = true1;
1400 surface.group_id = MEMSLOT_GROUP_GUEST1;
1401 if (loadvm) {
1402 surface.flags |= QXL_SURF_FLAG_KEEP_DATA(1 << 0);
1403 }
1404
1405 qxl->mode = QXL_MODE_NATIVE;
1406 qxl->cmdflags = 0;
1407 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1408
1409 if (async == QXL_SYNC) {
1410 qxl_create_guest_primary_complete(qxl);
1411 }
1412}
1413
1414/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1415 * done (in QXL_SYNC case), 0 otherwise. */
1416static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1417{
1418 if (d->mode == QXL_MODE_UNDEFINED) {
1419 return 0;
1420 }
1421 trace_qxl_destroy_primary(d->id);
1422 d->mode = QXL_MODE_UNDEFINED;
1423 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1424 qxl_spice_reset_cursor(d);
1425 return 1;
1426}
1427
1428static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1429{
1430 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1431 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1432 QXLMode *mode = d->modes->modes + modenr;
1433 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1434 QXLMemSlot slot = {
1435 .mem_start = start,
1436 .mem_end = end
1437 };
1438 QXLSurfaceCreate surface = {
1439 .width = mode->x_res,
1440 .height = mode->y_res,
1441 .stride = -mode->x_res * 4,
1442 .format = SPICE_SURFACE_FMT_32_xRGB,
1443 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA(1 << 0) : 0,
1444 .mouse_mode = true1,
1445 .mem = devmem + d->shadow_rom.draw_area_offset,
1446 };
1447
1448 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1449 devmem);
1450 if (!loadvm) {
1451 qxl_hard_reset(d, 0);
1452 }
1453
1454 d->guest_slots[0].slot = slot;
1455 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0)((qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0) ? (void) (0) :
__assert_fail ("qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c", 1455
, __PRETTY_FUNCTION__));
1456
1457 d->guest_primary.surface = surface;
1458 qxl_create_guest_primary(d, 0, QXL_SYNC);
1459
1460 d->mode = QXL_MODE_COMPAT;
1461 d->cmdflags = QXL_COMMAND_FLAG_COMPAT(1<<0);
1462 if (mode->bits == 16) {
1463 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP(2<<0);
1464 }
1465 d->shadow_rom.mode = cpu_to_le32(modenr);
1466 d->rom->mode = cpu_to_le32(modenr);
1467 qxl_rom_set_dirty(d);
1468}
1469
1470static void ioport_write(void *opaque, hwaddr addr,
1471 uint64_t val, unsigned size)
1472{
1473 PCIQXLDevice *d = opaque;
1474 uint32_t io_port = addr;
1475 qxl_async_io async = QXL_SYNC;
1476 uint32_t orig_io_port = io_port;
Value stored to 'orig_io_port' during its initialization is never read
1477
1478 if (d->guest_bug && io_port != QXL_IO_RESET) {
1479 return;
1480 }
1481
1482 if (d->revision <= QXL_REVISION_STABLE_V10 &&
1483 io_port > QXL_IO_FLUSH_RELEASE) {
1484 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1485 io_port, d->revision);
1486 return;
1487 }
1488
1489 switch (io_port) {
1490 case QXL_IO_RESET:
1491 case QXL_IO_SET_MODE:
1492 case QXL_IO_MEMSLOT_ADD:
1493 case QXL_IO_MEMSLOT_DEL:
1494 case QXL_IO_CREATE_PRIMARY:
1495 case QXL_IO_UPDATE_IRQ:
1496 case QXL_IO_LOG:
1497 case QXL_IO_MEMSLOT_ADD_ASYNC:
1498 case QXL_IO_CREATE_PRIMARY_ASYNC:
1499 break;
1500 default:
1501 if (d->mode != QXL_MODE_VGA) {
1502 break;
1503 }
1504 trace_qxl_io_unexpected_vga_mode(d->id,
1505 addr, val, io_port_to_string(io_port));
1506 /* be nice to buggy guest drivers */
1507 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1508 io_port < QXL_IO_RANGE_SIZE) {
1509 qxl_send_events(d, QXL_INTERRUPT_IO_CMD(1 << 2));
1510 }
1511 return;
1512 }
1513
1514 /* we change the io_port to avoid ifdeffery in the main switch */
1515 orig_io_port = io_port;
1516 switch (io_port) {
1517 case QXL_IO_UPDATE_AREA_ASYNC:
1518 io_port = QXL_IO_UPDATE_AREA;
1519 goto async_common;
1520 case QXL_IO_MEMSLOT_ADD_ASYNC:
1521 io_port = QXL_IO_MEMSLOT_ADD;
1522 goto async_common;
1523 case QXL_IO_CREATE_PRIMARY_ASYNC:
1524 io_port = QXL_IO_CREATE_PRIMARY;
1525 goto async_common;
1526 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1527 io_port = QXL_IO_DESTROY_PRIMARY;
1528 goto async_common;
1529 case QXL_IO_DESTROY_SURFACE_ASYNC:
1530 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1531 goto async_common;
1532 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1533 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1534 goto async_common;
1535 case QXL_IO_FLUSH_SURFACES_ASYNC:
1536 case QXL_IO_MONITORS_CONFIG_ASYNC:
1537async_common:
1538 async = QXL_ASYNC;
1539 qemu_mutex_lock(&d->async_lock);
1540 if (d->current_async != QXL_UNDEFINED_IO(4294967295U)) {
1541 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1542 io_port, d->current_async);
1543 qemu_mutex_unlock(&d->async_lock);
1544 return;
1545 }
1546 d->current_async = orig_io_port;
1547 qemu_mutex_unlock(&d->async_lock);
1548 break;
1549 default:
1550 break;
1551 }
1552 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1553 addr, io_port_to_string(addr),
1554 val, size, async);
1555
1556 switch (io_port) {
1557 case QXL_IO_UPDATE_AREA:
1558 {
1559 QXLCookie *cookie = NULL((void*)0);
1560 QXLRect update = d->ram->update_area;
1561
1562 if (d->ram->update_surface > d->ssd.num_surfaces) {
1563 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1564 d->ram->update_surface);
1565 break;
1566 }
1567 if (update.left >= update.right || update.top >= update.bottom ||
1568 update.left < 0 || update.top < 0) {
1569 qxl_set_guest_bug(d,
1570 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1571 update.left, update.top, update.right, update.bottom);
1572 break;
1573 }
1574 if (async == QXL_ASYNC) {
1575 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1576 QXL_IO_UPDATE_AREA_ASYNC);
1577 cookie->u.area = update;
1578 }
1579 qxl_spice_update_area(d, d->ram->update_surface,
1580 cookie ? &cookie->u.area : &update,
1581 NULL((void*)0), 0, 0, async, cookie);
1582 break;
1583 }
1584 case QXL_IO_NOTIFY_CMD:
1585 qemu_spice_wakeup(&d->ssd);
1586 break;
1587 case QXL_IO_NOTIFY_CURSOR:
1588 qemu_spice_wakeup(&d->ssd);
1589 break;
1590 case QXL_IO_UPDATE_IRQ:
1591 qxl_update_irq(d);
1592 break;
1593 case QXL_IO_NOTIFY_OOM:
1594 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)((&d->ram->release_ring)->cons == (&d->ram
->release_ring)->prod)) {
1595 break;
1596 }
1597 d->oom_running = 1;
1598 qxl_spice_oom(d);
1599 d->oom_running = 0;
1600 break;
1601 case QXL_IO_SET_MODE:
1602 qxl_set_mode(d, val, 0);
1603 break;
1604 case QXL_IO_LOG:
1605 trace_qxl_io_log(d->id, d->ram->log_buf);
1606 if (d->guestdebug) {
1607 fprintf(stderrstderr, "qxl/guest-%d: %" PRId64"l" "d" ": %s", d->id,
1608 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf);
1609 }
1610 break;
1611 case QXL_IO_RESET:
1612 qxl_hard_reset(d, 0);
1613 break;
1614 case QXL_IO_MEMSLOT_ADD:
1615 if (val >= NUM_MEMSLOTS8) {
1616 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1617 break;
1618 }
1619 if (d->guest_slots[val].active) {
1620 qxl_set_guest_bug(d,
1621 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1622 break;
1623 }
1624 d->guest_slots[val].slot = d->ram->mem_slot;
1625 qxl_add_memslot(d, val, 0, async);
1626 break;
1627 case QXL_IO_MEMSLOT_DEL:
1628 if (val >= NUM_MEMSLOTS8) {
1629 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1630 break;
1631 }
1632 qxl_del_memslot(d, val);
1633 break;
1634 case QXL_IO_CREATE_PRIMARY:
1635 if (val != 0) {
1636 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1637 async);
1638 goto cancel_async;
1639 }
1640 d->guest_primary.surface = d->ram->create_surface;
1641 qxl_create_guest_primary(d, 0, async);
1642 break;
1643 case QXL_IO_DESTROY_PRIMARY:
1644 if (val != 0) {
1645 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1646 async);
1647 goto cancel_async;
1648 }
1649 if (!qxl_destroy_primary(d, async)) {
1650 trace_qxl_io_destroy_primary_ignored(d->id,
1651 qxl_mode_to_string(d->mode));
1652 goto cancel_async;
1653 }
1654 break;
1655 case QXL_IO_DESTROY_SURFACE_WAIT:
1656 if (val >= d->ssd.num_surfaces) {
1657 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1658 "%" PRIu64"l" "u" " >= NUM_SURFACES", async, val);
1659 goto cancel_async;
1660 }
1661 qxl_spice_destroy_surface_wait(d, val, async);
1662 break;
1663 case QXL_IO_FLUSH_RELEASE: {
1664 QXLReleaseRing *ring = &d->ram->release_ring;
1665 if (ring->prod - ring->cons + 1 == ring->num_items) {
1666 fprintf(stderrstderr,
1667 "ERROR: no flush, full release ring [p%d,%dc]\n",
1668 ring->prod, ring->cons);
1669 }
1670 qxl_push_free_res(d, 1 /* flush */);
1671 break;
1672 }
1673 case QXL_IO_FLUSH_SURFACES_ASYNC:
1674 qxl_spice_flush_surfaces_async(d);
1675 break;
1676 case QXL_IO_DESTROY_ALL_SURFACES:
1677 d->mode = QXL_MODE_UNDEFINED;
1678 qxl_spice_destroy_surfaces(d, async);
1679 break;
1680 case QXL_IO_MONITORS_CONFIG_ASYNC:
1681 qxl_spice_monitors_config_async(d, 0);
1682 break;
1683 default:
1684 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1685 }
1686 return;
1687cancel_async:
1688 if (async) {
1689 qxl_send_events(d, QXL_INTERRUPT_IO_CMD(1 << 2));
1690 qemu_mutex_lock(&d->async_lock);
1691 d->current_async = QXL_UNDEFINED_IO(4294967295U);
1692 qemu_mutex_unlock(&d->async_lock);
1693 }
1694}
1695
1696static uint64_t ioport_read(void *opaque, hwaddr addr,
1697 unsigned size)
1698{
1699 PCIQXLDevice *qxl = opaque;
1700
1701 trace_qxl_io_read_unexpected(qxl->id);
1702 return 0xff;
1703}
1704
1705static const MemoryRegionOps qxl_io_ops = {
1706 .read = ioport_read,
1707 .write = ioport_write,
1708 .valid = {
1709 .min_access_size = 1,
1710 .max_access_size = 1,
1711 },
1712};
1713
1714static void qxl_update_irq_bh(void *opaque)
1715{
1716 PCIQXLDevice *d = opaque;
1717 qxl_update_irq(d);
1718}
1719
1720static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1721{
1722 uint32_t old_pending;
1723 uint32_t le_events = cpu_to_le32(events);
1724
1725 trace_qxl_send_events(d->id, events);
1726 if (!qemu_spice_display_is_running(&d->ssd)) {
1727 /* spice-server tracks guest running state and should not do this */
1728 fprintf(stderrstderr, "%s: spice-server bug: guest stopped, ignoring\n",
1729 __func__);
1730 trace_qxl_send_events_vm_stopped(d->id, events);
1731 return;
1732 }
1733 old_pending = atomic_fetch_or__sync_fetch_and_or(&d->ram->int_pending, le_events);
1734 if ((old_pending & le_events) == le_events) {
1735 return;
1736 }
1737 qemu_bh_schedule(d->update_irq);
1738}
1739
1740/* graphics console */
1741
1742static void qxl_hw_update(void *opaque)
1743{
1744 PCIQXLDevice *qxl = opaque;
1745 VGACommonState *vga = &qxl->vga;
1746
1747 switch (qxl->mode) {
1748 case QXL_MODE_VGA:
1749 vga->hw_ops->gfx_update(vga);
1750 break;
1751 case QXL_MODE_COMPAT:
1752 case QXL_MODE_NATIVE:
1753 qxl_render_update(qxl);
1754 break;
1755 default:
1756 break;
1757 }
1758}
1759
1760static void qxl_hw_invalidate(void *opaque)
1761{
1762 PCIQXLDevice *qxl = opaque;
1763 VGACommonState *vga = &qxl->vga;
1764
1765 if (qxl->mode == QXL_MODE_VGA) {
1766 vga->hw_ops->invalidate(vga);
1767 return;
1768 }
1769}
1770
1771static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1772{
1773 PCIQXLDevice *qxl = opaque;
1774 VGACommonState *vga = &qxl->vga;
1775
1776 if (qxl->mode == QXL_MODE_VGA) {
1777 vga->hw_ops->text_update(vga, chardata);
1778 return;
1779 }
1780}
1781
1782static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1783{
1784 uintptr_t vram_start;
1785 int i;
1786
1787 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1788 return;
1789 }
1790
1791 /* dirty the primary surface */
1792 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1793 qxl->shadow_rom.surface0_area_size);
1794
1795 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
1796
1797 /* dirty the off-screen surfaces */
1798 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1799 QXLSurfaceCmd *cmd;
1800 intptr_t surface_offset;
1801 int surface_size;
1802
1803 if (qxl->guest_surfaces.cmds[i] == 0) {
1804 continue;
1805 }
1806
1807 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1808 MEMSLOT_GROUP_GUEST1);
1809 assert(cmd)((cmd) ? (void) (0) : __assert_fail ("cmd", "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c"
, 1809, __PRETTY_FUNCTION__));
1810 assert(cmd->type == QXL_SURFACE_CMD_CREATE)((cmd->type == QXL_SURFACE_CMD_CREATE) ? (void) (0) : __assert_fail
("cmd->type == QXL_SURFACE_CMD_CREATE", "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c"
, 1810, __PRETTY_FUNCTION__));
1811 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1812 cmd->u.surface_create.data,
1813 MEMSLOT_GROUP_GUEST1);
1814 assert(surface_offset)((surface_offset) ? (void) (0) : __assert_fail ("surface_offset"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c", 1814
, __PRETTY_FUNCTION__));
1815 surface_offset -= vram_start;
1816 surface_size = cmd->u.surface_create.height *
1817 abs(cmd->u.surface_create.stride);
1818 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
1819 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1820 }
1821}
1822
1823static void qxl_vm_change_state_handler(void *opaque, int running,
1824 RunState state)
1825{
1826 PCIQXLDevice *qxl = opaque;
1827
1828 if (running) {
1829 /*
1830 * if qxl_send_events was called from spice server context before
1831 * migration ended, qxl_update_irq for these events might not have been
1832 * called
1833 */
1834 qxl_update_irq(qxl);
1835 } else {
1836 /* make sure surfaces are saved before migration */
1837 qxl_dirty_surfaces(qxl);
1838 }
1839}
1840
1841/* display change listener */
1842
1843static void display_update(DisplayChangeListener *dcl,
1844 int x, int y, int w, int h)
1845{
1846 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl)({ const typeof(((PCIQXLDevice *) 0)->ssd.dcl) *__mptr = (
dcl); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.dcl));});
1847
1848 if (qxl->mode == QXL_MODE_VGA) {
1849 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
1850 }
1851}
1852
1853static void display_switch(DisplayChangeListener *dcl,
1854 struct DisplaySurface *surface)
1855{
1856 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl)({ const typeof(((PCIQXLDevice *) 0)->ssd.dcl) *__mptr = (
dcl); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.dcl));});
1857
1858 qxl->ssd.ds = surface;
1859 if (qxl->mode == QXL_MODE_VGA) {
1860 qemu_spice_display_switch(&qxl->ssd, surface);
1861 }
1862}
1863
1864static void display_refresh(DisplayChangeListener *dcl)
1865{
1866 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl)({ const typeof(((PCIQXLDevice *) 0)->ssd.dcl) *__mptr = (
dcl); (PCIQXLDevice *) ((char *) __mptr - __builtin_offsetof(
PCIQXLDevice, ssd.dcl));});
1867
1868 if (qxl->mode == QXL_MODE_VGA) {
1869 qemu_spice_display_refresh(&qxl->ssd);
1870 } else {
1871 qemu_mutex_lock(&qxl->ssd.lock);
1872 qemu_spice_cursor_refresh_unlocked(&qxl->ssd);
1873 qemu_mutex_unlock(&qxl->ssd.lock);
1874 }
1875}
1876
1877static DisplayChangeListenerOps display_listener_ops = {
1878 .dpy_name = "spice/qxl",
1879 .dpy_gfx_update = display_update,
1880 .dpy_gfx_switch = display_switch,
1881 .dpy_refresh = display_refresh,
1882};
1883
1884static void qxl_init_ramsize(PCIQXLDevice *qxl)
1885{
1886 /* vga mode framebuffer / primary surface (bar 0, first part) */
1887 if (qxl->vgamem_size_mb < 8) {
1888 qxl->vgamem_size_mb = 8;
1889 }
1890 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
1891
1892 /* vga ram (bar 0, total) */
1893 if (qxl->ram_size_mb != -1) {
1894 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1895 }
1896 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
1897 qxl->vga.vram_size = qxl->vgamem_size * 2;
1898 }
1899
1900 /* vram32 (surfaces, 32bit, bar 1) */
1901 if (qxl->vram32_size_mb != -1) {
1902 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1903 }
1904 if (qxl->vram32_size < 4096) {
1905 qxl->vram32_size = 4096;
1906 }
1907
1908 /* vram (surfaces, 64bit, bar 4+5) */
1909 if (qxl->vram_size_mb != -1) {
1910 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1911 }
1912 if (qxl->vram_size < qxl->vram32_size) {
1913 qxl->vram_size = qxl->vram32_size;
1914 }
1915
1916 if (qxl->revision == 1) {
1917 qxl->vram32_size = 4096;
1918 qxl->vram_size = 4096;
1919 }
1920 qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1);
1921 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1922 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1);
1923 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1924}
1925
1926static int qxl_init_common(PCIQXLDevice *qxl)
1927{
1928 uint8_t* config = qxl->pci.config;
1929 uint32_t pci_device_rev;
1930 uint32_t io_size;
1931
1932 qxl->mode = QXL_MODE_UNDEFINED;
1933 qxl->generation = 1;
1934 qxl->num_memslots = NUM_MEMSLOTS8;
1935 qemu_mutex_init(&qxl->track_lock);
1936 qemu_mutex_init(&qxl->async_lock);
1937 qxl->current_async = QXL_UNDEFINED_IO(4294967295U);
1938 qxl->guest_bug = 0;
1939
1940 switch (qxl->revision) {
1941 case 1: /* spice 0.4 -- qxl-1 */
1942 pci_device_rev = QXL_REVISION_STABLE_V04;
1943 io_size = 8;
1944 break;
1945 case 2: /* spice 0.6 -- qxl-2 */
1946 pci_device_rev = QXL_REVISION_STABLE_V06;
1947 io_size = 16;
1948 break;
1949 case 3: /* qxl-3 */
1950 pci_device_rev = QXL_REVISION_STABLE_V10;
1951 io_size = 32; /* PCI region size must be pow2 */
1952 break;
1953 case 4: /* qxl-4 */
1954 pci_device_rev = QXL_REVISION_STABLE_V12;
1955 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1956 break;
1957 default:
1958 error_report("Invalid revision %d for qxl device (max %d)",
1959 qxl->revision, QXL_DEFAULT_REVISIONQXL_REVISION_STABLE_V12);
1960 return -1;
1961 }
1962
1963 pci_set_byte(&config[PCI_REVISION_ID0x08], pci_device_rev);
1964 pci_set_byte(&config[PCI_INTERRUPT_PIN0x3d], 1);
1965
1966 qxl->rom_size = qxl_rom_size();
1967 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl)((Object *)(qxl)), "qxl.vrom",
1968 qxl->rom_size);
1969 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
1970 init_qxl_rom(qxl);
1971 init_qxl_ram(qxl);
1972
1973 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces)((QXLPHYSICAL *) g_malloc0_n ((qxl->ssd.num_surfaces), sizeof
(QXLPHYSICAL)));
1974 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl)((Object *)(qxl)), "qxl.vram",
1975 qxl->vram_size);
1976 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
1977 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl)((Object *)(qxl)), "qxl.vram32",
1978 &qxl->vram_bar, 0, qxl->vram32_size);
1979
1980 memory_region_init_io(&qxl->io_bar, OBJECT(qxl)((Object *)(qxl)), &qxl_io_ops, qxl,
1981 "qxl-ioports", io_size);
1982 if (qxl->id == 0) {
1983 vga_dirty_log_start(&qxl->vga);
1984 }
1985 memory_region_set_flush_coalesced(&qxl->io_bar);
1986
1987
1988 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1989 PCI_BASE_ADDRESS_SPACE_IO0x01, &qxl->io_bar);
1990
1991 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1992 PCI_BASE_ADDRESS_SPACE_MEMORY0x00, &qxl->rom_bar);
1993
1994 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1995 PCI_BASE_ADDRESS_SPACE_MEMORY0x00, &qxl->vga.vram);
1996
1997 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
1998 PCI_BASE_ADDRESS_SPACE_MEMORY0x00, &qxl->vram32_bar);
1999
2000 if (qxl->vram32_size < qxl->vram_size) {
2001 /*
2002 * Make the 64bit vram bar show up only in case it is
2003 * configured to be larger than the 32bit vram bar.
2004 */
2005 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX4,
2006 PCI_BASE_ADDRESS_SPACE_MEMORY0x00 |
2007 PCI_BASE_ADDRESS_MEM_TYPE_640x04 |
2008 PCI_BASE_ADDRESS_MEM_PREFETCH0x08,
2009 &qxl->vram_bar);
2010 }
2011
2012 /* print pci bar details */
2013 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",do { if (qxl->debug >= 1) { fprintf(stderr, "qxl-%d: ",
qxl->id); fprintf(stderr, "ram/%s: %d MB [region 0]\n", qxl
->id == 0 ? "pri" : "sec", qxl->vga.vram_size / (1024*1024
)); } } while (0)
2014 qxl->id == 0 ? "pri" : "sec",do { if (qxl->debug >= 1) { fprintf(stderr, "qxl-%d: ",
qxl->id); fprintf(stderr, "ram/%s: %d MB [region 0]\n", qxl
->id == 0 ? "pri" : "sec", qxl->vga.vram_size / (1024*1024
)); } } while (0)
2015 qxl->vga.vram_size / (1024*1024))do { if (qxl->debug >= 1) { fprintf(stderr, "qxl-%d: ",
qxl->id); fprintf(stderr, "ram/%s: %d MB [region 0]\n", qxl
->id == 0 ? "pri" : "sec", qxl->vga.vram_size / (1024*1024
)); } } while (0);
2016 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",do { if (qxl->debug >= 1) { fprintf(stderr, "qxl-%d: ",
qxl->id); fprintf(stderr, "vram/32: %d MB [region 1]\n", qxl
->vram32_size / (1024*1024)); } } while (0)
2017 qxl->vram32_size / (1024*1024))do { if (qxl->debug >= 1) { fprintf(stderr, "qxl-%d: ",
qxl->id); fprintf(stderr, "vram/32: %d MB [region 1]\n", qxl
->vram32_size / (1024*1024)); } } while (0);
2018 dprint(qxl, 1, "vram/64: %d MB %s\n",do { if (qxl->debug >= 1) { fprintf(stderr, "qxl-%d: ",
qxl->id); fprintf(stderr, "vram/64: %d MB %s\n", qxl->
vram_size / (1024*1024), qxl->vram32_size < qxl->vram_size
? "[region 4]" : "[unmapped]"); } } while (0)
2019 qxl->vram_size / (1024*1024),do { if (qxl->debug >= 1) { fprintf(stderr, "qxl-%d: ",
qxl->id); fprintf(stderr, "vram/64: %d MB %s\n", qxl->
vram_size / (1024*1024), qxl->vram32_size < qxl->vram_size
? "[region 4]" : "[unmapped]"); } } while (0)
2020 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]")do { if (qxl->debug >= 1) { fprintf(stderr, "qxl-%d: ",
qxl->id); fprintf(stderr, "vram/64: %d MB %s\n", qxl->
vram_size / (1024*1024), qxl->vram32_size < qxl->vram_size
? "[region 4]" : "[unmapped]"); } } while (0);
2021
2022 qxl->ssd.qxl.base.sif = &qxl_interface.base;
2023 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
2024 error_report("qxl interface %d.%d not supported by spice-server",
2025 SPICE_INTERFACE_QXL_MAJOR3, SPICE_INTERFACE_QXL_MINOR3);
2026 return -1;
2027 }
2028 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2029
2030 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
2031 qxl_reset_state(qxl);
2032
2033 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2034
2035 return 0;
2036}
2037
2038static const GraphicHwOps qxl_ops = {
2039 .invalidate = qxl_hw_invalidate,
2040 .gfx_update = qxl_hw_update,
2041 .text_update = qxl_hw_text_update,
2042};
2043
2044static int qxl_init_primary(PCIDevice *dev)
2045{
2046 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(PCIQXLDevice, pci)]; ({ const typeof(((
PCIQXLDevice *) 0)->pci) *__mptr = (dev); (PCIQXLDevice *)
((char *) __mptr - __builtin_offsetof(PCIQXLDevice, pci));})
;}));
2047 VGACommonState *vga = &qxl->vga;
2048 PortioList *qxl_vga_port_list = g_new(PortioList, 1)((PortioList *) g_malloc_n ((1), sizeof (PortioList)));
2049 int rc;
2050
2051 qxl->id = 0;
2052 qxl_init_ramsize(qxl);
2053 vga->vram_size_mb = qxl->vga.vram_size >> 20;
2054 vga_common_init(vga, OBJECT(dev)((Object *)(dev)));
2055 vga_init(vga, OBJECT(dev)((Object *)(dev)),
2056 pci_address_space(dev), pci_address_space_io(dev), false0);
2057 portio_list_init(qxl_vga_port_list, OBJECT(dev)((Object *)(dev)), qxl_vga_portio_list,
2058 vga, "vga");
2059 portio_list_set_flush_coalesced(qxl_vga_port_list);
2060 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
2061
2062 vga->con = graphic_console_init(DEVICE(dev)((DeviceState *)object_dynamic_cast_assert(((Object *)((dev))
), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c"
, 2062, __func__)), &qxl_ops, qxl);
2063 qemu_spice_display_init_common(&qxl->ssd);
2064
2065 rc = qxl_init_common(qxl);
2066 if (rc != 0) {
2067 return rc;
2068 }
2069
2070 qxl->ssd.dcl.ops = &display_listener_ops;
2071 qxl->ssd.dcl.con = vga->con;
2072 register_displaychangelistener(&qxl->ssd.dcl);
2073 return rc;
2074}
2075
2076static int qxl_init_secondary(PCIDevice *dev)
2077{
2078 static int device_id = 1;
2079 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(PCIQXLDevice, pci)]; ({ const typeof(((
PCIQXLDevice *) 0)->pci) *__mptr = (dev); (PCIQXLDevice *)
((char *) __mptr - __builtin_offsetof(PCIQXLDevice, pci));})
;}));
2080
2081 qxl->id = device_id++;
2082 qxl_init_ramsize(qxl);
2083 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev)((Object *)(dev)), "qxl.vgavram",
2084 qxl->vga.vram_size);
2085 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
2086 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2087 qxl->vga.con = graphic_console_init(DEVICE(dev)((DeviceState *)object_dynamic_cast_assert(((Object *)((dev))
), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c"
, 2087, __func__)), &qxl_ops, qxl);
2088
2089 return qxl_init_common(qxl);
2090}
2091
2092static void qxl_pre_save(void *opaque)
2093{
2094 PCIQXLDevice* d = opaque;
2095 uint8_t *ram_start = d->vga.vram_ptr;
2096
2097 trace_qxl_pre_save(d->id);
2098 if (d->last_release == NULL((void*)0)) {
2099 d->last_release_offset = 0;
2100 } else {
2101 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2102 }
2103 assert(d->last_release_offset < d->vga.vram_size)((d->last_release_offset < d->vga.vram_size) ? (void
) (0) : __assert_fail ("d->last_release_offset < d->vga.vram_size"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c", 2103
, __PRETTY_FUNCTION__));
2104}
2105
2106static int qxl_pre_load(void *opaque)
2107{
2108 PCIQXLDevice* d = opaque;
2109
2110 trace_qxl_pre_load(d->id);
2111 qxl_hard_reset(d, 1);
2112 qxl_exit_vga_mode(d);
2113 return 0;
2114}
2115
2116static void qxl_create_memslots(PCIQXLDevice *d)
2117{
2118 int i;
2119
2120 for (i = 0; i < NUM_MEMSLOTS8; i++) {
2121 if (!d->guest_slots[i].active) {
2122 continue;
2123 }
2124 qxl_add_memslot(d, i, 0, QXL_SYNC);
2125 }
2126}
2127
2128static int qxl_post_load(void *opaque, int version)
2129{
2130 PCIQXLDevice* d = opaque;
2131 uint8_t *ram_start = d->vga.vram_ptr;
2132 QXLCommandExt *cmds;
2133 int in, out, newmode;
2134
2135 assert(d->last_release_offset < d->vga.vram_size)((d->last_release_offset < d->vga.vram_size) ? (void
) (0) : __assert_fail ("d->last_release_offset < d->vga.vram_size"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c", 2135
, __PRETTY_FUNCTION__));
2136 if (d->last_release_offset == 0) {
2137 d->last_release = NULL((void*)0);
2138 } else {
2139 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2140 }
2141
2142 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2143
2144 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2145 newmode = d->mode;
2146 d->mode = QXL_MODE_UNDEFINED;
2147
2148 switch (newmode) {
2149 case QXL_MODE_UNDEFINED:
2150 qxl_create_memslots(d);
2151 break;
2152 case QXL_MODE_VGA:
2153 qxl_create_memslots(d);
2154 qxl_enter_vga_mode(d);
2155 break;
2156 case QXL_MODE_NATIVE:
2157 qxl_create_memslots(d);
2158 qxl_create_guest_primary(d, 1, QXL_SYNC);
2159
2160 /* replay surface-create and cursor-set commands */
2161 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1));
2162 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2163 if (d->guest_surfaces.cmds[in] == 0) {
2164 continue;
2165 }
2166 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2167 cmds[out].cmd.type = QXL_CMD_SURFACE;
2168 cmds[out].group_id = MEMSLOT_GROUP_GUEST1;
2169 out++;
2170 }
2171 if (d->guest_cursor) {
2172 cmds[out].cmd.data = d->guest_cursor;
2173 cmds[out].cmd.type = QXL_CMD_CURSOR;
2174 cmds[out].group_id = MEMSLOT_GROUP_GUEST1;
2175 out++;
2176 }
2177 qxl_spice_loadvm_commands(d, cmds, out);
2178 g_free(cmds);
2179 if (d->guest_monitors_config) {
2180 qxl_spice_monitors_config_async(d, 1);
2181 }
2182 break;
2183 case QXL_MODE_COMPAT:
2184 /* note: no need to call qxl_create_memslots, qxl_set_mode
2185 * creates the mem slot. */
2186 qxl_set_mode(d, d->shadow_rom.mode, 1);
2187 break;
2188 }
2189 return 0;
2190}
2191
2192#define QXL_SAVE_VERSION21 21
2193
2194static bool_Bool qxl_monitors_config_needed(void *opaque)
2195{
2196 PCIQXLDevice *qxl = opaque;
2197
2198 return qxl->guest_monitors_config != 0;
2199}
2200
2201
2202static VMStateDescription qxl_memslot = {
2203 .name = "qxl-memslot",
2204 .version_id = QXL_SAVE_VERSION21,
2205 .minimum_version_id = QXL_SAVE_VERSION21,
2206 .fields = (VMStateField[]) {
2207 VMSTATE_UINT64(slot.mem_start, struct guest_slots){ .name = ("slot.mem_start"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint64_t), .info = &(vmstate_info_uint64
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(struct guest_slots
, slot.mem_start) + ((uint64_t*)0 - (typeof(((struct guest_slots
*)0)->slot.mem_start)*)0)), },
2208 VMSTATE_UINT64(slot.mem_end, struct guest_slots){ .name = ("slot.mem_end"), .version_id = (0), .field_exists =
(((void*)0)), .size = sizeof(uint64_t), .info = &(vmstate_info_uint64
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(struct guest_slots
, slot.mem_end) + ((uint64_t*)0 - (typeof(((struct guest_slots
*)0)->slot.mem_end)*)0)), },
2209 VMSTATE_UINT32(active, struct guest_slots){ .name = ("active"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(struct guest_slots
, active) + ((uint32_t*)0 - (typeof(((struct guest_slots *)0)
->active)*)0)), },
2210 VMSTATE_END_OF_LIST(){}
2211 }
2212};
2213
2214static VMStateDescription qxl_surface = {
2215 .name = "qxl-surface",
2216 .version_id = QXL_SAVE_VERSION21,
2217 .minimum_version_id = QXL_SAVE_VERSION21,
2218 .fields = (VMStateField[]) {
2219 VMSTATE_UINT32(width, QXLSurfaceCreate){ .name = ("width"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(QXLSurfaceCreate
, width) + ((uint32_t*)0 - (typeof(((QXLSurfaceCreate *)0)->
width)*)0)), },
2220 VMSTATE_UINT32(height, QXLSurfaceCreate){ .name = ("height"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(QXLSurfaceCreate
, height) + ((uint32_t*)0 - (typeof(((QXLSurfaceCreate *)0)->
height)*)0)), },
2221 VMSTATE_INT32(stride, QXLSurfaceCreate){ .name = ("stride"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(int32_t), .info = &(vmstate_info_int32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(QXLSurfaceCreate
, stride) + ((int32_t*)0 - (typeof(((QXLSurfaceCreate *)0)->
stride)*)0)), },
2222 VMSTATE_UINT32(format, QXLSurfaceCreate){ .name = ("format"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(QXLSurfaceCreate
, format) + ((uint32_t*)0 - (typeof(((QXLSurfaceCreate *)0)->
format)*)0)), },
2223 VMSTATE_UINT32(position, QXLSurfaceCreate){ .name = ("position"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(QXLSurfaceCreate
, position) + ((uint32_t*)0 - (typeof(((QXLSurfaceCreate *)0)
->position)*)0)), },
2224 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate){ .name = ("mouse_mode"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(QXLSurfaceCreate
, mouse_mode) + ((uint32_t*)0 - (typeof(((QXLSurfaceCreate *)
0)->mouse_mode)*)0)), },
2225 VMSTATE_UINT32(flags, QXLSurfaceCreate){ .name = ("flags"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(QXLSurfaceCreate
, flags) + ((uint32_t*)0 - (typeof(((QXLSurfaceCreate *)0)->
flags)*)0)), },
2226 VMSTATE_UINT32(type, QXLSurfaceCreate){ .name = ("type"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(QXLSurfaceCreate
, type) + ((uint32_t*)0 - (typeof(((QXLSurfaceCreate *)0)->
type)*)0)), },
2227 VMSTATE_UINT64(mem, QXLSurfaceCreate){ .name = ("mem"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint64_t), .info = &(vmstate_info_uint64
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(QXLSurfaceCreate
, mem) + ((uint64_t*)0 - (typeof(((QXLSurfaceCreate *)0)->
mem)*)0)), },
2228 VMSTATE_END_OF_LIST(){}
2229 }
2230};
2231
2232static VMStateDescription qxl_vmstate_monitors_config = {
2233 .name = "qxl/monitors-config",
2234 .version_id = 1,
2235 .minimum_version_id = 1,
2236 .fields = (VMStateField[]) {
2237 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice){ .name = ("guest_monitors_config"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint64_t), .info = &(vmstate_info_uint64
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(PCIQXLDevice
, guest_monitors_config) + ((uint64_t*)0 - (typeof(((PCIQXLDevice
*)0)->guest_monitors_config)*)0)), },
2238 VMSTATE_END_OF_LIST(){}
2239 },
2240};
2241
2242static VMStateDescription qxl_vmstate = {
2243 .name = "qxl",
2244 .version_id = QXL_SAVE_VERSION21,
2245 .minimum_version_id = QXL_SAVE_VERSION21,
2246 .pre_save = qxl_pre_save,
2247 .pre_load = qxl_pre_load,
2248 .post_load = qxl_post_load,
2249 .fields = (VMStateField[]) {
2250 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice){ .name = ("pci"), .size = sizeof(PCIDevice), .vmsd = &vmstate_pci_device
, .flags = VMS_STRUCT, .offset = (__builtin_offsetof(PCIQXLDevice
, pci) + ((PCIDevice*)0 - (typeof(((PCIQXLDevice *)0)->pci
)*)0)), },
2251 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState){ .name = ("vga"), .version_id = (0), .field_exists = (((void
*)0)), .vmsd = &(vmstate_vga_common), .size = sizeof(VGACommonState
), .flags = VMS_STRUCT, .offset = (__builtin_offsetof(PCIQXLDevice
, vga) + ((VGACommonState*)0 - (typeof(((PCIQXLDevice *)0)->
vga)*)0)), },
2252 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice){ .name = ("shadow_rom.mode"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(PCIQXLDevice
, shadow_rom.mode) + ((uint32_t*)0 - (typeof(((PCIQXLDevice *
)0)->shadow_rom.mode)*)0)), },
2253 VMSTATE_UINT32(num_free_res, PCIQXLDevice){ .name = ("num_free_res"), .version_id = (0), .field_exists =
(((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(PCIQXLDevice
, num_free_res) + ((uint32_t*)0 - (typeof(((PCIQXLDevice *)0)
->num_free_res)*)0)), },
2254 VMSTATE_UINT32(last_release_offset, PCIQXLDevice){ .name = ("last_release_offset"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(PCIQXLDevice
, last_release_offset) + ((uint32_t*)0 - (typeof(((PCIQXLDevice
*)0)->last_release_offset)*)0)), },
2255 VMSTATE_UINT32(mode, PCIQXLDevice){ .name = ("mode"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(PCIQXLDevice
, mode) + ((uint32_t*)0 - (typeof(((PCIQXLDevice *)0)->mode
)*)0)), },
2256 VMSTATE_UINT32(ssd.unique, PCIQXLDevice){ .name = ("ssd.unique"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(PCIQXLDevice
, ssd.unique) + ((uint32_t*)0 - (typeof(((PCIQXLDevice *)0)->
ssd.unique)*)0)), },
2257 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice){ .name = ("num_memslots"), .version_id = (0), .field_exists =
(((void*)0)), .size = sizeof(int32_t), .info = &(vmstate_info_int32_equal
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(PCIQXLDevice
, num_memslots) + ((int32_t*)0 - (typeof(((PCIQXLDevice *)0)->
num_memslots)*)0)), },
2258 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,{ .name = ("guest_slots"), .num = (8), .field_exists = (((void
*)0)), .version_id = (0), .vmsd = &(qxl_memslot), .size =
sizeof(struct guest_slots), .flags = VMS_STRUCT|VMS_ARRAY, .
offset = (__builtin_offsetof(PCIQXLDevice, guest_slots) + ((struct
guest_slots(*)[8])0 - (typeof(((PCIQXLDevice *)0)->guest_slots
)*)0)),}
2259 qxl_memslot, struct guest_slots){ .name = ("guest_slots"), .num = (8), .field_exists = (((void
*)0)), .version_id = (0), .vmsd = &(qxl_memslot), .size =
sizeof(struct guest_slots), .flags = VMS_STRUCT|VMS_ARRAY, .
offset = (__builtin_offsetof(PCIQXLDevice, guest_slots) + ((struct
guest_slots(*)[8])0 - (typeof(((PCIQXLDevice *)0)->guest_slots
)*)0)),},
2260 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,{ .name = ("guest_primary.surface"), .version_id = (0), .field_exists
= (((void*)0)), .vmsd = &(qxl_surface), .size = sizeof(QXLSurfaceCreate
), .flags = VMS_STRUCT, .offset = (__builtin_offsetof(PCIQXLDevice
, guest_primary.surface) + ((QXLSurfaceCreate*)0 - (typeof(((
PCIQXLDevice *)0)->guest_primary.surface)*)0)), }
2261 qxl_surface, QXLSurfaceCreate){ .name = ("guest_primary.surface"), .version_id = (0), .field_exists
= (((void*)0)), .vmsd = &(qxl_surface), .size = sizeof(QXLSurfaceCreate
), .flags = VMS_STRUCT, .offset = (__builtin_offsetof(PCIQXLDevice
, guest_primary.surface) + ((QXLSurfaceCreate*)0 - (typeof(((
PCIQXLDevice *)0)->guest_primary.surface)*)0)), },
2262 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice){ .name = ("ssd.num_surfaces"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(int32_t), .info = &(vmstate_info_int32_equal
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(PCIQXLDevice
, ssd.num_surfaces) + ((int32_t*)0 - (typeof(((PCIQXLDevice *
)0)->ssd.num_surfaces)*)0)), },
2263 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,{ .name = ("guest_surfaces.cmds"), .version_id = (0), .num_offset
= (__builtin_offsetof(PCIQXLDevice, ssd.num_surfaces) + ((int32_t
*)0 - (typeof(((PCIQXLDevice *)0)->ssd.num_surfaces)*)0)),
.info = &(vmstate_info_uint64), .size = sizeof(uint64_t)
, .flags = VMS_VARRAY_INT32|VMS_POINTER, .offset = (__builtin_offsetof
(PCIQXLDevice, guest_surfaces.cmds) + ((uint64_t**)0 - (typeof
(((PCIQXLDevice *)0)->guest_surfaces.cmds)*)0)), }
2264 ssd.num_surfaces, 0,{ .name = ("guest_surfaces.cmds"), .version_id = (0), .num_offset
= (__builtin_offsetof(PCIQXLDevice, ssd.num_surfaces) + ((int32_t
*)0 - (typeof(((PCIQXLDevice *)0)->ssd.num_surfaces)*)0)),
.info = &(vmstate_info_uint64), .size = sizeof(uint64_t)
, .flags = VMS_VARRAY_INT32|VMS_POINTER, .offset = (__builtin_offsetof
(PCIQXLDevice, guest_surfaces.cmds) + ((uint64_t**)0 - (typeof
(((PCIQXLDevice *)0)->guest_surfaces.cmds)*)0)), }
2265 vmstate_info_uint64, uint64_t){ .name = ("guest_surfaces.cmds"), .version_id = (0), .num_offset
= (__builtin_offsetof(PCIQXLDevice, ssd.num_surfaces) + ((int32_t
*)0 - (typeof(((PCIQXLDevice *)0)->ssd.num_surfaces)*)0)),
.info = &(vmstate_info_uint64), .size = sizeof(uint64_t)
, .flags = VMS_VARRAY_INT32|VMS_POINTER, .offset = (__builtin_offsetof
(PCIQXLDevice, guest_surfaces.cmds) + ((uint64_t**)0 - (typeof
(((PCIQXLDevice *)0)->guest_surfaces.cmds)*)0)), },
2266 VMSTATE_UINT64(guest_cursor, PCIQXLDevice){ .name = ("guest_cursor"), .version_id = (0), .field_exists =
(((void*)0)), .size = sizeof(uint64_t), .info = &(vmstate_info_uint64
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(PCIQXLDevice
, guest_cursor) + ((uint64_t*)0 - (typeof(((PCIQXLDevice *)0)
->guest_cursor)*)0)), },
2267 VMSTATE_END_OF_LIST(){}
2268 },
2269 .subsections = (VMStateSubsection[]) {
2270 {
2271 .vmsd = &qxl_vmstate_monitors_config,
2272 .needed = qxl_monitors_config_needed,
2273 }, {
2274 /* empty */
2275 }
2276 }
2277};
2278
2279static Property qxl_properties[] = {
2280 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,{ .name = ("ram_size"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(PCIQXLDevice, vga.vram_size) + ((uint32_t
*)0 - (typeof(((PCIQXLDevice *)0)->vga.vram_size)*)0), .qtype
= QTYPE_QINT, .defval = (uint32_t)64 * 1024 * 1024, }
2281 64 * 1024 * 1024){ .name = ("ram_size"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(PCIQXLDevice, vga.vram_size) + ((uint32_t
*)0 - (typeof(((PCIQXLDevice *)0)->vga.vram_size)*)0), .qtype
= QTYPE_QINT, .defval = (uint32_t)64 * 1024 * 1024, },
2282 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,{ .name = ("vram_size"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(PCIQXLDevice, vram32_size) + ((uint32_t
*)0 - (typeof(((PCIQXLDevice *)0)->vram32_size)*)0), .qtype
= QTYPE_QINT, .defval = (uint32_t)64 * 1024 * 1024, }
2283 64 * 1024 * 1024){ .name = ("vram_size"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(PCIQXLDevice, vram32_size) + ((uint32_t
*)0 - (typeof(((PCIQXLDevice *)0)->vram32_size)*)0), .qtype
= QTYPE_QINT, .defval = (uint32_t)64 * 1024 * 1024, },
2284 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,{ .name = ("revision"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(PCIQXLDevice, revision) + ((uint32_t*)0
- (typeof(((PCIQXLDevice *)0)->revision)*)0), .qtype = QTYPE_QINT
, .defval = (uint32_t)QXL_REVISION_STABLE_V12, }
2285 QXL_DEFAULT_REVISION){ .name = ("revision"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(PCIQXLDevice, revision) + ((uint32_t*)0
- (typeof(((PCIQXLDevice *)0)->revision)*)0), .qtype = QTYPE_QINT
, .defval = (uint32_t)QXL_REVISION_STABLE_V12, },
2286 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0){ .name = ("debug"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(PCIQXLDevice, debug) + ((uint32_t*)0 - (
typeof(((PCIQXLDevice *)0)->debug)*)0), .qtype = QTYPE_QINT
, .defval = (uint32_t)0, },
2287 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0){ .name = ("guestdebug"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(PCIQXLDevice, guestdebug) + ((uint32_t*
)0 - (typeof(((PCIQXLDevice *)0)->guestdebug)*)0), .qtype =
QTYPE_QINT, .defval = (uint32_t)0, },
2288 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0){ .name = ("cmdlog"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(PCIQXLDevice, cmdlog) + ((uint32_t*)0 -
(typeof(((PCIQXLDevice *)0)->cmdlog)*)0), .qtype = QTYPE_QINT
, .defval = (uint32_t)0, },
2289 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1){ .name = ("ram_size_mb"), .info = &(qdev_prop_uint32), .
offset = __builtin_offsetof(PCIQXLDevice, ram_size_mb) + ((uint32_t
*)0 - (typeof(((PCIQXLDevice *)0)->ram_size_mb)*)0), .qtype
= QTYPE_QINT, .defval = (uint32_t)-1, },
2290 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1){ .name = ("vram_size_mb"), .info = &(qdev_prop_uint32), .
offset = __builtin_offsetof(PCIQXLDevice, vram32_size_mb) + (
(uint32_t*)0 - (typeof(((PCIQXLDevice *)0)->vram32_size_mb
)*)0), .qtype = QTYPE_QINT, .defval = (uint32_t)-1, },
2291 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1){ .name = ("vram64_size_mb"), .info = &(qdev_prop_uint32)
, .offset = __builtin_offsetof(PCIQXLDevice, vram_size_mb) + (
(uint32_t*)0 - (typeof(((PCIQXLDevice *)0)->vram_size_mb)*
)0), .qtype = QTYPE_QINT, .defval = (uint32_t)-1, },
2292 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16){ .name = ("vgamem_mb"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(PCIQXLDevice, vgamem_size_mb) + ((uint32_t
*)0 - (typeof(((PCIQXLDevice *)0)->vgamem_size_mb)*)0), .qtype
= QTYPE_QINT, .defval = (uint32_t)16, },
2293 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024){ .name = ("surfaces"), .info = &(qdev_prop_int32), .offset
= __builtin_offsetof(PCIQXLDevice, ssd.num_surfaces) + ((int32_t
*)0 - (typeof(((PCIQXLDevice *)0)->ssd.num_surfaces)*)0), .
qtype = QTYPE_QINT, .defval = (int32_t)1024, },
2294 DEFINE_PROP_END_OF_LIST(){},
2295};
2296
2297static void qxl_primary_class_init(ObjectClass *klass, void *data)
2298{
2299 DeviceClass *dc = DEVICE_CLASS(klass)((DeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c"
, 2299, __func__));
2300 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass)((PCIDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c"
, 2300, __func__));
2301
2302 k->no_hotplug = 1;
2303 k->init = qxl_init_primary;
2304 k->romfile = "vgabios-qxl.bin";
2305 k->vendor_id = REDHAT_PCI_VENDOR_ID0x1b36;
2306 k->device_id = QXL_DEVICE_ID_STABLE0x0100;
2307 k->class_id = PCI_CLASS_DISPLAY_VGA0x0300;
2308 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2309 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2310 dc->reset = qxl_reset_handler;
2311 dc->vmsd = &qxl_vmstate;
2312 dc->props = qxl_properties;
2313}
2314
2315static const TypeInfo qxl_primary_info = {
2316 .name = "qxl-vga",
2317 .parent = TYPE_PCI_DEVICE"pci-device",
2318 .instance_size = sizeof(PCIQXLDevice),
2319 .class_init = qxl_primary_class_init,
2320};
2321
2322static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2323{
2324 DeviceClass *dc = DEVICE_CLASS(klass)((DeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c"
, 2324, __func__));
2325 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass)((PCIDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/qxl.c"
, 2325, __func__));
2326
2327 k->init = qxl_init_secondary;
2328 k->vendor_id = REDHAT_PCI_VENDOR_ID0x1b36;
2329 k->device_id = QXL_DEVICE_ID_STABLE0x0100;
2330 k->class_id = PCI_CLASS_DISPLAY_OTHER0x0380;
2331 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2332 dc->desc = "Spice QXL GPU (secondary)";
2333 dc->reset = qxl_reset_handler;
2334 dc->vmsd = &qxl_vmstate;
2335 dc->props = qxl_properties;
2336}
2337
2338static const TypeInfo qxl_secondary_info = {
2339 .name = "qxl",
2340 .parent = TYPE_PCI_DEVICE"pci-device",
2341 .instance_size = sizeof(PCIQXLDevice),
2342 .class_init = qxl_secondary_class_init,
2343};
2344
2345static void qxl_register_types(void)
2346{
2347 type_register_static(&qxl_primary_info);
2348 type_register_static(&qxl_secondary_info);
2349}
2350
2351type_init(qxl_register_types)static void __attribute__((constructor)) do_qemu_init_qxl_register_types
(void) { register_module_init(qxl_register_types, MODULE_INIT_QOM
); }