Bug Summary

File:hw/isa/vt82c686.c
Location:line 71, column 13
Description:Value stored to 'can_write' is never read

Annotated Source Code

1/*
2 * VT82C686B south bridge support
3 *
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13#include "hw/hw.h"
14#include "hw/i386/pc.h"
15#include "hw/isa/vt82c686.h"
16#include "hw/i2c/i2c.h"
17#include "hw/i2c/smbus.h"
18#include "hw/pci/pci.h"
19#include "hw/isa/isa.h"
20#include "hw/sysbus.h"
21#include "hw/mips/mips.h"
22#include "hw/isa/apm.h"
23#include "hw/acpi/acpi.h"
24#include "hw/i2c/pm_smbus.h"
25#include "sysemu/sysemu.h"
26#include "qemu/timer.h"
27#include "exec/address-spaces.h"
28
29//#define DEBUG_VT82C686B
30
31#ifdef DEBUG_VT82C686B
32#define DPRINTF(fmt, ...) fprintf(stderrstderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
33#else
34#define DPRINTF(fmt, ...)
35#endif
36
37typedef struct SuperIOConfig
38{
39 uint8_t config[0xff];
40 uint8_t index;
41 uint8_t data;
42} SuperIOConfig;
43
44typedef struct VT82C686BState {
45 PCIDevice dev;
46 MemoryRegion superio;
47 SuperIOConfig superio_conf;
48} VT82C686BState;
49
50static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data,
51 unsigned size)
52{
53 int can_write;
54 SuperIOConfig *superio_conf = opaque;
55
56 DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
57 if (addr == 0x3f0) {
58 superio_conf->index = data & 0xff;
59 } else {
60 /* 0x3f1 */
61 switch (superio_conf->index) {
62 case 0x00 ... 0xdf:
63 case 0xe4:
64 case 0xe5:
65 case 0xe9 ... 0xed:
66 case 0xf3:
67 case 0xf5:
68 case 0xf7:
69 case 0xf9 ... 0xfb:
70 case 0xfd ... 0xff:
71 can_write = 0;
Value stored to 'can_write' is never read
72 break;
73 default:
74 can_write = 1;
75
76 if (can_write) {
77 switch (superio_conf->index) {
78 case 0xe7:
79 if ((data & 0xff) != 0xfe) {
80 DPRINTF("chage uart 1 base. unsupported yet\n");
81 }
82 break;
83 case 0xe8:
84 if ((data & 0xff) != 0xbe) {
85 DPRINTF("chage uart 2 base. unsupported yet\n");
86 }
87 break;
88
89 default:
90 superio_conf->config[superio_conf->index] = data & 0xff;
91 }
92 }
93 }
94 superio_conf->config[superio_conf->index] = data & 0xff;
95 }
96}
97
98static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size)
99{
100 SuperIOConfig *superio_conf = opaque;
101
102 DPRINTF("superio_ioport_readb address 0x%x\n", addr);
103 return (superio_conf->config[superio_conf->index]);
104}
105
106static const MemoryRegionOps superio_ops = {
107 .read = superio_ioport_readb,
108 .write = superio_ioport_writeb,
109 .endianness = DEVICE_NATIVE_ENDIAN,
110 .impl = {
111 .min_access_size = 1,
112 .max_access_size = 1,
113 },
114};
115
116static void vt82c686b_reset(void * opaque)
117{
118 PCIDevice *d = opaque;
119 uint8_t *pci_conf = d->config;
120 VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(VT82C686BState, dev)]; ({ const typeof(
((VT82C686BState *) 0)->dev) *__mptr = (d); (VT82C686BState
*) ((char *) __mptr - __builtin_offsetof(VT82C686BState, dev
));});}));
121
122 pci_set_long(pci_conf + PCI_CAPABILITY_LIST0x34, 0x000000c0);
123 pci_set_word(pci_conf + PCI_COMMAND0x04, PCI_COMMAND_IO0x1 | PCI_COMMAND_MEMORY0x2 |
124 PCI_COMMAND_MASTER0x4 | PCI_COMMAND_SPECIAL0x8);
125 pci_set_word(pci_conf + PCI_STATUS0x06, PCI_STATUS_DEVSEL_MEDIUM0x200);
126
127 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
128 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
129 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
130 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
131 pci_conf[0x59] = 0x04;
132 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
133 pci_conf[0x5f] = 0x04;
134 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
135
136 vt82c->superio_conf.config[0xe0] = 0x3c;
137 vt82c->superio_conf.config[0xe2] = 0x03;
138 vt82c->superio_conf.config[0xe3] = 0xfc;
139 vt82c->superio_conf.config[0xe6] = 0xde;
140 vt82c->superio_conf.config[0xe7] = 0xfe;
141 vt82c->superio_conf.config[0xe8] = 0xbe;
142}
143
144/* write config pci function0 registers. PCI-ISA bridge */
145static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
146 uint32_t val, int len)
147{
148 VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(VT82C686BState, dev)]; ({ const typeof(
((VT82C686BState *) 0)->dev) *__mptr = (d); (VT82C686BState
*) ((char *) __mptr - __builtin_offsetof(VT82C686BState, dev
));});}));
149
150 DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
151 address, val, len);
152
153 pci_default_write_config(d, address, val, len);
154 if (address == 0x85) { /* enable or disable super IO configure */
155 memory_region_set_enabled(&vt686->superio, val & 0x2);
156 }
157}
158
159#define ACPI_DBG_IO_ADDR0xb044 0xb044
160
161typedef struct VT686PMState {
162 PCIDevice dev;
163 MemoryRegion io;
164 ACPIREGS ar;
165 APMState apm;
166 PMSMBus smb;
167 uint32_t smb_io_base;
168} VT686PMState;
169
170typedef struct VT686AC97State {
171 PCIDevice dev;
172} VT686AC97State;
173
174typedef struct VT686MC97State {
175 PCIDevice dev;
176} VT686MC97State;
177
178static void pm_update_sci(VT686PMState *s)
179{
180 int sci_level, pmsts;
181
182 pmsts = acpi_pm1_evt_get_sts(&s->ar);
183 sci_level = (((pmsts & s->ar.pm1.evt.en) &
184 (ACPI_BITMASK_RT_CLOCK_ENABLE0x0400 |
185 ACPI_BITMASK_POWER_BUTTON_ENABLE0x0100 |
186 ACPI_BITMASK_GLOBAL_LOCK_ENABLE0x0020 |
187 ACPI_BITMASK_TIMER_ENABLE0x0001)) != 0);
188 pci_set_irq(&s->dev, sci_level);
189 /* schedule a timer interruption if needed */
190 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE0x0001) &&
191 !(pmsts & ACPI_BITMASK_TIMER_STATUS0x0001));
192}
193
194static void pm_tmr_timer(ACPIREGS *ar)
195{
196 VT686PMState *s = container_of(ar, VT686PMState, ar)({ const typeof(((VT686PMState *) 0)->ar) *__mptr = (ar); (
VT686PMState *) ((char *) __mptr - __builtin_offsetof(VT686PMState
, ar));});
197 pm_update_sci(s);
198}
199
200static void pm_io_space_update(VT686PMState *s)
201{
202 uint32_t pm_io_base;
203
204 pm_io_base = pci_get_long(s->dev.config + 0x40);
205 pm_io_base &= 0xffc0;
206
207 memory_region_transaction_begin();
208 memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
209 memory_region_set_address(&s->io, pm_io_base);
210 memory_region_transaction_commit();
211}
212
213static void pm_write_config(PCIDevice *d,
214 uint32_t address, uint32_t val, int len)
215{
216 DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
217 address, val, len);
218 pci_default_write_config(d, address, val, len);
219}
220
221static int vmstate_acpi_post_load(void *opaque, int version_id)
222{
223 VT686PMState *s = opaque;
224
225 pm_io_space_update(s);
226 return 0;
227}
228
229static const VMStateDescription vmstate_acpi = {
230 .name = "vt82c686b_pm",
231 .version_id = 1,
232 .minimum_version_id = 1,
233 .minimum_version_id_old = 1,
234 .post_load = vmstate_acpi_post_load,
235 .fields = (VMStateField []) {
236 VMSTATE_PCI_DEVICE(dev, VT686PMState){ .name = ("dev"), .size = sizeof(PCIDevice), .vmsd = &vmstate_pci_device
, .flags = VMS_STRUCT, .offset = (__builtin_offsetof(VT686PMState
, dev) + ((PCIDevice*)0 - (typeof(((VT686PMState *)0)->dev
)*)0)), },
237 VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState){ .name = ("ar.pm1.evt.sts"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(VT686PMState
, ar.pm1.evt.sts) + ((uint16_t*)0 - (typeof(((VT686PMState *)
0)->ar.pm1.evt.sts)*)0)), },
238 VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState){ .name = ("ar.pm1.evt.en"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(VT686PMState
, ar.pm1.evt.en) + ((uint16_t*)0 - (typeof(((VT686PMState *)0
)->ar.pm1.evt.en)*)0)), },
239 VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState){ .name = ("ar.pm1.cnt.cnt"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(VT686PMState
, ar.pm1.cnt.cnt) + ((uint16_t*)0 - (typeof(((VT686PMState *)
0)->ar.pm1.cnt.cnt)*)0)), },
240 VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState){ .name = ("apm"), .version_id = (0), .field_exists = (((void
*)0)), .vmsd = &(vmstate_apm), .size = sizeof(APMState), .
flags = VMS_STRUCT, .offset = (__builtin_offsetof(VT686PMState
, apm) + ((APMState*)0 - (typeof(((VT686PMState *)0)->apm)
*)0)), },
241 VMSTATE_TIMER(ar.tmr.timer, VT686PMState){ .name = ("ar.tmr.timer"), .version_id = (0), .info = &(
vmstate_info_timer), .size = sizeof(QEMUTimer *), .flags = VMS_SINGLE
|VMS_POINTER, .offset = (__builtin_offsetof(VT686PMState, ar.
tmr.timer) + ((QEMUTimer **)0 - (typeof(((VT686PMState *)0)->
ar.tmr.timer)*)0)), },
242 VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState){ .name = ("ar.tmr.overflow_time"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(int64_t), .info = &(vmstate_info_int64
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(VT686PMState
, ar.tmr.overflow_time) + ((int64_t*)0 - (typeof(((VT686PMState
*)0)->ar.tmr.overflow_time)*)0)), },
243 VMSTATE_END_OF_LIST(){}
244 }
245};
246
247/*
248 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
249 * just register a PCI device now, functionalities will be implemented later.
250 */
251
252static int vt82c686b_ac97_initfn(PCIDevice *dev)
253{
254 VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(VT686AC97State, dev)]; ({ const typeof(
((VT686AC97State *) 0)->dev) *__mptr = (dev); (VT686AC97State
*) ((char *) __mptr - __builtin_offsetof(VT686AC97State, dev
));});}));
255 uint8_t *pci_conf = s->dev.config;
256
257 pci_set_word(pci_conf + PCI_COMMAND0x04, PCI_COMMAND_INVALIDATE0x10 |
258 PCI_COMMAND_PARITY0x40);
259 pci_set_word(pci_conf + PCI_STATUS0x06, PCI_STATUS_CAP_LIST0x10 |
260 PCI_STATUS_DEVSEL_MEDIUM0x200);
261 pci_set_long(pci_conf + PCI_INTERRUPT_PIN0x3d, 0x03);
262
263 return 0;
264}
265
266void vt82c686b_ac97_init(PCIBus *bus, int devfn)
267{
268 PCIDevice *dev;
269
270 dev = pci_create(bus, devfn, "VT82C686B_AC97");
271 qdev_init_nofail(&dev->qdev);
272}
273
274static void via_ac97_class_init(ObjectClass *klass, void *data)
275{
276 DeviceClass *dc = DEVICE_CLASS(klass)((DeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/isa/vt82c686.c"
, 276, __func__));
277 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass)((PCIDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/isa/vt82c686.c"
, 277, __func__));
278
279 k->init = vt82c686b_ac97_initfn;
280 k->vendor_id = PCI_VENDOR_ID_VIA0x1106;
281 k->device_id = PCI_DEVICE_ID_VIA_AC970x3058;
282 k->revision = 0x50;
283 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO0x0401;
284 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
285 dc->desc = "AC97";
286}
287
288static const TypeInfo via_ac97_info = {
289 .name = "VT82C686B_AC97",
290 .parent = TYPE_PCI_DEVICE"pci-device",
291 .instance_size = sizeof(VT686AC97State),
292 .class_init = via_ac97_class_init,
293};
294
295static int vt82c686b_mc97_initfn(PCIDevice *dev)
296{
297 VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(VT686MC97State, dev)]; ({ const typeof(
((VT686MC97State *) 0)->dev) *__mptr = (dev); (VT686MC97State
*) ((char *) __mptr - __builtin_offsetof(VT686MC97State, dev
));});}));
298 uint8_t *pci_conf = s->dev.config;
299
300 pci_set_word(pci_conf + PCI_COMMAND0x04, PCI_COMMAND_INVALIDATE0x10 |
301 PCI_COMMAND_VGA_PALETTE0x20);
302 pci_set_word(pci_conf + PCI_STATUS0x06, PCI_STATUS_DEVSEL_MEDIUM0x200);
303 pci_set_long(pci_conf + PCI_INTERRUPT_PIN0x3d, 0x03);
304
305 return 0;
306}
307
308void vt82c686b_mc97_init(PCIBus *bus, int devfn)
309{
310 PCIDevice *dev;
311
312 dev = pci_create(bus, devfn, "VT82C686B_MC97");
313 qdev_init_nofail(&dev->qdev);
314}
315
316static void via_mc97_class_init(ObjectClass *klass, void *data)
317{
318 DeviceClass *dc = DEVICE_CLASS(klass)((DeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/isa/vt82c686.c"
, 318, __func__));
319 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass)((PCIDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/isa/vt82c686.c"
, 319, __func__));
320
321 k->init = vt82c686b_mc97_initfn;
322 k->vendor_id = PCI_VENDOR_ID_VIA0x1106;
323 k->device_id = PCI_DEVICE_ID_VIA_MC970x3068;
324 k->class_id = PCI_CLASS_COMMUNICATION_OTHER0x0780;
325 k->revision = 0x30;
326 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
327 dc->desc = "MC97";
328}
329
330static const TypeInfo via_mc97_info = {
331 .name = "VT82C686B_MC97",
332 .parent = TYPE_PCI_DEVICE"pci-device",
333 .instance_size = sizeof(VT686MC97State),
334 .class_init = via_mc97_class_init,
335};
336
337/* vt82c686 pm init */
338static int vt82c686b_pm_initfn(PCIDevice *dev)
339{
340 VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(VT686PMState, dev)]; ({ const typeof(((
VT686PMState *) 0)->dev) *__mptr = (dev); (VT686PMState *)
((char *) __mptr - __builtin_offsetof(VT686PMState, dev));})
;}));
341 uint8_t *pci_conf;
342
343 pci_conf = s->dev.config;
344 pci_set_word(pci_conf + PCI_COMMAND0x04, 0);
345 pci_set_word(pci_conf + PCI_STATUS0x06, PCI_STATUS_FAST_BACK0x80 |
346 PCI_STATUS_DEVSEL_MEDIUM0x200);
347
348 /* 0x48-0x4B is Power Management I/O Base */
349 pci_set_long(pci_conf + 0x48, 0x00000001);
350
351 /* SMB ports:0xeee0~0xeeef */
352 s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
353 pci_conf[0x90] = s->smb_io_base | 1;
354 pci_conf[0x91] = s->smb_io_base >> 8;
355 pci_conf[0xd2] = 0x90;
356 pm_smbus_init(&s->dev.qdev, &s->smb);
357 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
358
359 apm_init(dev, &s->apm, NULL((void*)0), s);
360
361 memory_region_init(&s->io, OBJECT(dev)((Object *)(dev)), "vt82c686-pm", 64);
362 memory_region_set_enabled(&s->io, false0);
363 memory_region_add_subregion(get_system_io(), 0, &s->io);
364
365 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
366 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
367 acpi_pm1_cnt_init(&s->ar, &s->io, 2);
368
369 return 0;
370}
371
372i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
373 qemu_irq sci_irq)
374{
375 PCIDevice *dev;
376 VT686PMState *s;
377
378 dev = pci_create(bus, devfn, "VT82C686B_PM");
379 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
380
381 s = DO_UPCAST(VT686PMState, dev, dev)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(VT686PMState, dev)]; ({ const typeof(((
VT686PMState *) 0)->dev) *__mptr = (dev); (VT686PMState *)
((char *) __mptr - __builtin_offsetof(VT686PMState, dev));})
;}));
382
383 qdev_init_nofail(&dev->qdev);
384
385 return s->smb.smbus;
386}
387
388static Property via_pm_properties[] = {
389 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0){ .name = ("smb_io_base"), .info = &(qdev_prop_uint32), .
offset = __builtin_offsetof(VT686PMState, smb_io_base) + ((uint32_t
*)0 - (typeof(((VT686PMState *)0)->smb_io_base)*)0), .qtype
= QTYPE_QINT, .defval = (uint32_t)0, },
390 DEFINE_PROP_END_OF_LIST(){},
391};
392
393static void via_pm_class_init(ObjectClass *klass, void *data)
394{
395 DeviceClass *dc = DEVICE_CLASS(klass)((DeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/isa/vt82c686.c"
, 395, __func__));
396 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass)((PCIDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/isa/vt82c686.c"
, 396, __func__));
397
398 k->init = vt82c686b_pm_initfn;
399 k->config_write = pm_write_config;
400 k->vendor_id = PCI_VENDOR_ID_VIA0x1106;
401 k->device_id = PCI_DEVICE_ID_VIA_ACPI0x3057;
402 k->class_id = PCI_CLASS_BRIDGE_OTHER0x0680;
403 k->revision = 0x40;
404 dc->desc = "PM";
405 dc->vmsd = &vmstate_acpi;
406 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
407 dc->props = via_pm_properties;
408}
409
410static const TypeInfo via_pm_info = {
411 .name = "VT82C686B_PM",
412 .parent = TYPE_PCI_DEVICE"pci-device",
413 .instance_size = sizeof(VT686PMState),
414 .class_init = via_pm_class_init,
415};
416
417static const VMStateDescription vmstate_via = {
418 .name = "vt82c686b",
419 .version_id = 1,
420 .minimum_version_id = 1,
421 .minimum_version_id_old = 1,
422 .fields = (VMStateField []) {
423 VMSTATE_PCI_DEVICE(dev, VT82C686BState){ .name = ("dev"), .size = sizeof(PCIDevice), .vmsd = &vmstate_pci_device
, .flags = VMS_STRUCT, .offset = (__builtin_offsetof(VT82C686BState
, dev) + ((PCIDevice*)0 - (typeof(((VT82C686BState *)0)->dev
)*)0)), },
424 VMSTATE_END_OF_LIST(){}
425 }
426};
427
428/* init the PCI-to-ISA bridge */
429static int vt82c686b_initfn(PCIDevice *d)
430{
431 VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(VT82C686BState, dev)]; ({ const typeof(
((VT82C686BState *) 0)->dev) *__mptr = (d); (VT82C686BState
*) ((char *) __mptr - __builtin_offsetof(VT82C686BState, dev
));});}));
432 uint8_t *pci_conf;
433 ISABus *isa_bus;
434 uint8_t *wmask;
435 int i;
436
437 isa_bus = isa_bus_new(&d->qdev, pci_address_space_io(d));
438
439 pci_conf = d->config;
440 pci_config_set_prog_interface(pci_conf, 0x0);
441
442 wmask = d->wmask;
443 for (i = 0x00; i < 0xff; i++) {
444 if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
445 wmask[i] = 0x00;
446 }
447 }
448
449 memory_region_init_io(&vt82c->superio, OBJECT(d)((Object *)(d)), &superio_ops,
450 &vt82c->superio_conf, "superio", 2);
451 memory_region_set_enabled(&vt82c->superio, false0);
452 /* The floppy also uses 0x3f0 and 0x3f1.
453 * But we do not emulate a floppy, so just set it here. */
454 memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
455 &vt82c->superio);
456
457 qemu_register_reset(vt82c686b_reset, d);
458
459 return 0;
460}
461
462ISABus *vt82c686b_init(PCIBus *bus, int devfn)
463{
464 PCIDevice *d;
465
466 d = pci_create_simple_multifunction(bus, devfn, true1, "VT82C686B");
467
468 return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"))((ISABus *)object_dynamic_cast_assert(((Object *)((qdev_get_child_bus
(((DeviceState *)object_dynamic_cast_assert(((Object *)((d)))
, ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/isa/vt82c686.c"
, 468, __func__)), "isa.0")))), ("ISA"), "/home/stefan/src/qemu/qemu.org/qemu/hw/isa/vt82c686.c"
, 468, __func__));
469}
470
471static void via_class_init(ObjectClass *klass, void *data)
472{
473 DeviceClass *dc = DEVICE_CLASS(klass)((DeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/isa/vt82c686.c"
, 473, __func__));
474 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass)((PCIDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/isa/vt82c686.c"
, 474, __func__));
475
476 k->init = vt82c686b_initfn;
477 k->config_write = vt82c686b_write_config;
478 k->vendor_id = PCI_VENDOR_ID_VIA0x1106;
479 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE0x0686;
480 k->class_id = PCI_CLASS_BRIDGE_ISA0x0601;
481 k->revision = 0x40;
482 dc->desc = "ISA bridge";
483 dc->vmsd = &vmstate_via;
484 /*
485 * Reason: part of VIA VT82C686 southbridge, needs to be wired up,
486 * e.g. by mips_fulong2e_init()
487 */
488 dc->cannot_instantiate_with_device_add_yet = true1;
489}
490
491static const TypeInfo via_info = {
492 .name = "VT82C686B",
493 .parent = TYPE_PCI_DEVICE"pci-device",
494 .instance_size = sizeof(VT82C686BState),
495 .class_init = via_class_init,
496};
497
498static void vt82c686b_register_types(void)
499{
500 type_register_static(&via_ac97_info);
501 type_register_static(&via_mc97_info);
502 type_register_static(&via_pm_info);
503 type_register_static(&via_info);
504}
505
506type_init(vt82c686b_register_types)static void __attribute__((constructor)) do_qemu_init_vt82c686b_register_types
(void) { register_module_init(vt82c686b_register_types, MODULE_INIT_QOM
); }