Bug Summary

File:hw/char/exynos4210_uart.c
Location:line 337, column 5
Description:Value stored to 'frame_size' is never read

Annotated Source Code

1/*
2 * Exynos4210 UART Emulation
3 *
4 * Copyright (C) 2011 Samsung Electronics Co Ltd.
5 * Maksim Kozlov, <m.kozlov@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 *
20 */
21
22#include "hw/sysbus.h"
23#include "sysemu/sysemu.h"
24#include "sysemu/char.h"
25
26#include "hw/arm/exynos4210.h"
27
28#undef DEBUG_UART0
29#undef DEBUG_UART_EXTEND0
30#undef DEBUG_IRQ0
31#undef DEBUG_Rx_DATA0
32#undef DEBUG_Tx_DATA0
33
34#define DEBUG_UART0 0
35#define DEBUG_UART_EXTEND0 0
36#define DEBUG_IRQ0 0
37#define DEBUG_Rx_DATA0 0
38#define DEBUG_Tx_DATA0 0
39
40#if DEBUG_UART0
41#define PRINT_DEBUG(fmt, args...)do {} while (0) \
42 do { \
43 fprintf(stderrstderr, " [%s:%d] "fmt, __func__, __LINE__43, ##args); \
44 } while (0)
45
46#if DEBUG_UART_EXTEND0
47#define PRINT_DEBUG_EXTEND(fmt, args...)do {} while (0) \
48 do { \
49 fprintf(stderrstderr, " [%s:%d] "fmt, __func__, __LINE__49, ##args); \
50 } while (0)
51#else
52#define PRINT_DEBUG_EXTEND(fmt, args...)do {} while (0) \
53 do {} while (0)
54#endif /* EXTEND */
55
56#else
57#define PRINT_DEBUG(fmt, args...)do {} while (0) \
58 do {} while (0)
59#define PRINT_DEBUG_EXTEND(fmt, args...)do {} while (0) \
60 do {} while (0)
61#endif
62
63#define PRINT_ERROR(fmt, args...)do { fprintf(stderr, " [%s:%d] "fmt, __func__, 63, args...
); } while (0) \
64 do { \
65 fprintf(stderrstderr, " [%s:%d] "fmt, __func__, __LINE__65, ##args); \
66 } while (0)
67
68/*
69 * Offsets for UART registers relative to SFR base address
70 * for UARTn
71 *
72 */
73#define ULCON0x0000 0x0000 /* Line Control */
74#define UCON0x0004 0x0004 /* Control */
75#define UFCON0x0008 0x0008 /* FIFO Control */
76#define UMCON0x000C 0x000C /* Modem Control */
77#define UTRSTAT0x0010 0x0010 /* Tx/Rx Status */
78#define UERSTAT0x0014 0x0014 /* UART Error Status */
79#define UFSTAT0x0018 0x0018 /* FIFO Status */
80#define UMSTAT0x001C 0x001C /* Modem Status */
81#define UTXH0x0020 0x0020 /* Transmit Buffer */
82#define URXH0x0024 0x0024 /* Receive Buffer */
83#define UBRDIV0x0028 0x0028 /* Baud Rate Divisor */
84#define UFRACVAL0x002C 0x002C /* Divisor Fractional Value */
85#define UINTP0x0030 0x0030 /* Interrupt Pending */
86#define UINTSP0x0034 0x0034 /* Interrupt Source Pending */
87#define UINTM0x0038 0x0038 /* Interrupt Mask */
88
89/*
90 * for indexing register in the uint32_t array
91 *
92 * 'reg' - register offset (see offsets definitions above)
93 *
94 */
95#define I_(reg)(reg / sizeof(uint32_t)) (reg / sizeof(uint32_t))
96
97typedef struct Exynos4210UartReg {
98 const char *name; /* the only reason is the debug output */
99 hwaddr offset;
100 uint32_t reset_value;
101} Exynos4210UartReg;
102
103static Exynos4210UartReg exynos4210_uart_regs[] = {
104 {"ULCON", ULCON0x0000, 0x00000000},
105 {"UCON", UCON0x0004, 0x00003000},
106 {"UFCON", UFCON0x0008, 0x00000000},
107 {"UMCON", UMCON0x000C, 0x00000000},
108 {"UTRSTAT", UTRSTAT0x0010, 0x00000006}, /* RO */
109 {"UERSTAT", UERSTAT0x0014, 0x00000000}, /* RO */
110 {"UFSTAT", UFSTAT0x0018, 0x00000000}, /* RO */
111 {"UMSTAT", UMSTAT0x001C, 0x00000000}, /* RO */
112 {"UTXH", UTXH0x0020, 0x5c5c5c5c}, /* WO, undefined reset value*/
113 {"URXH", URXH0x0024, 0x00000000}, /* RO */
114 {"UBRDIV", UBRDIV0x0028, 0x00000000},
115 {"UFRACVAL", UFRACVAL0x002C, 0x00000000},
116 {"UINTP", UINTP0x0030, 0x00000000},
117 {"UINTSP", UINTSP0x0034, 0x00000000},
118 {"UINTM", UINTM0x0038, 0x00000000},
119};
120
121#define EXYNOS4210_UART_REGS_MEM_SIZE0x3C 0x3C
122
123/* UART FIFO Control */
124#define UFCON_FIFO_ENABLE0x1 0x1
125#define UFCON_Rx_FIFO_RESET0x2 0x2
126#define UFCON_Tx_FIFO_RESET0x4 0x4
127#define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT8 8
128#define UFCON_Tx_FIFO_TRIGGER_LEVEL(7 << 8) (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT8)
129#define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT4 4
130#define UFCON_Rx_FIFO_TRIGGER_LEVEL(7 << 4) (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT4)
131
132/* Uart FIFO Status */
133#define UFSTAT_Rx_FIFO_COUNT0xff 0xff
134#define UFSTAT_Rx_FIFO_FULL0x100 0x100
135#define UFSTAT_Rx_FIFO_ERROR0x200 0x200
136#define UFSTAT_Tx_FIFO_COUNT_SHIFT16 16
137#define UFSTAT_Tx_FIFO_COUNT(0xff << 16) (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT16)
138#define UFSTAT_Tx_FIFO_FULL_SHIFT24 24
139#define UFSTAT_Tx_FIFO_FULL(1 << 24) (1 << UFSTAT_Tx_FIFO_FULL_SHIFT24)
140
141/* UART Interrupt Source Pending */
142#define UINTSP_RXD0x1 0x1 /* Receive interrupt */
143#define UINTSP_ERROR0x2 0x2 /* Error interrupt */
144#define UINTSP_TXD0x4 0x4 /* Transmit interrupt */
145#define UINTSP_MODEM0x8 0x8 /* Modem interrupt */
146
147/* UART Line Control */
148#define ULCON_IR_MODE_SHIFT6 6
149#define ULCON_PARITY_SHIFT3 3
150#define ULCON_STOP_BIT_SHIFT1 1
151
152/* UART Tx/Rx Status */
153#define UTRSTAT_TRANSMITTER_EMPTY0x4 0x4
154#define UTRSTAT_Tx_BUFFER_EMPTY0x2 0x2
155#define UTRSTAT_Rx_BUFFER_DATA_READY0x1 0x1
156
157/* UART Error Status */
158#define UERSTAT_OVERRUN0x1 0x1
159#define UERSTAT_PARITY0x2 0x2
160#define UERSTAT_FRAME0x4 0x4
161#define UERSTAT_BREAK0x8 0x8
162
163typedef struct {
164 uint8_t *data;
165 uint32_t sp, rp; /* store and retrieve pointers */
166 uint32_t size;
167} Exynos4210UartFIFO;
168
169#define TYPE_EXYNOS4210_UART"exynos4210.uart" "exynos4210.uart"
170#define EXYNOS4210_UART(obj)((Exynos4210UartState *)object_dynamic_cast_assert(((Object *
)((obj))), ("exynos4210.uart"), "/home/stefan/src/qemu/qemu.org/qemu/hw/char/exynos4210_uart.c"
, 170, __func__)) \
171 OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART)((Exynos4210UartState *)object_dynamic_cast_assert(((Object *
)((obj))), ("exynos4210.uart"), "/home/stefan/src/qemu/qemu.org/qemu/hw/char/exynos4210_uart.c"
, 171, __func__))
172
173typedef struct Exynos4210UartState {
174 SysBusDevice parent_obj;
175
176 MemoryRegion iomem;
177
178 uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE0x3C / sizeof(uint32_t)];
179 Exynos4210UartFIFO rx;
180 Exynos4210UartFIFO tx;
181
182 CharDriverState *chr;
183 qemu_irq irq;
184
185 uint32_t channel;
186
187} Exynos4210UartState;
188
189
190#if DEBUG_UART0
191/* Used only for debugging inside PRINT_DEBUG_... macros */
192static const char *exynos4210_uart_regname(hwaddr offset)
193{
194
195 int i;
196
197 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs)(sizeof(exynos4210_uart_regs) / sizeof((exynos4210_uart_regs)
[0])); i++) {
198 if (offset == exynos4210_uart_regs[i].offset) {
199 return exynos4210_uart_regs[i].name;
200 }
201 }
202
203 return NULL((void*)0);
204}
205#endif
206
207
208static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch)
209{
210 q->data[q->sp] = ch;
211 q->sp = (q->sp + 1) % q->size;
212}
213
214static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
215{
216 uint8_t ret = q->data[q->rp];
217 q->rp = (q->rp + 1) % q->size;
218 return ret;
219}
220
221static int fifo_elements_number(Exynos4210UartFIFO *q)
222{
223 if (q->sp < q->rp) {
224 return q->size - q->rp + q->sp;
225 }
226
227 return q->sp - q->rp;
228}
229
230static int fifo_empty_elements_number(Exynos4210UartFIFO *q)
231{
232 return q->size - fifo_elements_number(q);
233}
234
235static void fifo_reset(Exynos4210UartFIFO *q)
236{
237 if (q->data != NULL((void*)0)) {
238 g_free(q->data);
239 q->data = NULL((void*)0);
240 }
241
242 q->data = (uint8_t *)g_malloc0(q->size);
243
244 q->sp = 0;
245 q->rp = 0;
246}
247
248static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
249{
250 uint32_t level = 0;
251 uint32_t reg;
252
253 reg = (s->reg[I_(UFCON)(0x0008 / sizeof(uint32_t))] & UFCON_Tx_FIFO_TRIGGER_LEVEL(7 << 8)) >>
254 UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT8;
255
256 switch (s->channel) {
257 case 0:
258 level = reg * 32;
259 break;
260 case 1:
261 case 4:
262 level = reg * 8;
263 break;
264 case 2:
265 case 3:
266 level = reg * 2;
267 break;
268 default:
269 level = 0;
270 PRINT_ERROR("Wrong UART channel number: %d\n", s->channel)do { fprintf(stderr, " [%s:%d] ""Wrong UART channel number: %d\n"
, __func__, 270, s->channel); } while (0);
271 }
272
273 return level;
274}
275
276static void exynos4210_uart_update_irq(Exynos4210UartState *s)
277{
278 /*
279 * The Tx interrupt is always requested if the number of data in the
280 * transmit FIFO is smaller than the trigger level.
281 */
282 if (s->reg[I_(UFCON)(0x0008 / sizeof(uint32_t))] & UFCON_FIFO_ENABLE0x1) {
283
284 uint32_t count = (s->reg[I_(UFSTAT)(0x0018 / sizeof(uint32_t))] & UFSTAT_Tx_FIFO_COUNT(0xff << 16)) >>
285 UFSTAT_Tx_FIFO_COUNT_SHIFT16;
286
287 if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {
288 s->reg[I_(UINTSP)(0x0034 / sizeof(uint32_t))] |= UINTSP_TXD0x4;
289 }
290 }
291
292 s->reg[I_(UINTP)(0x0030 / sizeof(uint32_t))] = s->reg[I_(UINTSP)(0x0034 / sizeof(uint32_t))] & ~s->reg[I_(UINTM)(0x0038 / sizeof(uint32_t))];
293
294 if (s->reg[I_(UINTP)(0x0030 / sizeof(uint32_t))]) {
295 qemu_irq_raise(s->irq);
296
297#if DEBUG_IRQ0
298 fprintf(stderrstderr, "UART%d: IRQ has been raised: %08x\n",
299 s->channel, s->reg[I_(UINTP)(0x0030 / sizeof(uint32_t))]);
300#endif
301
302 } else {
303 qemu_irq_lower(s->irq);
304 }
305}
306
307static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
308{
309 int speed, parity, data_bits, stop_bits, frame_size;
310 QEMUSerialSetParams ssp;
311 uint64_t uclk_rate;
312
313 if (s->reg[I_(UBRDIV)(0x0028 / sizeof(uint32_t))] == 0) {
314 return;
315 }
316
317 frame_size = 1; /* start bit */
318 if (s->reg[I_(ULCON)(0x0000 / sizeof(uint32_t))] & 0x20) {
319 frame_size++; /* parity bit */
320 if (s->reg[I_(ULCON)(0x0000 / sizeof(uint32_t))] & 0x28) {
321 parity = 'E';
322 } else {
323 parity = 'O';
324 }
325 } else {
326 parity = 'N';
327 }
328
329 if (s->reg[I_(ULCON)(0x0000 / sizeof(uint32_t))] & 0x4) {
330 stop_bits = 2;
331 } else {
332 stop_bits = 1;
333 }
334
335 data_bits = (s->reg[I_(ULCON)(0x0000 / sizeof(uint32_t))] & 0x3) + 5;
336
337 frame_size += data_bits + stop_bits;
Value stored to 'frame_size' is never read
338
339 uclk_rate = 24000000;
340
341 speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)(0x0028 / sizeof(uint32_t))]) & 0xffff) +
342 (s->reg[I_(UFRACVAL)(0x002C / sizeof(uint32_t))] & 0x7) + 16);
343
344 ssp.speed = speed;
345 ssp.parity = parity;
346 ssp.data_bits = data_bits;
347 ssp.stop_bits = stop_bits;
348
349 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS1, &ssp);
350
351 PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n",do {} while (0)
352 s->channel, speed, parity, data_bits, stop_bits)do {} while (0);
353}
354
355static void exynos4210_uart_write(void *opaque, hwaddr offset,
356 uint64_t val, unsigned size)
357{
358 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
359 uint8_t ch;
360
361 PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel,do {} while (0)
362 offset, exynos4210_uart_regname(offset), (long long unsigned int)val)do {} while (0);
363
364 switch (offset) {
365 case ULCON0x0000:
366 case UBRDIV0x0028:
367 case UFRACVAL0x002C:
368 s->reg[I_(offset)(offset / sizeof(uint32_t))] = val;
369 exynos4210_uart_update_parameters(s);
370 break;
371 case UFCON0x0008:
372 s->reg[I_(UFCON)(0x0008 / sizeof(uint32_t))] = val;
373 if (val & UFCON_Rx_FIFO_RESET0x2) {
374 fifo_reset(&s->rx);
375 s->reg[I_(UFCON)(0x0008 / sizeof(uint32_t))] &= ~UFCON_Rx_FIFO_RESET0x2;
376 PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel)do {} while (0);
377 }
378 if (val & UFCON_Tx_FIFO_RESET0x4) {
379 fifo_reset(&s->tx);
380 s->reg[I_(UFCON)(0x0008 / sizeof(uint32_t))] &= ~UFCON_Tx_FIFO_RESET0x4;
381 PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel)do {} while (0);
382 }
383 break;
384
385 case UTXH0x0020:
386 if (s->chr) {
387 s->reg[I_(UTRSTAT)(0x0010 / sizeof(uint32_t))] &= ~(UTRSTAT_TRANSMITTER_EMPTY0x4 |
388 UTRSTAT_Tx_BUFFER_EMPTY0x2);
389 ch = (uint8_t)val;
390 qemu_chr_fe_write(s->chr, &ch, 1);
391#if DEBUG_Tx_DATA0
392 fprintf(stderrstderr, "%c", ch);
393#endif
394 s->reg[I_(UTRSTAT)(0x0010 / sizeof(uint32_t))] |= UTRSTAT_TRANSMITTER_EMPTY0x4 |
395 UTRSTAT_Tx_BUFFER_EMPTY0x2;
396 s->reg[I_(UINTSP)(0x0034 / sizeof(uint32_t))] |= UINTSP_TXD0x4;
397 exynos4210_uart_update_irq(s);
398 }
399 break;
400
401 case UINTP0x0030:
402 s->reg[I_(UINTP)(0x0030 / sizeof(uint32_t))] &= ~val;
403 s->reg[I_(UINTSP)(0x0034 / sizeof(uint32_t))] &= ~val;
404 PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n",do {} while (0)
405 s->channel, offset, s->reg[I_(UINTP)])do {} while (0);
406 exynos4210_uart_update_irq(s);
407 break;
408 case UTRSTAT0x0010:
409 case UERSTAT0x0014:
410 case UFSTAT0x0018:
411 case UMSTAT0x001C:
412 case URXH0x0024:
413 PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n",do {} while (0)
414 s->channel, exynos4210_uart_regname(offset), offset)do {} while (0);
415 break;
416 case UINTSP0x0034:
417 s->reg[I_(UINTSP)(0x0034 / sizeof(uint32_t))] &= ~val;
418 break;
419 case UINTM0x0038:
420 s->reg[I_(UINTM)(0x0038 / sizeof(uint32_t))] = val;
421 exynos4210_uart_update_irq(s);
422 break;
423 case UCON0x0004:
424 case UMCON0x000C:
425 default:
426 s->reg[I_(offset)(offset / sizeof(uint32_t))] = val;
427 break;
428 }
429}
430static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
431 unsigned size)
432{
433 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
434 uint32_t res;
435
436 switch (offset) {
437 case UERSTAT0x0014: /* Read Only */
438 res = s->reg[I_(UERSTAT)(0x0014 / sizeof(uint32_t))];
439 s->reg[I_(UERSTAT)(0x0014 / sizeof(uint32_t))] = 0;
440 return res;
441 case UFSTAT0x0018: /* Read Only */
442 s->reg[I_(UFSTAT)(0x0018 / sizeof(uint32_t))] = fifo_elements_number(&s->rx) & 0xff;
443 if (fifo_empty_elements_number(&s->rx) == 0) {
444 s->reg[I_(UFSTAT)(0x0018 / sizeof(uint32_t))] |= UFSTAT_Rx_FIFO_FULL0x100;
445 s->reg[I_(UFSTAT)(0x0018 / sizeof(uint32_t))] &= ~0xff;
446 }
447 return s->reg[I_(UFSTAT)(0x0018 / sizeof(uint32_t))];
448 case URXH0x0024:
449 if (s->reg[I_(UFCON)(0x0008 / sizeof(uint32_t))] & UFCON_FIFO_ENABLE0x1) {
450 if (fifo_elements_number(&s->rx)) {
451 res = fifo_retrieve(&s->rx);
452#if DEBUG_Rx_DATA0
453 fprintf(stderrstderr, "%c", res);
454#endif
455 if (!fifo_elements_number(&s->rx)) {
456 s->reg[I_(UTRSTAT)(0x0010 / sizeof(uint32_t))] &= ~UTRSTAT_Rx_BUFFER_DATA_READY0x1;
457 } else {
458 s->reg[I_(UTRSTAT)(0x0010 / sizeof(uint32_t))] |= UTRSTAT_Rx_BUFFER_DATA_READY0x1;
459 }
460 } else {
461 s->reg[I_(UINTSP)(0x0034 / sizeof(uint32_t))] |= UINTSP_ERROR0x2;
462 exynos4210_uart_update_irq(s);
463 res = 0;
464 }
465 } else {
466 s->reg[I_(UTRSTAT)(0x0010 / sizeof(uint32_t))] &= ~UTRSTAT_Rx_BUFFER_DATA_READY0x1;
467 res = s->reg[I_(URXH)(0x0024 / sizeof(uint32_t))];
468 }
469 return res;
470 case UTXH0x0020:
471 PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n",do {} while (0)
472 s->channel, exynos4210_uart_regname(offset), offset)do {} while (0);
473 break;
474 default:
475 return s->reg[I_(offset)(offset / sizeof(uint32_t))];
476 }
477
478 return 0;
479}
480
481static const MemoryRegionOps exynos4210_uart_ops = {
482 .read = exynos4210_uart_read,
483 .write = exynos4210_uart_write,
484 .endianness = DEVICE_NATIVE_ENDIAN,
485 .valid = {
486 .max_access_size = 4,
487 .unaligned = false0
488 },
489};
490
491static int exynos4210_uart_can_receive(void *opaque)
492{
493 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
494
495 return fifo_empty_elements_number(&s->rx);
496}
497
498
499static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
500{
501 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
502 int i;
503
504 if (s->reg[I_(UFCON)(0x0008 / sizeof(uint32_t))] & UFCON_FIFO_ENABLE0x1) {
505 if (fifo_empty_elements_number(&s->rx) < size) {
506 for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) {
507 fifo_store(&s->rx, buf[i]);
508 }
509 s->reg[I_(UINTSP)(0x0034 / sizeof(uint32_t))] |= UINTSP_ERROR0x2;
510 s->reg[I_(UTRSTAT)(0x0010 / sizeof(uint32_t))] |= UTRSTAT_Rx_BUFFER_DATA_READY0x1;
511 } else {
512 for (i = 0; i < size; i++) {
513 fifo_store(&s->rx, buf[i]);
514 }
515 s->reg[I_(UTRSTAT)(0x0010 / sizeof(uint32_t))] |= UTRSTAT_Rx_BUFFER_DATA_READY0x1;
516 }
517 /* XXX: Around here we maybe should check Rx trigger level */
518 s->reg[I_(UINTSP)(0x0034 / sizeof(uint32_t))] |= UINTSP_RXD0x1;
519 } else {
520 s->reg[I_(URXH)(0x0024 / sizeof(uint32_t))] = buf[0];
521 s->reg[I_(UINTSP)(0x0034 / sizeof(uint32_t))] |= UINTSP_RXD0x1;
522 s->reg[I_(UTRSTAT)(0x0010 / sizeof(uint32_t))] |= UTRSTAT_Rx_BUFFER_DATA_READY0x1;
523 }
524
525 exynos4210_uart_update_irq(s);
526}
527
528
529static void exynos4210_uart_event(void *opaque, int event)
530{
531 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
532
533 if (event == CHR_EVENT_BREAK0) {
534 /* When the RxDn is held in logic 0, then a null byte is pushed into the
535 * fifo */
536 fifo_store(&s->rx, '\0');
537 s->reg[I_(UERSTAT)(0x0014 / sizeof(uint32_t))] |= UERSTAT_BREAK0x8;
538 exynos4210_uart_update_irq(s);
539 }
540}
541
542
543static void exynos4210_uart_reset(DeviceState *dev)
544{
545 Exynos4210UartState *s = EXYNOS4210_UART(dev)((Exynos4210UartState *)object_dynamic_cast_assert(((Object *
)((dev))), ("exynos4210.uart"), "/home/stefan/src/qemu/qemu.org/qemu/hw/char/exynos4210_uart.c"
, 545, __func__));
546 int i;
547
548 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs)(sizeof(exynos4210_uart_regs) / sizeof((exynos4210_uart_regs)
[0])); i++) {
549 s->reg[I_(exynos4210_uart_regs[i].offset)(exynos4210_uart_regs[i].offset / sizeof(uint32_t))] =
550 exynos4210_uart_regs[i].reset_value;
551 }
552
553 fifo_reset(&s->rx);
554 fifo_reset(&s->tx);
555
556 PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size)do {} while (0);
557}
558
559static const VMStateDescription vmstate_exynos4210_uart_fifo = {
560 .name = "exynos4210.uart.fifo",
561 .version_id = 1,
562 .minimum_version_id = 1,
563 .minimum_version_id_old = 1,
564 .fields = (VMStateField[]) {
565 VMSTATE_UINT32(sp, Exynos4210UartFIFO){ .name = ("sp"), .version_id = (0), .field_exists = (((void*
)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210UartFIFO
, sp) + ((uint32_t*)0 - (typeof(((Exynos4210UartFIFO *)0)->
sp)*)0)), },
566 VMSTATE_UINT32(rp, Exynos4210UartFIFO){ .name = ("rp"), .version_id = (0), .field_exists = (((void*
)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210UartFIFO
, rp) + ((uint32_t*)0 - (typeof(((Exynos4210UartFIFO *)0)->
rp)*)0)), },
567 VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, 0, size){ .name = ("data"), .version_id = (1), .field_exists = (((void
*)0)), .size_offset = (__builtin_offsetof(Exynos4210UartFIFO,
size) + ((uint32_t*)0 - (typeof(((Exynos4210UartFIFO *)0)->
size)*)0)), .info = &vmstate_info_buffer, .flags = VMS_VBUFFER
|VMS_POINTER, .offset = __builtin_offsetof(Exynos4210UartFIFO
, data), .start = (0), },
568 VMSTATE_END_OF_LIST(){}
569 }
570};
571
572static const VMStateDescription vmstate_exynos4210_uart = {
573 .name = "exynos4210.uart",
574 .version_id = 1,
575 .minimum_version_id = 1,
576 .minimum_version_id_old = 1,
577 .fields = (VMStateField[]) {
578 VMSTATE_STRUCT(rx, Exynos4210UartState, 1,{ .name = ("rx"), .version_id = (1), .field_exists = (((void*
)0)), .vmsd = &(vmstate_exynos4210_uart_fifo), .size = sizeof
(Exynos4210UartFIFO), .flags = VMS_STRUCT, .offset = (__builtin_offsetof
(Exynos4210UartState, rx) + ((Exynos4210UartFIFO*)0 - (typeof
(((Exynos4210UartState *)0)->rx)*)0)), }
579 vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO){ .name = ("rx"), .version_id = (1), .field_exists = (((void*
)0)), .vmsd = &(vmstate_exynos4210_uart_fifo), .size = sizeof
(Exynos4210UartFIFO), .flags = VMS_STRUCT, .offset = (__builtin_offsetof
(Exynos4210UartState, rx) + ((Exynos4210UartFIFO*)0 - (typeof
(((Exynos4210UartState *)0)->rx)*)0)), },
580 VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState,{ .name = ("reg"), .version_id = (0), .num = (0x3C / sizeof(uint32_t
)), .info = &(vmstate_info_uint32), .size = sizeof(uint32_t
), .flags = VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210UartState
, reg) + ((uint32_t(*)[0x3C / sizeof(uint32_t)])0 - (typeof((
(Exynos4210UartState *)0)->reg)*)0)), }
581 EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)){ .name = ("reg"), .version_id = (0), .num = (0x3C / sizeof(uint32_t
)), .info = &(vmstate_info_uint32), .size = sizeof(uint32_t
), .flags = VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210UartState
, reg) + ((uint32_t(*)[0x3C / sizeof(uint32_t)])0 - (typeof((
(Exynos4210UartState *)0)->reg)*)0)), },
582 VMSTATE_END_OF_LIST(){}
583 }
584};
585
586DeviceState *exynos4210_uart_create(hwaddr addr,
587 int fifo_size,
588 int channel,
589 CharDriverState *chr,
590 qemu_irq irq)
591{
592 DeviceState *dev;
593 SysBusDevice *bus;
594
595 const char chr_name[] = "serial";
596 char label[ARRAY_SIZE(chr_name)(sizeof(chr_name) / sizeof((chr_name)[0])) + 1];
597
598 dev = qdev_create(NULL((void*)0), TYPE_EXYNOS4210_UART"exynos4210.uart");
599
600 if (!chr) {
601 if (channel >= MAX_SERIAL_PORTS4) {
602 hw_error("Only %d serial ports are supported by QEMU.\n",
603 MAX_SERIAL_PORTS4);
604 }
605 chr = serial_hds[channel];
606 if (!chr) {
607 snprintf(label, ARRAY_SIZE(label)(sizeof(label) / sizeof((label)[0])), "%s%d", chr_name, channel);
608 chr = qemu_chr_new(label, "null", NULL((void*)0));
609 if (!(chr)) {
610 hw_error("Can't assign serial port to UART%d.\n", channel);
611 }
612 }
613 }
614
615 qdev_prop_set_chr(dev, "chardev", chr);
616 qdev_prop_set_uint32(dev, "channel", channel);
617 qdev_prop_set_uint32(dev, "rx-size", fifo_size);
618 qdev_prop_set_uint32(dev, "tx-size", fifo_size);
619
620 bus = SYS_BUS_DEVICE(dev)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((dev)
)), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/char/exynos4210_uart.c"
, 620, __func__));
621 qdev_init_nofail(dev);
622 if (addr != (hwaddr)-1) {
623 sysbus_mmio_map(bus, 0, addr);
624 }
625 sysbus_connect_irq(bus, 0, irq);
626
627 return dev;
628}
629
630static int exynos4210_uart_init(SysBusDevice *dev)
631{
632 Exynos4210UartState *s = EXYNOS4210_UART(dev)((Exynos4210UartState *)object_dynamic_cast_assert(((Object *
)((dev))), ("exynos4210.uart"), "/home/stefan/src/qemu/qemu.org/qemu/hw/char/exynos4210_uart.c"
, 632, __func__));
633
634 /* memory mapping */
635 memory_region_init_io(&s->iomem, OBJECT(s)((Object *)(s)), &exynos4210_uart_ops, s,
636 "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE0x3C);
637 sysbus_init_mmio(dev, &s->iomem);
638
639 sysbus_init_irq(dev, &s->irq);
640
641 qemu_chr_add_handlers(s->chr, exynos4210_uart_can_receive,
642 exynos4210_uart_receive, exynos4210_uart_event, s);
643
644 return 0;
645}
646
647static Property exynos4210_uart_properties[] = {
648 DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr){ .name = ("chardev"), .info = &(qdev_prop_chr), .offset =
__builtin_offsetof(Exynos4210UartState, chr) + ((CharDriverState
**)0 - (typeof(((Exynos4210UartState *)0)->chr)*)0), },
649 DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0){ .name = ("channel"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(Exynos4210UartState, channel) + ((uint32_t
*)0 - (typeof(((Exynos4210UartState *)0)->channel)*)0), .qtype
= QTYPE_QINT, .defval = (uint32_t)0, },
650 DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16){ .name = ("rx-size"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(Exynos4210UartState, rx.size) + ((uint32_t
*)0 - (typeof(((Exynos4210UartState *)0)->rx.size)*)0), .qtype
= QTYPE_QINT, .defval = (uint32_t)16, },
651 DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16){ .name = ("tx-size"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(Exynos4210UartState, tx.size) + ((uint32_t
*)0 - (typeof(((Exynos4210UartState *)0)->tx.size)*)0), .qtype
= QTYPE_QINT, .defval = (uint32_t)16, },
652 DEFINE_PROP_END_OF_LIST(){},
653};
654
655static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
656{
657 DeviceClass *dc = DEVICE_CLASS(klass)((DeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/char/exynos4210_uart.c"
, 657, __func__));
658 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass)((SysBusDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/char/exynos4210_uart.c"
, 658, __func__));
659
660 k->init = exynos4210_uart_init;
661 dc->reset = exynos4210_uart_reset;
662 dc->props = exynos4210_uart_properties;
663 dc->vmsd = &vmstate_exynos4210_uart;
664}
665
666static const TypeInfo exynos4210_uart_info = {
667 .name = TYPE_EXYNOS4210_UART"exynos4210.uart",
668 .parent = TYPE_SYS_BUS_DEVICE"sys-bus-device",
669 .instance_size = sizeof(Exynos4210UartState),
670 .class_init = exynos4210_uart_class_init,
671};
672
673static void exynos4210_uart_register(void)
674{
675 type_register_static(&exynos4210_uart_info);
676}
677
678type_init(exynos4210_uart_register)static void __attribute__((constructor)) do_qemu_init_exynos4210_uart_register
(void) { register_module_init(exynos4210_uart_register, MODULE_INIT_QOM
); }