Bug Summary

File:hw/display/exynos4210_fimd.c
Location:line 1303, column 17
Description:Value stored to 'is_dirty' is never read

Annotated Source Code

1/*
2 * Samsung exynos4210 Display Controller (FIMD)
3 *
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
5 * All rights reserved.
6 * Based on LCD controller for Samsung S5PC1xx-based board emulation
7 * by Kirill Batuzov <batuzovk@ispras.ru>
8 *
9 * Contributed by Mitsyanko Igor <i.mitsyanko@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25#include "qemu-common.h"
26#include "hw/sysbus.h"
27#include "ui/console.h"
28#include "ui/pixel_ops.h"
29#include "qemu/bswap.h"
30
31/* Debug messages configuration */
32#define EXYNOS4210_FIMD_DEBUG0 0
33#define EXYNOS4210_FIMD_MODE_TRACE0 0
34
35#if EXYNOS4210_FIMD_DEBUG0 == 0
36 #define DPRINT_L1(fmt, args...)do { } while (0) do { } while (0)
37 #define DPRINT_L2(fmt, args...)do { } while (0) do { } while (0)
38 #define DPRINT_ERROR(fmt, args...)do { } while (0) do { } while (0)
39#elif EXYNOS4210_FIMD_DEBUG0 == 1
40 #define DPRINT_L1(fmt, args...)do { } while (0) \
41 do {fprintf(stderrstderr, "QEMU FIMD: "fmt, ## args); } while (0)
42 #define DPRINT_L2(fmt, args...)do { } while (0) do { } while (0)
43 #define DPRINT_ERROR(fmt, args...)do { } while (0) \
44 do {fprintf(stderrstderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
45#else
46 #define DPRINT_L1(fmt, args...)do { } while (0) \
47 do {fprintf(stderrstderr, "QEMU FIMD: "fmt, ## args); } while (0)
48 #define DPRINT_L2(fmt, args...)do { } while (0) \
49 do {fprintf(stderrstderr, "QEMU FIMD: "fmt, ## args); } while (0)
50 #define DPRINT_ERROR(fmt, args...)do { } while (0) \
51 do {fprintf(stderrstderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
52#endif
53
54#if EXYNOS4210_FIMD_MODE_TRACE0 == 0
55 #define DPRINT_TRACE(fmt, args...)do { } while (0) do { } while (0)
56#else
57 #define DPRINT_TRACE(fmt, args...)do { } while (0) \
58 do {fprintf(stderrstderr, "QEMU FIMD: "fmt, ## args); } while (0)
59#endif
60
61#define NUM_OF_WINDOWS5 5
62#define FIMD_REGS_SIZE0x4114 0x4114
63
64/* Video main control registers */
65#define FIMD_VIDCON00x0000 0x0000
66#define FIMD_VIDCON10x0004 0x0004
67#define FIMD_VIDCON20x0008 0x0008
68#define FIMD_VIDCON30x000C 0x000C
69#define FIMD_VIDCON0_ENVID_F(1 << 0) (1 << 0)
70#define FIMD_VIDCON0_ENVID(1 << 1) (1 << 1)
71#define FIMD_VIDCON0_ENVID_MASK((1 << 0) | (1 << 1)) ((1 << 0) | (1 << 1))
72#define FIMD_VIDCON1_ROMASK0x07FFE000 0x07FFE000
73
74/* Video time control registers */
75#define FIMD_VIDTCON_START0x10 0x10
76#define FIMD_VIDTCON_END0x1C 0x1C
77#define FIMD_VIDTCON2_SIZE_MASK0x07FF 0x07FF
78#define FIMD_VIDTCON2_HOR_SHIFT0 0
79#define FIMD_VIDTCON2_VER_SHIFT11 11
80
81/* Window control registers */
82#define FIMD_WINCON_START0x0020 0x0020
83#define FIMD_WINCON_END0x0030 0x0030
84#define FIMD_WINCON_ROMASK0x82200000 0x82200000
85#define FIMD_WINCON_ENWIN(1 << 0) (1 << 0)
86#define FIMD_WINCON_BLD_PIX(1 << 6) (1 << 6)
87#define FIMD_WINCON_ALPHA_MUL(1 << 7) (1 << 7)
88#define FIMD_WINCON_ALPHA_SEL(1 << 1) (1 << 1)
89#define FIMD_WINCON_SWAP0x078000 0x078000
90#define FIMD_WINCON_SWAP_SHIFT15 15
91#define FIMD_WINCON_SWAP_WORD0x1 0x1
92#define FIMD_WINCON_SWAP_HWORD0x2 0x2
93#define FIMD_WINCON_SWAP_BYTE0x4 0x4
94#define FIMD_WINCON_SWAP_BITS0x8 0x8
95#define FIMD_WINCON_BUFSTAT_L(1 << 21) (1 << 21)
96#define FIMD_WINCON_BUFSTAT_H(1 << 31) (1 << 31)
97#define FIMD_WINCON_BUFSTATUS((1 << 21) | (1 << 31)) ((1 << 21) | (1 << 31))
98#define FIMD_WINCON_BUF0_STAT((0 << 21) | (0 << 31)) ((0 << 21) | (0 << 31))
99#define FIMD_WINCON_BUF1_STAT((1 << 21) | (0 << 31)) ((1 << 21) | (0 << 31))
100#define FIMD_WINCON_BUF2_STAT((0 << 21) | (1 << 31)) ((0 << 21) | (1 << 31))
101#define FIMD_WINCON_BUFSELECT((1 << 20) | (1 << 30)) ((1 << 20) | (1 << 30))
102#define FIMD_WINCON_BUF0_SEL((0 << 20) | (0 << 30)) ((0 << 20) | (0 << 30))
103#define FIMD_WINCON_BUF1_SEL((1 << 20) | (0 << 30)) ((1 << 20) | (0 << 30))
104#define FIMD_WINCON_BUF2_SEL((0 << 20) | (1 << 30)) ((0 << 20) | (1 << 30))
105#define FIMD_WINCON_BUFMODE(1 << 14) (1 << 14)
106#define IS_PALETTIZED_MODE(w)(w->wincon & 0xC) (w->wincon & 0xC)
107#define PAL_MODE_WITH_ALPHA(x)((x) == 7) ((x) == 7)
108#define WIN_BPP_MODE(w)((w->wincon >> 2) & 0xF) ((w->wincon >> 2) & 0xF)
109#define WIN_BPP_MODE_WITH_ALPHA(w)(((w->wincon >> 2) & 0xF) == 0xD || ((w->wincon
>> 2) & 0xF) == 0xE) \
110 (WIN_BPP_MODE(w)((w->wincon >> 2) & 0xF) == 0xD || WIN_BPP_MODE(w)((w->wincon >> 2) & 0xF) == 0xE)
111
112/* Shadow control register */
113#define FIMD_SHADOWCON0x0034 0x0034
114#define FIMD_WINDOW_PROTECTED(s, w)((s) & (1 << (10 + (w)))) ((s) & (1 << (10 + (w))))
115/* Channel mapping control register */
116#define FIMD_WINCHMAP0x003C 0x003C
117
118/* Window position control registers */
119#define FIMD_VIDOSD_START0x0040 0x0040
120#define FIMD_VIDOSD_END0x0088 0x0088
121#define FIMD_VIDOSD_COORD_MASK0x07FF 0x07FF
122#define FIMD_VIDOSD_HOR_SHIFT11 11
123#define FIMD_VIDOSD_VER_SHIFT0 0
124#define FIMD_VIDOSD_ALPHA_AEN00xFFF000 0xFFF000
125#define FIMD_VIDOSD_AEN0_SHIFT12 12
126#define FIMD_VIDOSD_ALPHA_AEN10x000FFF 0x000FFF
127
128/* Frame buffer address registers */
129#define FIMD_VIDWADD0_START0x00A0 0x00A0
130#define FIMD_VIDWADD0_END0x00C4 0x00C4
131#define FIMD_VIDWADD0_END0x00C4 0x00C4
132#define FIMD_VIDWADD1_START0x00D0 0x00D0
133#define FIMD_VIDWADD1_END0x00F4 0x00F4
134#define FIMD_VIDWADD2_START0x0100 0x0100
135#define FIMD_VIDWADD2_END0x0110 0x0110
136#define FIMD_VIDWADD2_PAGEWIDTH0x1FFF 0x1FFF
137#define FIMD_VIDWADD2_OFFSIZE0x1FFF 0x1FFF
138#define FIMD_VIDWADD2_OFFSIZE_SHIFT13 13
139#define FIMD_VIDW0ADD0_B20x20A0 0x20A0
140#define FIMD_VIDW4ADD0_B20x20C0 0x20C0
141
142/* Video interrupt control registers */
143#define FIMD_VIDINTCON00x130 0x130
144#define FIMD_VIDINTCON10x134 0x134
145
146/* Window color key registers */
147#define FIMD_WKEYCON_START0x140 0x140
148#define FIMD_WKEYCON_END0x15C 0x15C
149#define FIMD_WKEYCON0_COMPKEY0x00FFFFFF 0x00FFFFFF
150#define FIMD_WKEYCON0_CTL_SHIFT24 24
151#define FIMD_WKEYCON0_DIRCON(1 << 24) (1 << 24)
152#define FIMD_WKEYCON0_KEYEN(1 << 25) (1 << 25)
153#define FIMD_WKEYCON0_KEYBLEN(1 << 26) (1 << 26)
154/* Window color key alpha control register */
155#define FIMD_WKEYALPHA_START0x160 0x160
156#define FIMD_WKEYALPHA_END0x16C 0x16C
157
158/* Dithering control register */
159#define FIMD_DITHMODE0x170 0x170
160
161/* Window alpha control registers */
162#define FIMD_VIDALPHA_ALPHA_LOWER0x000F0F0F 0x000F0F0F
163#define FIMD_VIDALPHA_ALPHA_UPPER0x00F0F0F0 0x00F0F0F0
164#define FIMD_VIDWALPHA_START0x21C 0x21C
165#define FIMD_VIDWALPHA_END0x240 0x240
166
167/* Window color map registers */
168#define FIMD_WINMAP_START0x180 0x180
169#define FIMD_WINMAP_END0x190 0x190
170#define FIMD_WINMAP_EN(1 << 24) (1 << 24)
171#define FIMD_WINMAP_COLOR_MASK0x00FFFFFF 0x00FFFFFF
172
173/* Window palette control registers */
174#define FIMD_WPALCON_HIGH0x019C 0x019C
175#define FIMD_WPALCON_LOW0x01A0 0x01A0
176#define FIMD_WPALCON_UPDATEEN(1 << 9) (1 << 9)
177#define FIMD_WPAL_W0PAL_L0x07 0x07
178#define FIMD_WPAL_W0PAL_L_SHT0 0
179#define FIMD_WPAL_W1PAL_L0x07 0x07
180#define FIMD_WPAL_W1PAL_L_SHT3 3
181#define FIMD_WPAL_W2PAL_L0x01 0x01
182#define FIMD_WPAL_W2PAL_L_SHT6 6
183#define FIMD_WPAL_W2PAL_H0x06 0x06
184#define FIMD_WPAL_W2PAL_H_SHT8 8
185#define FIMD_WPAL_W3PAL_L0x01 0x01
186#define FIMD_WPAL_W3PAL_L_SHT7 7
187#define FIMD_WPAL_W3PAL_H0x06 0x06
188#define FIMD_WPAL_W3PAL_H_SHT12 12
189#define FIMD_WPAL_W4PAL_L0x01 0x01
190#define FIMD_WPAL_W4PAL_L_SHT8 8
191#define FIMD_WPAL_W4PAL_H0x06 0x06
192#define FIMD_WPAL_W4PAL_H_SHT16 16
193
194/* Trigger control registers */
195#define FIMD_TRIGCON0x01A4 0x01A4
196#define FIMD_TRIGCON_ROMASK0x00000004 0x00000004
197
198/* LCD I80 Interface Control */
199#define FIMD_I80IFCON_START0x01B0 0x01B0
200#define FIMD_I80IFCON_END0x01BC 0x01BC
201/* Color gain control register */
202#define FIMD_COLORGAINCON0x01C0 0x01C0
203/* LCD i80 Interface Command Control */
204#define FIMD_LDI_CMDCON00x01D0 0x01D0
205#define FIMD_LDI_CMDCON10x01D4 0x01D4
206/* I80 System Interface Manual Command Control */
207#define FIMD_SIFCCON00x01E0 0x01E0
208#define FIMD_SIFCCON20x01E8 0x01E8
209
210/* Hue Control Registers */
211#define FIMD_HUECOEFCR_START0x01EC 0x01EC
212#define FIMD_HUECOEFCR_END0x01F4 0x01F4
213#define FIMD_HUECOEFCB_START0x01FC 0x01FC
214#define FIMD_HUECOEFCB_END0x0208 0x0208
215#define FIMD_HUEOFFSET0x020C 0x020C
216
217/* Video interrupt control registers */
218#define FIMD_VIDINT_INTFIFOPEND(1 << 0) (1 << 0)
219#define FIMD_VIDINT_INTFRMPEND(1 << 1) (1 << 1)
220#define FIMD_VIDINT_INTI80PEND(1 << 2) (1 << 2)
221#define FIMD_VIDINT_INTEN(1 << 0) (1 << 0)
222#define FIMD_VIDINT_INTFIFOEN(1 << 1) (1 << 1)
223#define FIMD_VIDINT_INTFRMEN(1 << 12) (1 << 12)
224#define FIMD_VIDINT_I80IFDONE(1 << 17) (1 << 17)
225
226/* Window blend equation control registers */
227#define FIMD_BLENDEQ_START0x0244 0x0244
228#define FIMD_BLENDEQ_END0x0250 0x0250
229#define FIMD_BLENDCON0x0260 0x0260
230#define FIMD_ALPHA_8BIT(1 << 0) (1 << 0)
231#define FIMD_BLENDEQ_COEF_MASK0xF 0xF
232
233/* Window RTQOS Control Registers */
234#define FIMD_WRTQOSCON_START0x0264 0x0264
235#define FIMD_WRTQOSCON_END0x0274 0x0274
236
237/* LCD I80 Interface Command */
238#define FIMD_I80IFCMD_START0x0280 0x0280
239#define FIMD_I80IFCMD_END0x02AC 0x02AC
240
241/* Shadow windows control registers */
242#define FIMD_SHD_ADD0_START0x40A0 0x40A0
243#define FIMD_SHD_ADD0_END0x40C0 0x40C0
244#define FIMD_SHD_ADD1_START0x40D0 0x40D0
245#define FIMD_SHD_ADD1_END0x40F0 0x40F0
246#define FIMD_SHD_ADD2_START0x4100 0x4100
247#define FIMD_SHD_ADD2_END0x4110 0x4110
248
249/* Palette memory */
250#define FIMD_PAL_MEM_START0x2400 0x2400
251#define FIMD_PAL_MEM_END0x37FC 0x37FC
252/* Palette memory aliases for windows 0 and 1 */
253#define FIMD_PALMEM_AL_START0x0400 0x0400
254#define FIMD_PALMEM_AL_END0x0BFC 0x0BFC
255
256typedef struct {
257 uint8_t r, g, b;
258 /* D[31..24]dummy, D[23..16]rAlpha, D[15..8]gAlpha, D[7..0]bAlpha */
259 uint32_t a;
260} rgba;
261#define RGBA_SIZE7 7
262
263typedef void pixel_to_rgb_func(uint32_t pixel, rgba *p);
264typedef struct Exynos4210fimdWindow Exynos4210fimdWindow;
265
266struct Exynos4210fimdWindow {
267 uint32_t wincon; /* Window control register */
268 uint32_t buf_start[3]; /* Start address for video frame buffer */
269 uint32_t buf_end[3]; /* End address for video frame buffer */
270 uint32_t keycon[2]; /* Window color key registers */
271 uint32_t keyalpha; /* Color key alpha control register */
272 uint32_t winmap; /* Window color map register */
273 uint32_t blendeq; /* Window blending equation control register */
274 uint32_t rtqoscon; /* Window RTQOS Control Registers */
275 uint32_t palette[256]; /* Palette RAM */
276 uint32_t shadow_buf_start; /* Start address of shadow frame buffer */
277 uint32_t shadow_buf_end; /* End address of shadow frame buffer */
278 uint32_t shadow_buf_size; /* Virtual shadow screen width */
279
280 pixel_to_rgb_func *pixel_to_rgb;
281 void (*draw_line)(Exynos4210fimdWindow *w, uint8_t *src, uint8_t *dst,
282 bool_Bool blend);
283 uint32_t (*get_alpha)(Exynos4210fimdWindow *w, uint32_t pix_a);
284 uint16_t lefttop_x, lefttop_y; /* VIDOSD0 register */
285 uint16_t rightbot_x, rightbot_y; /* VIDOSD1 register */
286 uint32_t osdsize; /* VIDOSD2&3 register */
287 uint32_t alpha_val[2]; /* VIDOSD2&3, VIDWALPHA registers */
288 uint16_t virtpage_width; /* VIDWADD2 register */
289 uint16_t virtpage_offsize; /* VIDWADD2 register */
290 MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */
291 uint8_t *host_fb_addr; /* Host pointer to window's framebuffer */
292 hwaddr fb_len; /* Framebuffer length */
293};
294
295#define TYPE_EXYNOS4210_FIMD"exynos4210.fimd" "exynos4210.fimd"
296#define EXYNOS4210_FIMD(obj)((Exynos4210fimdState *)object_dynamic_cast_assert(((Object *
)((obj))), ("exynos4210.fimd"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/exynos4210_fimd.c"
, 296, __func__)) \
297 OBJECT_CHECK(Exynos4210fimdState, (obj), TYPE_EXYNOS4210_FIMD)((Exynos4210fimdState *)object_dynamic_cast_assert(((Object *
)((obj))), ("exynos4210.fimd"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/exynos4210_fimd.c"
, 297, __func__))
298
299typedef struct {
300 SysBusDevice parent_obj;
301
302 MemoryRegion iomem;
303 QemuConsole *console;
304 qemu_irq irq[3];
305
306 uint32_t vidcon[4]; /* Video main control registers 0-3 */
307 uint32_t vidtcon[4]; /* Video time control registers 0-3 */
308 uint32_t shadowcon; /* Window shadow control register */
309 uint32_t winchmap; /* Channel mapping control register */
310 uint32_t vidintcon[2]; /* Video interrupt control registers */
311 uint32_t dithmode; /* Dithering control register */
312 uint32_t wpalcon[2]; /* Window palette control registers */
313 uint32_t trigcon; /* Trigger control register */
314 uint32_t i80ifcon[4]; /* I80 interface control registers */
315 uint32_t colorgaincon; /* Color gain control register */
316 uint32_t ldi_cmdcon[2]; /* LCD I80 interface command control */
317 uint32_t sifccon[3]; /* I80 System Interface Manual Command Control */
318 uint32_t huecoef_cr[4]; /* Hue control registers */
319 uint32_t huecoef_cb[4]; /* Hue control registers */
320 uint32_t hueoffset; /* Hue offset control register */
321 uint32_t blendcon; /* Blending control register */
322 uint32_t i80ifcmd[12]; /* LCD I80 Interface Command */
323
324 Exynos4210fimdWindow window[5]; /* Window-specific registers */
325 uint8_t *ifb; /* Internal frame buffer */
326 bool_Bool invalidate; /* Image needs to be redrawn */
327 bool_Bool enabled; /* Display controller is enabled */
328} Exynos4210fimdState;
329
330/* Perform byte/halfword/word swap of data according to WINCON */
331static inline void fimd_swap_data(unsigned int swap_ctl, uint64_t *data)
332{
333 int i;
334 uint64_t res;
335 uint64_t x = *data;
336
337 if (swap_ctl & FIMD_WINCON_SWAP_BITS0x8) {
338 res = 0;
339 for (i = 0; i < 64; i++) {
340 if (x & (1ULL << (64 - i))) {
341 res |= (1ULL << i);
342 }
343 }
344 x = res;
345 }
346
347 if (swap_ctl & FIMD_WINCON_SWAP_BYTE0x4) {
348 x = bswap64(x);
349 }
350
351 if (swap_ctl & FIMD_WINCON_SWAP_HWORD0x2) {
352 x = ((x & 0x000000000000FFFFULL) << 48) |
353 ((x & 0x00000000FFFF0000ULL) << 16) |
354 ((x & 0x0000FFFF00000000ULL) >> 16) |
355 ((x & 0xFFFF000000000000ULL) >> 48);
356 }
357
358 if (swap_ctl & FIMD_WINCON_SWAP_WORD0x1) {
359 x = ((x & 0x00000000FFFFFFFFULL) << 32) |
360 ((x & 0xFFFFFFFF00000000ULL) >> 32);
361 }
362
363 *data = x;
364}
365
366/* Conversion routines of Pixel data from frame buffer area to internal RGBA
367 * pixel representation.
368 * Every color component internally represented as 8-bit value. If original
369 * data has less than 8 bit for component, data is extended to 8 bit. For
370 * example, if blue component has only two possible values 0 and 1 it will be
371 * extended to 0 and 0xFF */
372
373/* One bit for alpha representation */
374#define DEF_PIXEL_TO_RGB_A1(N, R, G, B)static void N(uint32_t pixel, rgba *p) { p->b = ((pixel &
((1 << (B)) - 1)) << (8 - (B))) | ((pixel >>
(2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); pixel >>=
(B); p->g = (pixel & ((1 << (G)) - 1)) <<
(8 - (G)) | ((pixel >> (2 * (G) - 8)) & ((1 <<
(8 - (G))) - 1)); pixel >>= (G); p->r = (pixel &
((1 << (R)) - 1)) << (8 - (R)) | ((pixel >>
(2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); pixel >>=
(R); p->a = (pixel & 0x1); } \
375static void N(uint32_t pixel, rgba *p) \
376{ \
377 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
378 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
379 pixel >>= (B); \
380 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
381 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
382 pixel >>= (G); \
383 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
384 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
385 pixel >>= (R); \
386 p->a = (pixel & 0x1); \
387}
388
389DEF_PIXEL_TO_RGB_A1(pixel_a444_to_rgb, 4, 4, 4)static void pixel_a444_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (4)) - 1)) << (8 - (4)))
| ((pixel >> (2 * (4) - 8)) & ((1 << (8 - (4
))) - 1)); pixel >>= (4); p->g = (pixel & ((1 <<
(4)) - 1)) << (8 - (4)) | ((pixel >> (2 * (4) - 8
)) & ((1 << (8 - (4))) - 1)); pixel >>= (4); p
->r = (pixel & ((1 << (4)) - 1)) << (8 - (
4)) | ((pixel >> (2 * (4) - 8)) & ((1 << (8 -
(4))) - 1)); pixel >>= (4); p->a = (pixel & 0x1
); }
390DEF_PIXEL_TO_RGB_A1(pixel_a555_to_rgb, 5, 5, 5)static void pixel_a555_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (5)) - 1)) << (8 - (5)))
| ((pixel >> (2 * (5) - 8)) & ((1 << (8 - (5
))) - 1)); pixel >>= (5); p->g = (pixel & ((1 <<
(5)) - 1)) << (8 - (5)) | ((pixel >> (2 * (5) - 8
)) & ((1 << (8 - (5))) - 1)); pixel >>= (5); p
->r = (pixel & ((1 << (5)) - 1)) << (8 - (
5)) | ((pixel >> (2 * (5) - 8)) & ((1 << (8 -
(5))) - 1)); pixel >>= (5); p->a = (pixel & 0x1
); }
391DEF_PIXEL_TO_RGB_A1(pixel_a666_to_rgb, 6, 6, 6)static void pixel_a666_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (6)) - 1)) << (8 - (6)))
| ((pixel >> (2 * (6) - 8)) & ((1 << (8 - (6
))) - 1)); pixel >>= (6); p->g = (pixel & ((1 <<
(6)) - 1)) << (8 - (6)) | ((pixel >> (2 * (6) - 8
)) & ((1 << (8 - (6))) - 1)); pixel >>= (6); p
->r = (pixel & ((1 << (6)) - 1)) << (8 - (
6)) | ((pixel >> (2 * (6) - 8)) & ((1 << (8 -
(6))) - 1)); pixel >>= (6); p->a = (pixel & 0x1
); }
392DEF_PIXEL_TO_RGB_A1(pixel_a665_to_rgb, 6, 6, 5)static void pixel_a665_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (5)) - 1)) << (8 - (5)))
| ((pixel >> (2 * (5) - 8)) & ((1 << (8 - (5
))) - 1)); pixel >>= (5); p->g = (pixel & ((1 <<
(6)) - 1)) << (8 - (6)) | ((pixel >> (2 * (6) - 8
)) & ((1 << (8 - (6))) - 1)); pixel >>= (6); p
->r = (pixel & ((1 << (6)) - 1)) << (8 - (
6)) | ((pixel >> (2 * (6) - 8)) & ((1 << (8 -
(6))) - 1)); pixel >>= (6); p->a = (pixel & 0x1
); }
393DEF_PIXEL_TO_RGB_A1(pixel_a888_to_rgb, 8, 8, 8)static void pixel_a888_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (8)) - 1)) << (8 - (8)))
| ((pixel >> (2 * (8) - 8)) & ((1 << (8 - (8
))) - 1)); pixel >>= (8); p->g = (pixel & ((1 <<
(8)) - 1)) << (8 - (8)) | ((pixel >> (2 * (8) - 8
)) & ((1 << (8 - (8))) - 1)); pixel >>= (8); p
->r = (pixel & ((1 << (8)) - 1)) << (8 - (
8)) | ((pixel >> (2 * (8) - 8)) & ((1 << (8 -
(8))) - 1)); pixel >>= (8); p->a = (pixel & 0x1
); }
394DEF_PIXEL_TO_RGB_A1(pixel_a887_to_rgb, 8, 8, 7)static void pixel_a887_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (7)) - 1)) << (8 - (7)))
| ((pixel >> (2 * (7) - 8)) & ((1 << (8 - (7
))) - 1)); pixel >>= (7); p->g = (pixel & ((1 <<
(8)) - 1)) << (8 - (8)) | ((pixel >> (2 * (8) - 8
)) & ((1 << (8 - (8))) - 1)); pixel >>= (8); p
->r = (pixel & ((1 << (8)) - 1)) << (8 - (
8)) | ((pixel >> (2 * (8) - 8)) & ((1 << (8 -
(8))) - 1)); pixel >>= (8); p->a = (pixel & 0x1
); }
395
396/* Alpha component is always zero */
397#define DEF_PIXEL_TO_RGB_A0(N, R, G, B)static void N(uint32_t pixel, rgba *p) { p->b = ((pixel &
((1 << (B)) - 1)) << (8 - (B))) | ((pixel >>
(2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); pixel >>=
(B); p->g = (pixel & ((1 << (G)) - 1)) <<
(8 - (G)) | ((pixel >> (2 * (G) - 8)) & ((1 <<
(8 - (G))) - 1)); pixel >>= (G); p->r = (pixel &
((1 << (R)) - 1)) << (8 - (R)) | ((pixel >>
(2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); p->a =
0x0; } \
398static void N(uint32_t pixel, rgba *p) \
399{ \
400 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
401 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
402 pixel >>= (B); \
403 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
404 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
405 pixel >>= (G); \
406 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
407 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
408 p->a = 0x0; \
409}
410
411DEF_PIXEL_TO_RGB_A0(pixel_565_to_rgb, 5, 6, 5)static void pixel_565_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (5)) - 1)) << (8 - (5)))
| ((pixel >> (2 * (5) - 8)) & ((1 << (8 - (5
))) - 1)); pixel >>= (5); p->g = (pixel & ((1 <<
(6)) - 1)) << (8 - (6)) | ((pixel >> (2 * (6) - 8
)) & ((1 << (8 - (6))) - 1)); pixel >>= (6); p
->r = (pixel & ((1 << (5)) - 1)) << (8 - (
5)) | ((pixel >> (2 * (5) - 8)) & ((1 << (8 -
(5))) - 1)); p->a = 0x0; }
412DEF_PIXEL_TO_RGB_A0(pixel_555_to_rgb, 5, 5, 5)static void pixel_555_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (5)) - 1)) << (8 - (5)))
| ((pixel >> (2 * (5) - 8)) & ((1 << (8 - (5
))) - 1)); pixel >>= (5); p->g = (pixel & ((1 <<
(5)) - 1)) << (8 - (5)) | ((pixel >> (2 * (5) - 8
)) & ((1 << (8 - (5))) - 1)); pixel >>= (5); p
->r = (pixel & ((1 << (5)) - 1)) << (8 - (
5)) | ((pixel >> (2 * (5) - 8)) & ((1 << (8 -
(5))) - 1)); p->a = 0x0; }
413DEF_PIXEL_TO_RGB_A0(pixel_666_to_rgb, 6, 6, 6)static void pixel_666_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (6)) - 1)) << (8 - (6)))
| ((pixel >> (2 * (6) - 8)) & ((1 << (8 - (6
))) - 1)); pixel >>= (6); p->g = (pixel & ((1 <<
(6)) - 1)) << (8 - (6)) | ((pixel >> (2 * (6) - 8
)) & ((1 << (8 - (6))) - 1)); pixel >>= (6); p
->r = (pixel & ((1 << (6)) - 1)) << (8 - (
6)) | ((pixel >> (2 * (6) - 8)) & ((1 << (8 -
(6))) - 1)); p->a = 0x0; }
414DEF_PIXEL_TO_RGB_A0(pixel_888_to_rgb, 8, 8, 8)static void pixel_888_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (8)) - 1)) << (8 - (8)))
| ((pixel >> (2 * (8) - 8)) & ((1 << (8 - (8
))) - 1)); pixel >>= (8); p->g = (pixel & ((1 <<
(8)) - 1)) << (8 - (8)) | ((pixel >> (2 * (8) - 8
)) & ((1 << (8 - (8))) - 1)); pixel >>= (8); p
->r = (pixel & ((1 << (8)) - 1)) << (8 - (
8)) | ((pixel >> (2 * (8) - 8)) & ((1 << (8 -
(8))) - 1)); p->a = 0x0; }
415
416/* Alpha component has some meaningful value */
417#define DEF_PIXEL_TO_RGB_A(N, R, G, B, A)static void N(uint32_t pixel, rgba *p) { p->b = ((pixel &
((1 << (B)) - 1)) << (8 - (B))) | ((pixel >>
(2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); pixel >>=
(B); p->g = (pixel & ((1 << (G)) - 1)) <<
(8 - (G)) | ((pixel >> (2 * (G) - 8)) & ((1 <<
(8 - (G))) - 1)); pixel >>= (G); p->r = (pixel &
((1 << (R)) - 1)) << (8 - (R)) | ((pixel >>
(2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); pixel >>=
(R); p->a = (pixel & ((1 << (A)) - 1)) <<
(8 - (A)) | ((pixel >> (2 * (A) - 8)) & ((1 <<
(8 - (A))) - 1)); p->a = p->a | (p->a << 8) |
(p->a << 16); } \
418static void N(uint32_t pixel, rgba *p) \
419{ \
420 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
421 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
422 pixel >>= (B); \
423 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
424 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
425 pixel >>= (G); \
426 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
427 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
428 pixel >>= (R); \
429 p->a = (pixel & ((1 << (A)) - 1)) << (8 - (A)) | \
430 ((pixel >> (2 * (A) - 8)) & ((1 << (8 - (A))) - 1)); \
431 p->a = p->a | (p->a << 8) | (p->a << 16); \
432}
433
434DEF_PIXEL_TO_RGB_A(pixel_4444_to_rgb, 4, 4, 4, 4)static void pixel_4444_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (4)) - 1)) << (8 - (4)))
| ((pixel >> (2 * (4) - 8)) & ((1 << (8 - (4
))) - 1)); pixel >>= (4); p->g = (pixel & ((1 <<
(4)) - 1)) << (8 - (4)) | ((pixel >> (2 * (4) - 8
)) & ((1 << (8 - (4))) - 1)); pixel >>= (4); p
->r = (pixel & ((1 << (4)) - 1)) << (8 - (
4)) | ((pixel >> (2 * (4) - 8)) & ((1 << (8 -
(4))) - 1)); pixel >>= (4); p->a = (pixel & ((1
<< (4)) - 1)) << (8 - (4)) | ((pixel >> (2
* (4) - 8)) & ((1 << (8 - (4))) - 1)); p->a = p
->a | (p->a << 8) | (p->a << 16); }
435DEF_PIXEL_TO_RGB_A(pixel_8888_to_rgb, 8, 8, 8, 8)static void pixel_8888_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (8)) - 1)) << (8 - (8)))
| ((pixel >> (2 * (8) - 8)) & ((1 << (8 - (8
))) - 1)); pixel >>= (8); p->g = (pixel & ((1 <<
(8)) - 1)) << (8 - (8)) | ((pixel >> (2 * (8) - 8
)) & ((1 << (8 - (8))) - 1)); pixel >>= (8); p
->r = (pixel & ((1 << (8)) - 1)) << (8 - (
8)) | ((pixel >> (2 * (8) - 8)) & ((1 << (8 -
(8))) - 1)); pixel >>= (8); p->a = (pixel & ((1
<< (8)) - 1)) << (8 - (8)) | ((pixel >> (2
* (8) - 8)) & ((1 << (8 - (8))) - 1)); p->a = p
->a | (p->a << 8) | (p->a << 16); }
436
437/* Lookup table to extent 2-bit color component to 8 bit */
438static const uint8_t pixel_lutable_2b[4] = {
439 0x0, 0x55, 0xAA, 0xFF
440};
441/* Lookup table to extent 3-bit color component to 8 bit */
442static const uint8_t pixel_lutable_3b[8] = {
443 0x0, 0x24, 0x49, 0x6D, 0x92, 0xB6, 0xDB, 0xFF
444};
445/* Special case for a232 bpp mode */
446static void pixel_a232_to_rgb(uint32_t pixel, rgba *p)
447{
448 p->b = pixel_lutable_2b[(pixel & 0x3)];
449 pixel >>= 2;
450 p->g = pixel_lutable_3b[(pixel & 0x7)];
451 pixel >>= 3;
452 p->r = pixel_lutable_2b[(pixel & 0x3)];
453 pixel >>= 2;
454 p->a = (pixel & 0x1);
455}
456
457/* Special case for (5+1, 5+1, 5+1) mode. Data bit 15 is common LSB
458 * for all three color components */
459static void pixel_1555_to_rgb(uint32_t pixel, rgba *p)
460{
461 uint8_t comm = (pixel >> 15) & 1;
462 p->b = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
463 pixel >>= 5;
464 p->g = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
465 pixel >>= 5;
466 p->r = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
467 p->a = 0x0;
468}
469
470/* Put/get pixel to/from internal LCD Controller framebuffer */
471
472static int put_pixel_ifb(const rgba p, uint8_t *d)
473{
474 *(uint8_t *)d++ = p.r;
475 *(uint8_t *)d++ = p.g;
476 *(uint8_t *)d++ = p.b;
477 *(uint32_t *)d = p.a;
478 return RGBA_SIZE7;
479}
480
481static int get_pixel_ifb(const uint8_t *s, rgba *p)
482{
483 p->r = *(uint8_t *)s++;
484 p->g = *(uint8_t *)s++;
485 p->b = *(uint8_t *)s++;
486 p->a = (*(uint32_t *)s) & 0x00FFFFFF;
487 return RGBA_SIZE7;
488}
489
490static pixel_to_rgb_func *palette_data_format[8] = {
491 [0] = pixel_565_to_rgb,
492 [1] = pixel_a555_to_rgb,
493 [2] = pixel_666_to_rgb,
494 [3] = pixel_a665_to_rgb,
495 [4] = pixel_a666_to_rgb,
496 [5] = pixel_888_to_rgb,
497 [6] = pixel_a888_to_rgb,
498 [7] = pixel_8888_to_rgb
499};
500
501/* Returns Index in palette data formats table for given window number WINDOW */
502static uint32_t
503exynos4210_fimd_palette_format(Exynos4210fimdState *s, int window)
504{
505 uint32_t ret;
506
507 switch (window) {
508 case 0:
509 ret = (s->wpalcon[1] >> FIMD_WPAL_W0PAL_L_SHT0) & FIMD_WPAL_W0PAL_L0x07;
510 if (ret != 7) {
511 ret = 6 - ret;
512 }
513 break;
514 case 1:
515 ret = (s->wpalcon[1] >> FIMD_WPAL_W1PAL_L_SHT3) & FIMD_WPAL_W1PAL_L0x07;
516 if (ret != 7) {
517 ret = 6 - ret;
518 }
519 break;
520 case 2:
521 ret = ((s->wpalcon[0] >> FIMD_WPAL_W2PAL_H_SHT8) & FIMD_WPAL_W2PAL_H0x06) |
522 ((s->wpalcon[1] >> FIMD_WPAL_W2PAL_L_SHT6) & FIMD_WPAL_W2PAL_L0x01);
523 break;
524 case 3:
525 ret = ((s->wpalcon[0] >> FIMD_WPAL_W3PAL_H_SHT12) & FIMD_WPAL_W3PAL_H0x06) |
526 ((s->wpalcon[1] >> FIMD_WPAL_W3PAL_L_SHT7) & FIMD_WPAL_W3PAL_L0x01);
527 break;
528 case 4:
529 ret = ((s->wpalcon[0] >> FIMD_WPAL_W4PAL_H_SHT16) & FIMD_WPAL_W4PAL_H0x06) |
530 ((s->wpalcon[1] >> FIMD_WPAL_W4PAL_L_SHT8) & FIMD_WPAL_W4PAL_L0x01);
531 break;
532 default:
533 hw_error("exynos4210.fimd: incorrect window number %d\n", window);
534 ret = 0;
535 break;
536 }
537 return ret;
538}
539
540#define FIMD_1_MINUS_COLOR(x)((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | (
0xFF0000 - ((x) & 0xFF0000))) \
541 ((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | \
542 (0xFF0000 - ((x) & 0xFF0000)))
543#define EXTEND_LOWER_HALFBYTE(x)(((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0)) (((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0))
544#define EXTEND_UPPER_HALFBYTE(x)(((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F)) (((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F))
545
546/* Multiply three lower bytes of two 32-bit words with each other.
547 * Each byte with values 0-255 is considered as a number with possible values
548 * in a range [0 - 1] */
549static inline uint32_t fimd_mult_each_byte(uint32_t a, uint32_t b)
550{
551 uint32_t tmp;
552 uint32_t ret;
553
554 ret = ((tmp = (((a & 0xFF) * (b & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF : tmp;
555 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF)) / 0xFF)) > 0xFF) ?
556 0xFF00 : tmp << 8;
557 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
558 0xFF0000 : tmp << 16;
559 return ret;
560}
561
562/* For each corresponding bytes of two 32-bit words: (a*b + c*d)
563 * Byte values 0-255 are mapped to a range [0 .. 1] */
564static inline uint32_t
565fimd_mult_and_sum_each_byte(uint32_t a, uint32_t b, uint32_t c, uint32_t d)
566{
567 uint32_t tmp;
568 uint32_t ret;
569
570 ret = ((tmp = (((a & 0xFF) * (b & 0xFF) + (c & 0xFF) * (d & 0xFF)) / 0xFF))
571 > 0xFF) ? 0xFF : tmp;
572 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF) + ((c >> 8) & 0xFF) *
573 ((d >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF00 : tmp << 8;
574 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF) +
575 ((c >> 16) & 0xFF) * ((d >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
576 0xFF0000 : tmp << 16;
577 return ret;
578}
579
580/* These routines cover all possible sources of window's transparent factor
581 * used in blending equation. Choice of routine is affected by WPALCON
582 * registers, BLENDCON register and window's WINCON register */
583
584static uint32_t fimd_get_alpha_pix(Exynos4210fimdWindow *w, uint32_t pix_a)
585{
586 return pix_a;
587}
588
589static uint32_t
590fimd_get_alpha_pix_extlow(Exynos4210fimdWindow *w, uint32_t pix_a)
591{
592 return EXTEND_LOWER_HALFBYTE(pix_a)(((pix_a) & 0xF0F0F) | (((pix_a) << 4) & 0xF0F0F0
));
593}
594
595static uint32_t
596fimd_get_alpha_pix_exthigh(Exynos4210fimdWindow *w, uint32_t pix_a)
597{
598 return EXTEND_UPPER_HALFBYTE(pix_a)(((pix_a) & 0xF0F0F0) | (((pix_a) >> 4) & 0xF0F0F
));
599}
600
601static uint32_t fimd_get_alpha_mult(Exynos4210fimdWindow *w, uint32_t pix_a)
602{
603 return fimd_mult_each_byte(pix_a, w->alpha_val[0]);
604}
605
606static uint32_t fimd_get_alpha_mult_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
607{
608 return fimd_mult_each_byte(EXTEND_LOWER_HALFBYTE(pix_a)(((pix_a) & 0xF0F0F) | (((pix_a) << 4) & 0xF0F0F0
)),
609 EXTEND_UPPER_HALFBYTE(w->alpha_val[0])(((w->alpha_val[0]) & 0xF0F0F0) | (((w->alpha_val[0
]) >> 4) & 0xF0F0F)));
610}
611
612static uint32_t fimd_get_alpha_aen(Exynos4210fimdWindow *w, uint32_t pix_a)
613{
614 return w->alpha_val[pix_a];
615}
616
617static uint32_t fimd_get_alpha_aen_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
618{
619 return EXTEND_UPPER_HALFBYTE(w->alpha_val[pix_a])(((w->alpha_val[pix_a]) & 0xF0F0F0) | (((w->alpha_val
[pix_a]) >> 4) & 0xF0F0F));
620}
621
622static uint32_t fimd_get_alpha_sel(Exynos4210fimdWindow *w, uint32_t pix_a)
623{
624 return w->alpha_val[(w->wincon & FIMD_WINCON_ALPHA_SEL(1 << 1)) ? 1 : 0];
625}
626
627static uint32_t fimd_get_alpha_sel_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
628{
629 return EXTEND_UPPER_HALFBYTE(w->alpha_val[(w->wincon &(((w->alpha_val[(w->wincon & (1 << 1)) ? 1 : 0
]) & 0xF0F0F0) | (((w->alpha_val[(w->wincon & (
1 << 1)) ? 1 : 0]) >> 4) & 0xF0F0F))
630 FIMD_WINCON_ALPHA_SEL) ? 1 : 0])(((w->alpha_val[(w->wincon & (1 << 1)) ? 1 : 0
]) & 0xF0F0F0) | (((w->alpha_val[(w->wincon & (
1 << 1)) ? 1 : 0]) >> 4) & 0xF0F0F));
631}
632
633/* Updates currently active alpha value get function for specified window */
634static void fimd_update_get_alpha(Exynos4210fimdState *s, int win)
635{
636 Exynos4210fimdWindow *w = &s->window[win];
637 const bool_Bool alpha_is_8bit = s->blendcon & FIMD_ALPHA_8BIT(1 << 0);
638
639 if (w->wincon & FIMD_WINCON_BLD_PIX(1 << 6)) {
640 if ((w->wincon & FIMD_WINCON_ALPHA_SEL(1 << 1)) && WIN_BPP_MODE_WITH_ALPHA(w)(((w->wincon >> 2) & 0xF) == 0xD || ((w->wincon
>> 2) & 0xF) == 0xE)) {
641 /* In this case, alpha component contains meaningful value */
642 if (w->wincon & FIMD_WINCON_ALPHA_MUL(1 << 7)) {
643 w->get_alpha = alpha_is_8bit ?
644 fimd_get_alpha_mult : fimd_get_alpha_mult_ext;
645 } else {
646 w->get_alpha = alpha_is_8bit ?
647 fimd_get_alpha_pix : fimd_get_alpha_pix_extlow;
648 }
649 } else {
650 if (IS_PALETTIZED_MODE(w)(w->wincon & 0xC) &&
651 PAL_MODE_WITH_ALPHA(exynos4210_fimd_palette_format(s, win))((exynos4210_fimd_palette_format(s, win)) == 7)) {
652 /* Alpha component has 8-bit numeric value */
653 w->get_alpha = alpha_is_8bit ?
654 fimd_get_alpha_pix : fimd_get_alpha_pix_exthigh;
655 } else {
656 /* Alpha has only two possible values (AEN) */
657 w->get_alpha = alpha_is_8bit ?
658 fimd_get_alpha_aen : fimd_get_alpha_aen_ext;
659 }
660 }
661 } else {
662 w->get_alpha = alpha_is_8bit ? fimd_get_alpha_sel :
663 fimd_get_alpha_sel_ext;
664 }
665}
666
667/* Blends current window's (w) pixel (foreground pixel *ret) with background
668 * window (w_blend) pixel p_bg according to formula:
669 * NEW_COLOR = a_coef x FG_PIXEL_COLOR + b_coef x BG_PIXEL_COLOR
670 * NEW_ALPHA = p_coef x FG_ALPHA + q_coef x BG_ALPHA
671 */
672static void
673exynos4210_fimd_blend_pixel(Exynos4210fimdWindow *w, rgba p_bg, rgba *ret)
674{
675 rgba p_fg = *ret;
676 uint32_t bg_color = ((p_bg.r & 0xFF) << 16) | ((p_bg.g & 0xFF) << 8) |
677 (p_bg.b & 0xFF);
678 uint32_t fg_color = ((p_fg.r & 0xFF) << 16) | ((p_fg.g & 0xFF) << 8) |
679 (p_fg.b & 0xFF);
680 uint32_t alpha_fg = p_fg.a;
681 int i;
682 /* It is possible that blending equation parameters a and b do not
683 * depend on window BLENEQ register. Account for this with first_coef */
684 enum { A_COEF = 0, B_COEF = 1, P_COEF = 2, Q_COEF = 3, COEF_NUM = 4};
685 uint32_t first_coef = A_COEF;
686 uint32_t blend_param[COEF_NUM];
687
688 if (w->keycon[0] & FIMD_WKEYCON0_KEYEN(1 << 25)) {
689 uint32_t colorkey = (w->keycon[1] &
690 ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY0x00FFFFFF)) & FIMD_WKEYCON0_COMPKEY0x00FFFFFF;
691
692 if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON(1 << 24)) &&
693 (bg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY0x00FFFFFF)) == colorkey) {
694 /* Foreground pixel is displayed */
695 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN(1 << 26)) {
696 alpha_fg = w->keyalpha;
697 blend_param[A_COEF] = alpha_fg;
698 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg)((0xFF - ((alpha_fg) & 0xFF)) | (0xFF00 - ((alpha_fg) &
0xFF00)) | (0xFF0000 - ((alpha_fg) & 0xFF0000)));
699 } else {
700 alpha_fg = 0;
701 blend_param[A_COEF] = 0xFFFFFF;
702 blend_param[B_COEF] = 0x0;
703 }
704 first_coef = P_COEF;
705 } else if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON(1 << 24)) == 0 &&
706 (fg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY0x00FFFFFF)) == colorkey) {
707 /* Background pixel is displayed */
708 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN(1 << 26)) {
709 alpha_fg = w->keyalpha;
710 blend_param[A_COEF] = alpha_fg;
711 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg)((0xFF - ((alpha_fg) & 0xFF)) | (0xFF00 - ((alpha_fg) &
0xFF00)) | (0xFF0000 - ((alpha_fg) & 0xFF0000)));
712 } else {
713 alpha_fg = 0;
714 blend_param[A_COEF] = 0x0;
715 blend_param[B_COEF] = 0xFFFFFF;
716 }
717 first_coef = P_COEF;
718 }
719 }
720
721 for (i = first_coef; i < COEF_NUM; i++) {
722 switch ((w->blendeq >> i * 6) & FIMD_BLENDEQ_COEF_MASK0xF) {
723 case 0:
724 blend_param[i] = 0;
725 break;
726 case 1:
727 blend_param[i] = 0xFFFFFF;
728 break;
729 case 2:
730 blend_param[i] = alpha_fg;
731 break;
732 case 3:
733 blend_param[i] = FIMD_1_MINUS_COLOR(alpha_fg)((0xFF - ((alpha_fg) & 0xFF)) | (0xFF00 - ((alpha_fg) &
0xFF00)) | (0xFF0000 - ((alpha_fg) & 0xFF0000)));
734 break;
735 case 4:
736 blend_param[i] = p_bg.a;
737 break;
738 case 5:
739 blend_param[i] = FIMD_1_MINUS_COLOR(p_bg.a)((0xFF - ((p_bg.a) & 0xFF)) | (0xFF00 - ((p_bg.a) & 0xFF00
)) | (0xFF0000 - ((p_bg.a) & 0xFF0000)));
740 break;
741 case 6:
742 blend_param[i] = w->alpha_val[0];
743 break;
744 case 10:
745 blend_param[i] = fg_color;
746 break;
747 case 11:
748 blend_param[i] = FIMD_1_MINUS_COLOR(fg_color)((0xFF - ((fg_color) & 0xFF)) | (0xFF00 - ((fg_color) &
0xFF00)) | (0xFF0000 - ((fg_color) & 0xFF0000)));
749 break;
750 case 12:
751 blend_param[i] = bg_color;
752 break;
753 case 13:
754 blend_param[i] = FIMD_1_MINUS_COLOR(bg_color)((0xFF - ((bg_color) & 0xFF)) | (0xFF00 - ((bg_color) &
0xFF00)) | (0xFF0000 - ((bg_color) & 0xFF0000)));
755 break;
756 default:
757 hw_error("exynos4210.fimd: blend equation coef illegal value\n");
758 break;
759 }
760 }
761
762 fg_color = fimd_mult_and_sum_each_byte(bg_color, blend_param[B_COEF],
763 fg_color, blend_param[A_COEF]);
764 ret->b = fg_color & 0xFF;
765 fg_color >>= 8;
766 ret->g = fg_color & 0xFF;
767 fg_color >>= 8;
768 ret->r = fg_color & 0xFF;
769 ret->a = fimd_mult_and_sum_each_byte(alpha_fg, blend_param[P_COEF],
770 p_bg.a, blend_param[Q_COEF]);
771}
772
773/* These routines read data from video frame buffer in system RAM, convert
774 * this data to display controller internal representation, if necessary,
775 * perform pixel blending with data, currently presented in internal buffer.
776 * Result is stored in display controller internal frame buffer. */
777
778/* Draw line with index in palette table in RAM frame buffer data */
779#define DEF_DRAW_LINE_PALETTE(N)static void draw_line_palette_N(Exynos4210fimdWindow *w, uint8_t
*src, uint8_t *dst, _Bool blend) { int width = w->rightbot_x
- w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w
->wincon & 0x078000) >> 15; uint64_t data; rgba p
, p_old; int i; do { memcpy(&data, src, sizeof(data)); src
+= 8; fimd_swap_data(swap, &data); for (i = (64 / (N) - 1
); i >= 0; i--) { w->pixel_to_rgb(w->palette[(data >>
((N) * i)) & ((1ULL << (N)) - 1)], &p); p.a = w
->get_alpha(w, p.a); if (blend) { ifb += get_pixel_ifb(ifb
, &p_old); exynos4210_fimd_blend_pixel(w, p_old, &p);
} dst += put_pixel_ifb(p, dst); } width -= (64 / (N)); } while
(width > 0); } \
780static void glue(draw_line_palette_, N)draw_line_palette_N(Exynos4210fimdWindow *w, uint8_t *src, \
781 uint8_t *dst, bool_Bool blend) \
782{ \
783 int width = w->rightbot_x - w->lefttop_x + 1; \
784 uint8_t *ifb = dst; \
785 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP0x078000) >> FIMD_WINCON_SWAP_SHIFT15; \
786 uint64_t data; \
787 rgba p, p_old; \
788 int i; \
789 do { \
790 memcpy(&data, src, sizeof(data)); \
791 src += 8; \
792 fimd_swap_data(swap, &data); \
793 for (i = (64 / (N) - 1); i >= 0; i--) { \
794 w->pixel_to_rgb(w->palette[(data >> ((N) * i)) & \
795 ((1ULL << (N)) - 1)], &p); \
796 p.a = w->get_alpha(w, p.a); \
797 if (blend) { \
798 ifb += get_pixel_ifb(ifb, &p_old); \
799 exynos4210_fimd_blend_pixel(w, p_old, &p); \
800 } \
801 dst += put_pixel_ifb(p, dst); \
802 } \
803 width -= (64 / (N)); \
804 } while (width > 0); \
805}
806
807/* Draw line with direct color value in RAM frame buffer data */
808#define DEF_DRAW_LINE_NOPALETTE(N)static void draw_line_N(Exynos4210fimdWindow *w, uint8_t *src
, uint8_t *dst, _Bool blend) { int width = w->rightbot_x -
w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w->
wincon & 0x078000) >> 15; uint64_t data; rgba p, p_old
; int i; do { memcpy(&data, src, sizeof(data)); src += 8;
fimd_swap_data(swap, &data); for (i = (64 / (N) - 1); i >=
0; i--) { w->pixel_to_rgb((data >> ((N) * i)) &
((1ULL << (N)) - 1), &p); p.a = w->get_alpha(w,
p.a); if (blend) { ifb += get_pixel_ifb(ifb, &p_old); exynos4210_fimd_blend_pixel
(w, p_old, &p); } dst += put_pixel_ifb(p, dst); } width -=
(64 / (N)); } while (width > 0); } \
809static void glue(draw_line_, N)draw_line_N(Exynos4210fimdWindow *w, uint8_t *src, \
810 uint8_t *dst, bool_Bool blend) \
811{ \
812 int width = w->rightbot_x - w->lefttop_x + 1; \
813 uint8_t *ifb = dst; \
814 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP0x078000) >> FIMD_WINCON_SWAP_SHIFT15; \
815 uint64_t data; \
816 rgba p, p_old; \
817 int i; \
818 do { \
819 memcpy(&data, src, sizeof(data)); \
820 src += 8; \
821 fimd_swap_data(swap, &data); \
822 for (i = (64 / (N) - 1); i >= 0; i--) { \
823 w->pixel_to_rgb((data >> ((N) * i)) & ((1ULL << (N)) - 1), &p); \
824 p.a = w->get_alpha(w, p.a); \
825 if (blend) { \
826 ifb += get_pixel_ifb(ifb, &p_old); \
827 exynos4210_fimd_blend_pixel(w, p_old, &p); \
828 } \
829 dst += put_pixel_ifb(p, dst); \
830 } \
831 width -= (64 / (N)); \
832 } while (width > 0); \
833}
834
835DEF_DRAW_LINE_PALETTE(1)static void draw_line_palette_1(Exynos4210fimdWindow *w, uint8_t
*src, uint8_t *dst, _Bool blend) { int width = w->rightbot_x
- w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w
->wincon & 0x078000) >> 15; uint64_t data; rgba p
, p_old; int i; do { memcpy(&data, src, sizeof(data)); src
+= 8; fimd_swap_data(swap, &data); for (i = (64 / (1) - 1
); i >= 0; i--) { w->pixel_to_rgb(w->palette[(data >>
((1) * i)) & ((1ULL << (1)) - 1)], &p); p.a = w
->get_alpha(w, p.a); if (blend) { ifb += get_pixel_ifb(ifb
, &p_old); exynos4210_fimd_blend_pixel(w, p_old, &p);
} dst += put_pixel_ifb(p, dst); } width -= (64 / (1)); } while
(width > 0); }
836DEF_DRAW_LINE_PALETTE(2)static void draw_line_palette_2(Exynos4210fimdWindow *w, uint8_t
*src, uint8_t *dst, _Bool blend) { int width = w->rightbot_x
- w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w
->wincon & 0x078000) >> 15; uint64_t data; rgba p
, p_old; int i; do { memcpy(&data, src, sizeof(data)); src
+= 8; fimd_swap_data(swap, &data); for (i = (64 / (2) - 1
); i >= 0; i--) { w->pixel_to_rgb(w->palette[(data >>
((2) * i)) & ((1ULL << (2)) - 1)], &p); p.a = w
->get_alpha(w, p.a); if (blend) { ifb += get_pixel_ifb(ifb
, &p_old); exynos4210_fimd_blend_pixel(w, p_old, &p);
} dst += put_pixel_ifb(p, dst); } width -= (64 / (2)); } while
(width > 0); }
837DEF_DRAW_LINE_PALETTE(4)static void draw_line_palette_4(Exynos4210fimdWindow *w, uint8_t
*src, uint8_t *dst, _Bool blend) { int width = w->rightbot_x
- w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w
->wincon & 0x078000) >> 15; uint64_t data; rgba p
, p_old; int i; do { memcpy(&data, src, sizeof(data)); src
+= 8; fimd_swap_data(swap, &data); for (i = (64 / (4) - 1
); i >= 0; i--) { w->pixel_to_rgb(w->palette[(data >>
((4) * i)) & ((1ULL << (4)) - 1)], &p); p.a = w
->get_alpha(w, p.a); if (blend) { ifb += get_pixel_ifb(ifb
, &p_old); exynos4210_fimd_blend_pixel(w, p_old, &p);
} dst += put_pixel_ifb(p, dst); } width -= (64 / (4)); } while
(width > 0); }
838DEF_DRAW_LINE_PALETTE(8)static void draw_line_palette_8(Exynos4210fimdWindow *w, uint8_t
*src, uint8_t *dst, _Bool blend) { int width = w->rightbot_x
- w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w
->wincon & 0x078000) >> 15; uint64_t data; rgba p
, p_old; int i; do { memcpy(&data, src, sizeof(data)); src
+= 8; fimd_swap_data(swap, &data); for (i = (64 / (8) - 1
); i >= 0; i--) { w->pixel_to_rgb(w->palette[(data >>
((8) * i)) & ((1ULL << (8)) - 1)], &p); p.a = w
->get_alpha(w, p.a); if (blend) { ifb += get_pixel_ifb(ifb
, &p_old); exynos4210_fimd_blend_pixel(w, p_old, &p);
} dst += put_pixel_ifb(p, dst); } width -= (64 / (8)); } while
(width > 0); }
839DEF_DRAW_LINE_NOPALETTE(8)static void draw_line_8(Exynos4210fimdWindow *w, uint8_t *src
, uint8_t *dst, _Bool blend) { int width = w->rightbot_x -
w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w->
wincon & 0x078000) >> 15; uint64_t data; rgba p, p_old
; int i; do { memcpy(&data, src, sizeof(data)); src += 8;
fimd_swap_data(swap, &data); for (i = (64 / (8) - 1); i >=
0; i--) { w->pixel_to_rgb((data >> ((8) * i)) &
((1ULL << (8)) - 1), &p); p.a = w->get_alpha(w,
p.a); if (blend) { ifb += get_pixel_ifb(ifb, &p_old); exynos4210_fimd_blend_pixel
(w, p_old, &p); } dst += put_pixel_ifb(p, dst); } width -=
(64 / (8)); } while (width > 0); } /* 8bpp mode has palette and non-palette versions */
840DEF_DRAW_LINE_NOPALETTE(16)static void draw_line_16(Exynos4210fimdWindow *w, uint8_t *src
, uint8_t *dst, _Bool blend) { int width = w->rightbot_x -
w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w->
wincon & 0x078000) >> 15; uint64_t data; rgba p, p_old
; int i; do { memcpy(&data, src, sizeof(data)); src += 8;
fimd_swap_data(swap, &data); for (i = (64 / (16) - 1); i
>= 0; i--) { w->pixel_to_rgb((data >> ((16) * i)
) & ((1ULL << (16)) - 1), &p); p.a = w->get_alpha
(w, p.a); if (blend) { ifb += get_pixel_ifb(ifb, &p_old);
exynos4210_fimd_blend_pixel(w, p_old, &p); } dst += put_pixel_ifb
(p, dst); } width -= (64 / (16)); } while (width > 0); }
841DEF_DRAW_LINE_NOPALETTE(32)static void draw_line_32(Exynos4210fimdWindow *w, uint8_t *src
, uint8_t *dst, _Bool blend) { int width = w->rightbot_x -
w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w->
wincon & 0x078000) >> 15; uint64_t data; rgba p, p_old
; int i; do { memcpy(&data, src, sizeof(data)); src += 8;
fimd_swap_data(swap, &data); for (i = (64 / (32) - 1); i
>= 0; i--) { w->pixel_to_rgb((data >> ((32) * i)
) & ((1ULL << (32)) - 1), &p); p.a = w->get_alpha
(w, p.a); if (blend) { ifb += get_pixel_ifb(ifb, &p_old);
exynos4210_fimd_blend_pixel(w, p_old, &p); } dst += put_pixel_ifb
(p, dst); } width -= (64 / (32)); } while (width > 0); }
842
843/* Special draw line routine for window color map case */
844static void draw_line_mapcolor(Exynos4210fimdWindow *w, uint8_t *src,
845 uint8_t *dst, bool_Bool blend)
846{
847 rgba p, p_old;
848 uint8_t *ifb = dst;
849 int width = w->rightbot_x - w->lefttop_x + 1;
850 uint32_t map_color = w->winmap & FIMD_WINMAP_COLOR_MASK0x00FFFFFF;
851
852 do {
853 pixel_888_to_rgb(map_color, &p);
854 p.a = w->get_alpha(w, p.a);
855 if (blend) {
856 ifb += get_pixel_ifb(ifb, &p_old);
857 exynos4210_fimd_blend_pixel(w, p_old, &p);
858 }
859 dst += put_pixel_ifb(p, dst);
860 } while (--width);
861}
862
863/* Write RGB to QEMU's GraphicConsole framebuffer */
864
865static int put_to_qemufb_pixel8(const rgba p, uint8_t *d)
866{
867 uint32_t pixel = rgb_to_pixel8(p.r, p.g, p.b);
868 *(uint8_t *)d = pixel;
869 return 1;
870}
871
872static int put_to_qemufb_pixel15(const rgba p, uint8_t *d)
873{
874 uint32_t pixel = rgb_to_pixel15(p.r, p.g, p.b);
875 *(uint16_t *)d = pixel;
876 return 2;
877}
878
879static int put_to_qemufb_pixel16(const rgba p, uint8_t *d)
880{
881 uint32_t pixel = rgb_to_pixel16(p.r, p.g, p.b);
882 *(uint16_t *)d = pixel;
883 return 2;
884}
885
886static int put_to_qemufb_pixel24(const rgba p, uint8_t *d)
887{
888 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);
889 *(uint8_t *)d++ = (pixel >> 0) & 0xFF;
890 *(uint8_t *)d++ = (pixel >> 8) & 0xFF;
891 *(uint8_t *)d++ = (pixel >> 16) & 0xFF;
892 return 3;
893}
894
895static int put_to_qemufb_pixel32(const rgba p, uint8_t *d)
896{
897 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);
898 *(uint32_t *)d = pixel;
899 return 4;
900}
901
902/* Routine to copy pixel from internal buffer to QEMU buffer */
903static int (*put_pixel_toqemu)(const rgba p, uint8_t *pixel);
904static inline void fimd_update_putpix_qemu(int bpp)
905{
906 switch (bpp) {
907 case 8:
908 put_pixel_toqemu = put_to_qemufb_pixel8;
909 break;
910 case 15:
911 put_pixel_toqemu = put_to_qemufb_pixel15;
912 break;
913 case 16:
914 put_pixel_toqemu = put_to_qemufb_pixel16;
915 break;
916 case 24:
917 put_pixel_toqemu = put_to_qemufb_pixel24;
918 break;
919 case 32:
920 put_pixel_toqemu = put_to_qemufb_pixel32;
921 break;
922 default:
923 hw_error("exynos4210.fimd: unsupported BPP (%d)", bpp);
924 break;
925 }
926}
927
928/* Routine to copy a line from internal frame buffer to QEMU display */
929static void fimd_copy_line_toqemu(int width, uint8_t *src, uint8_t *dst)
930{
931 rgba p;
932
933 do {
934 src += get_pixel_ifb(src, &p);
935 dst += put_pixel_toqemu(p, dst);
936 } while (--width);
937}
938
939/* Parse BPPMODE_F = WINCON1[5:2] bits */
940static void exynos4210_fimd_update_win_bppmode(Exynos4210fimdState *s, int win)
941{
942 Exynos4210fimdWindow *w = &s->window[win];
943
944 if (w->winmap & FIMD_WINMAP_EN(1 << 24)) {
945 w->draw_line = draw_line_mapcolor;
946 return;
947 }
948
949 switch (WIN_BPP_MODE(w)((w->wincon >> 2) & 0xF)) {
950 case 0:
951 w->draw_line = draw_line_palette_1;
952 w->pixel_to_rgb =
953 palette_data_format[exynos4210_fimd_palette_format(s, win)];
954 break;
955 case 1:
956 w->draw_line = draw_line_palette_2;
957 w->pixel_to_rgb =
958 palette_data_format[exynos4210_fimd_palette_format(s, win)];
959 break;
960 case 2:
961 w->draw_line = draw_line_palette_4;
962 w->pixel_to_rgb =
963 palette_data_format[exynos4210_fimd_palette_format(s, win)];
964 break;
965 case 3:
966 w->draw_line = draw_line_palette_8;
967 w->pixel_to_rgb =
968 palette_data_format[exynos4210_fimd_palette_format(s, win)];
969 break;
970 case 4:
971 w->draw_line = draw_line_8;
972 w->pixel_to_rgb = pixel_a232_to_rgb;
973 break;
974 case 5:
975 w->draw_line = draw_line_16;
976 w->pixel_to_rgb = pixel_565_to_rgb;
977 break;
978 case 6:
979 w->draw_line = draw_line_16;
980 w->pixel_to_rgb = pixel_a555_to_rgb;
981 break;
982 case 7:
983 w->draw_line = draw_line_16;
984 w->pixel_to_rgb = pixel_1555_to_rgb;
985 break;
986 case 8:
987 w->draw_line = draw_line_32;
988 w->pixel_to_rgb = pixel_666_to_rgb;
989 break;
990 case 9:
991 w->draw_line = draw_line_32;
992 w->pixel_to_rgb = pixel_a665_to_rgb;
993 break;
994 case 10:
995 w->draw_line = draw_line_32;
996 w->pixel_to_rgb = pixel_a666_to_rgb;
997 break;
998 case 11:
999 w->draw_line = draw_line_32;
1000 w->pixel_to_rgb = pixel_888_to_rgb;
1001 break;
1002 case 12:
1003 w->draw_line = draw_line_32;
1004 w->pixel_to_rgb = pixel_a887_to_rgb;
1005 break;
1006 case 13:
1007 w->draw_line = draw_line_32;
1008 if ((w->wincon & FIMD_WINCON_BLD_PIX(1 << 6)) && (w->wincon &
1009 FIMD_WINCON_ALPHA_SEL(1 << 1))) {
1010 w->pixel_to_rgb = pixel_8888_to_rgb;
1011 } else {
1012 w->pixel_to_rgb = pixel_a888_to_rgb;
1013 }
1014 break;
1015 case 14:
1016 w->draw_line = draw_line_16;
1017 if ((w->wincon & FIMD_WINCON_BLD_PIX(1 << 6)) && (w->wincon &
1018 FIMD_WINCON_ALPHA_SEL(1 << 1))) {
1019 w->pixel_to_rgb = pixel_4444_to_rgb;
1020 } else {
1021 w->pixel_to_rgb = pixel_a444_to_rgb;
1022 }
1023 break;
1024 case 15:
1025 w->draw_line = draw_line_16;
1026 w->pixel_to_rgb = pixel_555_to_rgb;
1027 break;
1028 }
1029}
1030
1031#if EXYNOS4210_FIMD_MODE_TRACE0 > 0
1032static const char *exynos4210_fimd_get_bppmode(int mode_code)
1033{
1034 switch (mode_code) {
1035 case 0:
1036 return "1 bpp";
1037 case 1:
1038 return "2 bpp";
1039 case 2:
1040 return "4 bpp";
1041 case 3:
1042 return "8 bpp (palettized)";
1043 case 4:
1044 return "8 bpp (non-palettized, A: 1-R:2-G:3-B:2)";
1045 case 5:
1046 return "16 bpp (non-palettized, R:5-G:6-B:5)";
1047 case 6:
1048 return "16 bpp (non-palettized, A:1-R:5-G:5-B:5)";
1049 case 7:
1050 return "16 bpp (non-palettized, I :1-R:5-G:5-B:5)";
1051 case 8:
1052 return "Unpacked 18 bpp (non-palettized, R:6-G:6-B:6)";
1053 case 9:
1054 return "Unpacked 18bpp (non-palettized,A:1-R:6-G:6-B:5)";
1055 case 10:
1056 return "Unpacked 19bpp (non-palettized,A:1-R:6-G:6-B:6)";
1057 case 11:
1058 return "Unpacked 24 bpp (non-palettized R:8-G:8-B:8)";
1059 case 12:
1060 return "Unpacked 24 bpp (non-palettized A:1-R:8-G:8-B:7)";
1061 case 13:
1062 return "Unpacked 25 bpp (non-palettized A:1-R:8-G:8-B:8)";
1063 case 14:
1064 return "Unpacked 13 bpp (non-palettized A:1-R:4-G:4-B:4)";
1065 case 15:
1066 return "Unpacked 15 bpp (non-palettized R:5-G:5-B:5)";
1067 default:
1068 return "Non-existing bpp mode";
1069 }
1070}
1071
1072static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
1073 int win_num, uint32_t val)
1074{
1075 Exynos4210fimdWindow *w = &s->window[win_num];
1076
1077 if (w->winmap & FIMD_WINMAP_EN(1 << 24)) {
1078 printf("QEMU FIMD: Window %d is mapped with MAPCOLOR=0x%x\n",
1079 win_num, w->winmap & 0xFFFFFF);
1080 return;
1081 }
1082
1083 if ((val != 0xFFFFFFFF) && ((w->wincon >> 2) & 0xF) == ((val >> 2) & 0xF)) {
1084 return;
1085 }
1086 printf("QEMU FIMD: Window %d BPP mode set to %s\n", win_num,
1087 exynos4210_fimd_get_bppmode((val >> 2) & 0xF));
1088}
1089#else
1090static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
1091 int win_num, uint32_t val)
1092{
1093
1094}
1095#endif
1096
1097static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w)
1098{
1099 switch (w->wincon & FIMD_WINCON_BUFSTATUS((1 << 21) | (1 << 31))) {
1100 case FIMD_WINCON_BUF0_STAT((0 << 21) | (0 << 31)):
1101 return 0;
1102 case FIMD_WINCON_BUF1_STAT((1 << 21) | (0 << 31)):
1103 return 1;
1104 case FIMD_WINCON_BUF2_STAT((0 << 21) | (1 << 31)):
1105 return 2;
1106 default:
1107 DPRINT_ERROR("Non-existent buffer index\n")do { } while (0);
1108 return 0;
1109 }
1110}
1111
1112/* Updates specified window's MemorySection based on values of WINCON,
1113 * VIDOSDA, VIDOSDB, VIDWADDx and SHADOWCON registers */
1114static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
1115{
1116 SysBusDevice *sbd = SYS_BUS_DEVICE(s)((SysBusDevice *)object_dynamic_cast_assert(((Object *)((s)))
, ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/exynos4210_fimd.c"
, 1116, __func__));
1117 Exynos4210fimdWindow *w = &s->window[win];
1118 hwaddr fb_start_addr, fb_mapped_len;
1119
1120 if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN(1 << 0)) ||
1121 FIMD_WINDOW_PROTECTED(s->shadowcon, win)((s->shadowcon) & (1 << (10 + (win))))) {
1122 return;
1123 }
1124
1125 if (w->host_fb_addr) {
1126 cpu_physical_memory_unmap(w->host_fb_addr, w->fb_len, 0, 0);
1127 w->host_fb_addr = NULL((void*)0);
1128 w->fb_len = 0;
1129 }
1130
1131 fb_start_addr = w->buf_start[fimd_get_buffer_id(w)];
1132 /* Total number of bytes of virtual screen used by current window */
1133 w->fb_len = fb_mapped_len = (w->virtpage_width + w->virtpage_offsize) *
1134 (w->rightbot_y - w->lefttop_y + 1);
1135
1136 /* TODO: add .exit and unref the region there. Not needed yet since sysbus
1137 * does not support hot-unplug.
1138 */
1139 memory_region_unref(w->mem_section.mr);
1140 w->mem_section = memory_region_find(sysbus_address_space(sbd),
1141 fb_start_addr, w->fb_len);
1142 assert(w->mem_section.mr)((w->mem_section.mr) ? (void) (0) : __assert_fail ("w->mem_section.mr"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/display/exynos4210_fimd.c"
, 1142, __PRETTY_FUNCTION__));
1143 assert(w->mem_section.offset_within_address_space == fb_start_addr)((w->mem_section.offset_within_address_space == fb_start_addr
) ? (void) (0) : __assert_fail ("w->mem_section.offset_within_address_space == fb_start_addr"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/display/exynos4210_fimd.c"
, 1143, __PRETTY_FUNCTION__));
1144 DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n",do { } while (0)
1145 win, fb_start_addr, w->fb_len)do { } while (0);
1146
1147 if (int128_get64(w->mem_section.size) != w->fb_len ||
1148 !memory_region_is_ram(w->mem_section.mr)) {
1149 DPRINT_ERROR("Failed to find window %u framebuffer region\n", win)do { } while (0);
1150 goto error_return;
1151 }
1152
1153 w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len, 0);
1154 if (!w->host_fb_addr) {
1155 DPRINT_ERROR("Failed to map window %u framebuffer\n", win)do { } while (0);
1156 goto error_return;
1157 }
1158
1159 if (fb_mapped_len != w->fb_len) {
1160 DPRINT_ERROR("Window %u mapped framebuffer length is less then "do { } while (0)
1161 "expected\n", win)do { } while (0);
1162 cpu_physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0);
1163 goto error_return;
1164 }
1165 return;
1166
1167error_return:
1168 memory_region_unref(w->mem_section.mr);
1169 w->mem_section.mr = NULL((void*)0);
1170 w->mem_section.size = int128_zero();
1171 w->host_fb_addr = NULL((void*)0);
1172 w->fb_len = 0;
1173}
1174
1175static void exynos4210_fimd_enable(Exynos4210fimdState *s, bool_Bool enabled)
1176{
1177 if (enabled && !s->enabled) {
1178 unsigned w;
1179 s->enabled = true1;
1180 for (w = 0; w < NUM_OF_WINDOWS5; w++) {
1181 fimd_update_memory_section(s, w);
1182 }
1183 }
1184 s->enabled = enabled;
1185 DPRINT_TRACE("display controller %s\n", enabled ? "enabled" : "disabled")do { } while (0);
1186}
1187
1188static inline uint32_t unpack_upper_4(uint32_t x)
1189{
1190 return ((x & 0xF00) << 12) | ((x & 0xF0) << 8) | ((x & 0xF) << 4);
1191}
1192
1193static inline uint32_t pack_upper_4(uint32_t x)
1194{
1195 return (((x & 0xF00000) >> 12) | ((x & 0xF000) >> 8) |
1196 ((x & 0xF0) >> 4)) & 0xFFF;
1197}
1198
1199static void exynos4210_fimd_update_irq(Exynos4210fimdState *s)
1200{
1201 if (!(s->vidintcon[0] & FIMD_VIDINT_INTEN(1 << 0))) {
1202 qemu_irq_lower(s->irq[0]);
1203 qemu_irq_lower(s->irq[1]);
1204 qemu_irq_lower(s->irq[2]);
1205 return;
1206 }
1207 if ((s->vidintcon[0] & FIMD_VIDINT_INTFIFOEN(1 << 1)) &&
1208 (s->vidintcon[1] & FIMD_VIDINT_INTFIFOPEND(1 << 0))) {
1209 qemu_irq_raise(s->irq[0]);
1210 } else {
1211 qemu_irq_lower(s->irq[0]);
1212 }
1213 if ((s->vidintcon[0] & FIMD_VIDINT_INTFRMEN(1 << 12)) &&
1214 (s->vidintcon[1] & FIMD_VIDINT_INTFRMPEND(1 << 1))) {
1215 qemu_irq_raise(s->irq[1]);
1216 } else {
1217 qemu_irq_lower(s->irq[1]);
1218 }
1219 if ((s->vidintcon[0] & FIMD_VIDINT_I80IFDONE(1 << 17)) &&
1220 (s->vidintcon[1] & FIMD_VIDINT_INTI80PEND(1 << 2))) {
1221 qemu_irq_raise(s->irq[2]);
1222 } else {
1223 qemu_irq_lower(s->irq[2]);
1224 }
1225}
1226
1227static void exynos4210_fimd_invalidate(void *opaque)
1228{
1229 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1230 s->invalidate = true1;
1231}
1232
1233static void exynos4210_update_resolution(Exynos4210fimdState *s)
1234{
1235 DisplaySurface *surface = qemu_console_surface(s->console);
1236
1237 /* LCD resolution is stored in VIDEO TIME CONTROL REGISTER 2 */
1238 uint32_t width = ((s->vidtcon[2] >> FIMD_VIDTCON2_HOR_SHIFT0) &
1239 FIMD_VIDTCON2_SIZE_MASK0x07FF) + 1;
1240 uint32_t height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT11) &
1241 FIMD_VIDTCON2_SIZE_MASK0x07FF) + 1;
1242
1243 if (s->ifb == NULL((void*)0) || surface_width(surface) != width ||
1244 surface_height(surface) != height) {
1245 DPRINT_L1("Resolution changed from %ux%u to %ux%u\n",do { } while (0)
1246 surface_width(surface), surface_height(surface), width, height)do { } while (0);
1247 qemu_console_resize(s->console, width, height);
1248 s->ifb = g_realloc(s->ifb, width * height * RGBA_SIZE7 + 1);
1249 memset(s->ifb, 0, width * height * RGBA_SIZE7 + 1);
1250 exynos4210_fimd_invalidate(s);
1251 }
1252}
1253
1254static void exynos4210_fimd_update(void *opaque)
1255{
1256 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1257 DisplaySurface *surface;
1258 Exynos4210fimdWindow *w;
1259 int i, line;
1260 hwaddr fb_line_addr, inc_size;
1261 int scrn_height;
1262 int first_line = -1, last_line = -1, scrn_width;
1263 bool_Bool blend = false0;
1264 uint8_t *host_fb_addr;
1265 bool_Bool is_dirty = false0;
1266 const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK0x07FF) + 1;
1267 const int global_height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT11) &
1268 FIMD_VIDTCON2_SIZE_MASK0x07FF) + 1;
1269
1270 if (!s || !s->console || !s->enabled ||
1271 surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) {
1272 return;
1273 }
1274 exynos4210_update_resolution(s);
1275 surface = qemu_console_surface(s->console);
1276
1277 for (i = 0; i < NUM_OF_WINDOWS5; i++) {
1278 w = &s->window[i];
1279 if ((w->wincon & FIMD_WINCON_ENWIN(1 << 0)) && w->host_fb_addr) {
1280 scrn_height = w->rightbot_y - w->lefttop_y + 1;
1281 scrn_width = w->virtpage_width;
1282 /* Total width of virtual screen page in bytes */
1283 inc_size = scrn_width + w->virtpage_offsize;
1284 memory_region_sync_dirty_bitmap(w->mem_section.mr);
1285 host_fb_addr = w->host_fb_addr;
1286 fb_line_addr = w->mem_section.offset_within_region;
1287
1288 for (line = 0; line < scrn_height; line++) {
1289 is_dirty = memory_region_get_dirty(w->mem_section.mr,
1290 fb_line_addr, scrn_width, DIRTY_MEMORY_VGA0);
1291
1292 if (s->invalidate || is_dirty) {
1293 if (first_line == -1) {
1294 first_line = line;
1295 }
1296 last_line = line;
1297 w->draw_line(w, host_fb_addr, s->ifb +
1298 w->lefttop_x * RGBA_SIZE7 + (w->lefttop_y + line) *
1299 global_width * RGBA_SIZE7, blend);
1300 }
1301 host_fb_addr += inc_size;
1302 fb_line_addr += inc_size;
1303 is_dirty = false0;
Value stored to 'is_dirty' is never read
1304 }
1305 memory_region_reset_dirty(w->mem_section.mr,
1306 w->mem_section.offset_within_region,
1307 w->fb_len, DIRTY_MEMORY_VGA0);
1308 blend = true1;
1309 }
1310 }
1311
1312 /* Copy resulting image to QEMU_CONSOLE. */
1313 if (first_line >= 0) {
1314 uint8_t *d;
1315 int bpp;
1316
1317 bpp = surface_bits_per_pixel(surface);
1318 fimd_update_putpix_qemu(bpp);
1319 bpp = (bpp + 1) >> 3;
1320 d = surface_data(surface);
1321 for (line = first_line; line <= last_line; line++) {
1322 fimd_copy_line_toqemu(global_width, s->ifb + global_width * line *
1323 RGBA_SIZE7, d + global_width * line * bpp);
1324 }
1325 dpy_gfx_update(s->console, 0, 0, global_width, global_height);
1326 }
1327 s->invalidate = false0;
1328 s->vidintcon[1] |= FIMD_VIDINT_INTFRMPEND(1 << 1);
1329 if ((s->vidcon[0] & FIMD_VIDCON0_ENVID_F(1 << 0)) == 0) {
1330 exynos4210_fimd_enable(s, false0);
1331 }
1332 exynos4210_fimd_update_irq(s);
1333}
1334
1335static void exynos4210_fimd_reset(DeviceState *d)
1336{
1337 Exynos4210fimdState *s = EXYNOS4210_FIMD(d)((Exynos4210fimdState *)object_dynamic_cast_assert(((Object *
)((d))), ("exynos4210.fimd"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/exynos4210_fimd.c"
, 1337, __func__));
1338 unsigned w;
1339
1340 DPRINT_TRACE("Display controller reset\n")do { } while (0);
1341 /* Set all display controller registers to 0 */
1342 memset(&s->vidcon, 0, (uint8_t *)&s->window - (uint8_t *)&s->vidcon);
1343 for (w = 0; w < NUM_OF_WINDOWS5; w++) {
1344 memset(&s->window[w], 0, sizeof(Exynos4210fimdWindow));
1345 s->window[w].blendeq = 0xC2;
1346 exynos4210_fimd_update_win_bppmode(s, w);
1347 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
1348 fimd_update_get_alpha(s, w);
1349 }
1350
1351 if (s->ifb != NULL((void*)0)) {
1352 g_free(s->ifb);
1353 }
1354 s->ifb = NULL((void*)0);
1355
1356 exynos4210_fimd_invalidate(s);
1357 exynos4210_fimd_enable(s, false0);
1358 /* Some registers have non-zero initial values */
1359 s->winchmap = 0x7D517D51;
1360 s->colorgaincon = 0x10040100;
1361 s->huecoef_cr[0] = s->huecoef_cr[3] = 0x01000100;
1362 s->huecoef_cb[0] = s->huecoef_cb[3] = 0x01000100;
1363 s->hueoffset = 0x01800080;
1364}
1365
1366static void exynos4210_fimd_write(void *opaque, hwaddr offset,
1367 uint64_t val, unsigned size)
1368{
1369 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1370 unsigned w, i;
1371 uint32_t old_value;
1372
1373 DPRINT_L2("write offset 0x%08x, value=%llu(0x%08llx)\n", offset,do { } while (0)
1374 (long long unsigned int)val, (long long unsigned int)val)do { } while (0);
1375
1376 switch (offset) {
1377 case FIMD_VIDCON00x0000:
1378 if ((val & FIMD_VIDCON0_ENVID_MASK((1 << 0) | (1 << 1))) == FIMD_VIDCON0_ENVID_MASK((1 << 0) | (1 << 1))) {
1379 exynos4210_fimd_enable(s, true1);
1380 } else {
1381 if ((val & FIMD_VIDCON0_ENVID(1 << 1)) == 0) {
1382 exynos4210_fimd_enable(s, false0);
1383 }
1384 }
1385 s->vidcon[0] = val;
1386 break;
1387 case FIMD_VIDCON10x0004:
1388 /* Leave read-only bits as is */
1389 val = (val & (~FIMD_VIDCON1_ROMASK0x07FFE000)) |
1390 (s->vidcon[1] & FIMD_VIDCON1_ROMASK0x07FFE000);
1391 s->vidcon[1] = val;
1392 break;
1393 case FIMD_VIDCON20x0008 ... FIMD_VIDCON30x000C:
1394 s->vidcon[(offset) >> 2] = val;
1395 break;
1396 case FIMD_VIDTCON_START0x10 ... FIMD_VIDTCON_END0x1C:
1397 s->vidtcon[(offset - FIMD_VIDTCON_START0x10) >> 2] = val;
1398 break;
1399 case FIMD_WINCON_START0x0020 ... FIMD_WINCON_END0x0030:
1400 w = (offset - FIMD_WINCON_START0x0020) >> 2;
1401 /* Window's current buffer ID */
1402 i = fimd_get_buffer_id(&s->window[w]);
1403 old_value = s->window[w].wincon;
1404 val = (val & ~FIMD_WINCON_ROMASK0x82200000) |
1405 (s->window[w].wincon & FIMD_WINCON_ROMASK0x82200000);
1406 if (w == 0) {
1407 /* Window 0 wincon ALPHA_MUL bit must always be 0 */
1408 val &= ~FIMD_WINCON_ALPHA_MUL(1 << 7);
1409 }
1410 exynos4210_fimd_trace_bppmode(s, w, val);
1411 switch (val & FIMD_WINCON_BUFSELECT((1 << 20) | (1 << 30))) {
1412 case FIMD_WINCON_BUF0_SEL((0 << 20) | (0 << 30)):
1413 val &= ~FIMD_WINCON_BUFSTATUS((1 << 21) | (1 << 31));
1414 break;
1415 case FIMD_WINCON_BUF1_SEL((1 << 20) | (0 << 30)):
1416 val = (val & ~FIMD_WINCON_BUFSTAT_H(1 << 31)) | FIMD_WINCON_BUFSTAT_L(1 << 21);
1417 break;
1418 case FIMD_WINCON_BUF2_SEL((0 << 20) | (1 << 30)):
1419 if (val & FIMD_WINCON_BUFMODE(1 << 14)) {
1420 val = (val & ~FIMD_WINCON_BUFSTAT_L(1 << 21)) | FIMD_WINCON_BUFSTAT_H(1 << 31);
1421 }
1422 break;
1423 default:
1424 break;
1425 }
1426 s->window[w].wincon = val;
1427 exynos4210_fimd_update_win_bppmode(s, w);
1428 fimd_update_get_alpha(s, w);
1429 if ((i != fimd_get_buffer_id(&s->window[w])) ||
1430 (!(old_value & FIMD_WINCON_ENWIN(1 << 0)) && (s->window[w].wincon &
1431 FIMD_WINCON_ENWIN(1 << 0)))) {
1432 fimd_update_memory_section(s, w);
1433 }
1434 break;
1435 case FIMD_SHADOWCON0x0034:
1436 old_value = s->shadowcon;
1437 s->shadowcon = val;
1438 for (w = 0; w < NUM_OF_WINDOWS5; w++) {
1439 if (FIMD_WINDOW_PROTECTED(old_value, w)((old_value) & (1 << (10 + (w)))) &&
1440 !FIMD_WINDOW_PROTECTED(s->shadowcon, w)((s->shadowcon) & (1 << (10 + (w))))) {
1441 fimd_update_memory_section(s, w);
1442 }
1443 }
1444 break;
1445 case FIMD_WINCHMAP0x003C:
1446 s->winchmap = val;
1447 break;
1448 case FIMD_VIDOSD_START0x0040 ... FIMD_VIDOSD_END0x0088:
1449 w = (offset - FIMD_VIDOSD_START0x0040) >> 4;
1450 i = ((offset - FIMD_VIDOSD_START0x0040) & 0xF) >> 2;
1451 switch (i) {
1452 case 0:
1453 old_value = s->window[w].lefttop_y;
1454 s->window[w].lefttop_x = (val >> FIMD_VIDOSD_HOR_SHIFT11) &
1455 FIMD_VIDOSD_COORD_MASK0x07FF;
1456 s->window[w].lefttop_y = (val >> FIMD_VIDOSD_VER_SHIFT0) &
1457 FIMD_VIDOSD_COORD_MASK0x07FF;
1458 if (s->window[w].lefttop_y != old_value) {
1459 fimd_update_memory_section(s, w);
1460 }
1461 break;
1462 case 1:
1463 old_value = s->window[w].rightbot_y;
1464 s->window[w].rightbot_x = (val >> FIMD_VIDOSD_HOR_SHIFT11) &
1465 FIMD_VIDOSD_COORD_MASK0x07FF;
1466 s->window[w].rightbot_y = (val >> FIMD_VIDOSD_VER_SHIFT0) &
1467 FIMD_VIDOSD_COORD_MASK0x07FF;
1468 if (s->window[w].rightbot_y != old_value) {
1469 fimd_update_memory_section(s, w);
1470 }
1471 break;
1472 case 2:
1473 if (w == 0) {
1474 s->window[w].osdsize = val;
1475 } else {
1476 s->window[w].alpha_val[0] =
1477 unpack_upper_4((val & FIMD_VIDOSD_ALPHA_AEN00xFFF000) >>
1478 FIMD_VIDOSD_AEN0_SHIFT12) |
1479 (s->window[w].alpha_val[0] & FIMD_VIDALPHA_ALPHA_LOWER0x000F0F0F);
1480 s->window[w].alpha_val[1] =
1481 unpack_upper_4(val & FIMD_VIDOSD_ALPHA_AEN10x000FFF) |
1482 (s->window[w].alpha_val[1] & FIMD_VIDALPHA_ALPHA_LOWER0x000F0F0F);
1483 }
1484 break;
1485 case 3:
1486 if (w != 1 && w != 2) {
1487 DPRINT_ERROR("Bad write offset 0x%08x\n", offset)do { } while (0);
1488 return;
1489 }
1490 s->window[w].osdsize = val;
1491 break;
1492 }
1493 break;
1494 case FIMD_VIDWADD0_START0x00A0 ... FIMD_VIDWADD0_END0x00C4:
1495 w = (offset - FIMD_VIDWADD0_START0x00A0) >> 3;
1496 i = ((offset - FIMD_VIDWADD0_START0x00A0) >> 2) & 1;
1497 if (i == fimd_get_buffer_id(&s->window[w]) &&
1498 s->window[w].buf_start[i] != val) {
1499 s->window[w].buf_start[i] = val;
1500 fimd_update_memory_section(s, w);
1501 break;
1502 }
1503 s->window[w].buf_start[i] = val;
1504 break;
1505 case FIMD_VIDWADD1_START0x00D0 ... FIMD_VIDWADD1_END0x00F4:
1506 w = (offset - FIMD_VIDWADD1_START0x00D0) >> 3;
1507 i = ((offset - FIMD_VIDWADD1_START0x00D0) >> 2) & 1;
1508 s->window[w].buf_end[i] = val;
1509 break;
1510 case FIMD_VIDWADD2_START0x0100 ... FIMD_VIDWADD2_END0x0110:
1511 w = (offset - FIMD_VIDWADD2_START0x0100) >> 2;
1512 if (((val & FIMD_VIDWADD2_PAGEWIDTH0x1FFF) != s->window[w].virtpage_width) ||
1513 (((val >> FIMD_VIDWADD2_OFFSIZE_SHIFT13) & FIMD_VIDWADD2_OFFSIZE0x1FFF) !=
1514 s->window[w].virtpage_offsize)) {
1515 s->window[w].virtpage_width = val & FIMD_VIDWADD2_PAGEWIDTH0x1FFF;
1516 s->window[w].virtpage_offsize =
1517 (val >> FIMD_VIDWADD2_OFFSIZE_SHIFT13) & FIMD_VIDWADD2_OFFSIZE0x1FFF;
1518 fimd_update_memory_section(s, w);
1519 }
1520 break;
1521 case FIMD_VIDINTCON00x130:
1522 s->vidintcon[0] = val;
1523 break;
1524 case FIMD_VIDINTCON10x134:
1525 s->vidintcon[1] &= ~(val & 7);
1526 exynos4210_fimd_update_irq(s);
1527 break;
1528 case FIMD_WKEYCON_START0x140 ... FIMD_WKEYCON_END0x15C:
1529 w = ((offset - FIMD_WKEYCON_START0x140) >> 3) + 1;
1530 i = ((offset - FIMD_WKEYCON_START0x140) >> 2) & 1;
1531 s->window[w].keycon[i] = val;
1532 break;
1533 case FIMD_WKEYALPHA_START0x160 ... FIMD_WKEYALPHA_END0x16C:
1534 w = ((offset - FIMD_WKEYALPHA_START0x160) >> 2) + 1;
1535 s->window[w].keyalpha = val;
1536 break;
1537 case FIMD_DITHMODE0x170:
1538 s->dithmode = val;
1539 break;
1540 case FIMD_WINMAP_START0x180 ... FIMD_WINMAP_END0x190:
1541 w = (offset - FIMD_WINMAP_START0x180) >> 2;
1542 old_value = s->window[w].winmap;
1543 s->window[w].winmap = val;
1544 if ((val & FIMD_WINMAP_EN(1 << 24)) ^ (old_value & FIMD_WINMAP_EN(1 << 24))) {
1545 exynos4210_fimd_invalidate(s);
1546 exynos4210_fimd_update_win_bppmode(s, w);
1547 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
1548 exynos4210_fimd_update(s);
1549 }
1550 break;
1551 case FIMD_WPALCON_HIGH0x019C ... FIMD_WPALCON_LOW0x01A0:
1552 i = (offset - FIMD_WPALCON_HIGH0x019C) >> 2;
1553 s->wpalcon[i] = val;
1554 if (s->wpalcon[1] & FIMD_WPALCON_UPDATEEN(1 << 9)) {
1555 for (w = 0; w < NUM_OF_WINDOWS5; w++) {
1556 exynos4210_fimd_update_win_bppmode(s, w);
1557 fimd_update_get_alpha(s, w);
1558 }
1559 }
1560 break;
1561 case FIMD_TRIGCON0x01A4:
1562 val = (val & ~FIMD_TRIGCON_ROMASK0x00000004) | (s->trigcon & FIMD_TRIGCON_ROMASK0x00000004);
1563 s->trigcon = val;
1564 break;
1565 case FIMD_I80IFCON_START0x01B0 ... FIMD_I80IFCON_END0x01BC:
1566 s->i80ifcon[(offset - FIMD_I80IFCON_START0x01B0) >> 2] = val;
1567 break;
1568 case FIMD_COLORGAINCON0x01C0:
1569 s->colorgaincon = val;
1570 break;
1571 case FIMD_LDI_CMDCON00x01D0 ... FIMD_LDI_CMDCON10x01D4:
1572 s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON00x01D0) >> 2] = val;
1573 break;
1574 case FIMD_SIFCCON00x01E0 ... FIMD_SIFCCON20x01E8:
1575 i = (offset - FIMD_SIFCCON00x01E0) >> 2;
1576 if (i != 2) {
1577 s->sifccon[i] = val;
1578 }
1579 break;
1580 case FIMD_HUECOEFCR_START0x01EC ... FIMD_HUECOEFCR_END0x01F4:
1581 i = (offset - FIMD_HUECOEFCR_START0x01EC) >> 2;
1582 s->huecoef_cr[i] = val;
1583 break;
1584 case FIMD_HUECOEFCB_START0x01FC ... FIMD_HUECOEFCB_END0x0208:
1585 i = (offset - FIMD_HUECOEFCB_START0x01FC) >> 2;
1586 s->huecoef_cb[i] = val;
1587 break;
1588 case FIMD_HUEOFFSET0x020C:
1589 s->hueoffset = val;
1590 break;
1591 case FIMD_VIDWALPHA_START0x21C ... FIMD_VIDWALPHA_END0x240:
1592 w = ((offset - FIMD_VIDWALPHA_START0x21C) >> 3);
1593 i = ((offset - FIMD_VIDWALPHA_START0x21C) >> 2) & 1;
1594 if (w == 0) {
1595 s->window[w].alpha_val[i] = val;
1596 } else {
1597 s->window[w].alpha_val[i] = (val & FIMD_VIDALPHA_ALPHA_LOWER0x000F0F0F) |
1598 (s->window[w].alpha_val[i] & FIMD_VIDALPHA_ALPHA_UPPER0x00F0F0F0);
1599 }
1600 break;
1601 case FIMD_BLENDEQ_START0x0244 ... FIMD_BLENDEQ_END0x0250:
1602 s->window[(offset - FIMD_BLENDEQ_START0x0244) >> 2].blendeq = val;
1603 break;
1604 case FIMD_BLENDCON0x0260:
1605 old_value = s->blendcon;
1606 s->blendcon = val;
1607 if ((s->blendcon & FIMD_ALPHA_8BIT(1 << 0)) != (old_value & FIMD_ALPHA_8BIT(1 << 0))) {
1608 for (w = 0; w < NUM_OF_WINDOWS5; w++) {
1609 fimd_update_get_alpha(s, w);
1610 }
1611 }
1612 break;
1613 case FIMD_WRTQOSCON_START0x0264 ... FIMD_WRTQOSCON_END0x0274:
1614 s->window[(offset - FIMD_WRTQOSCON_START0x0264) >> 2].rtqoscon = val;
1615 break;
1616 case FIMD_I80IFCMD_START0x0280 ... FIMD_I80IFCMD_END0x02AC:
1617 s->i80ifcmd[(offset - FIMD_I80IFCMD_START0x0280) >> 2] = val;
1618 break;
1619 case FIMD_VIDW0ADD0_B20x20A0 ... FIMD_VIDW4ADD0_B20x20C0:
1620 if (offset & 0x0004) {
1621 DPRINT_ERROR("bad write offset 0x%08x\n", offset)do { } while (0);
1622 break;
1623 }
1624 w = (offset - FIMD_VIDW0ADD0_B20x20A0) >> 3;
1625 if (fimd_get_buffer_id(&s->window[w]) == 2 &&
1626 s->window[w].buf_start[2] != val) {
1627 s->window[w].buf_start[2] = val;
1628 fimd_update_memory_section(s, w);
1629 break;
1630 }
1631 s->window[w].buf_start[2] = val;
1632 break;
1633 case FIMD_SHD_ADD0_START0x40A0 ... FIMD_SHD_ADD0_END0x40C0:
1634 if (offset & 0x0004) {
1635 DPRINT_ERROR("bad write offset 0x%08x\n", offset)do { } while (0);
1636 break;
1637 }
1638 s->window[(offset - FIMD_SHD_ADD0_START0x40A0) >> 3].shadow_buf_start = val;
1639 break;
1640 case FIMD_SHD_ADD1_START0x40D0 ... FIMD_SHD_ADD1_END0x40F0:
1641 if (offset & 0x0004) {
1642 DPRINT_ERROR("bad write offset 0x%08x\n", offset)do { } while (0);
1643 break;
1644 }
1645 s->window[(offset - FIMD_SHD_ADD1_START0x40D0) >> 3].shadow_buf_end = val;
1646 break;
1647 case FIMD_SHD_ADD2_START0x4100 ... FIMD_SHD_ADD2_END0x4110:
1648 s->window[(offset - FIMD_SHD_ADD2_START0x4100) >> 2].shadow_buf_size = val;
1649 break;
1650 case FIMD_PAL_MEM_START0x2400 ... FIMD_PAL_MEM_END0x37FC:
1651 w = (offset - FIMD_PAL_MEM_START0x2400) >> 10;
1652 i = ((offset - FIMD_PAL_MEM_START0x2400) >> 2) & 0xFF;
1653 s->window[w].palette[i] = val;
1654 break;
1655 case FIMD_PALMEM_AL_START0x0400 ... FIMD_PALMEM_AL_END0x0BFC:
1656 /* Palette memory aliases for windows 0 and 1 */
1657 w = (offset - FIMD_PALMEM_AL_START0x0400) >> 10;
1658 i = ((offset - FIMD_PALMEM_AL_START0x0400) >> 2) & 0xFF;
1659 s->window[w].palette[i] = val;
1660 break;
1661 default:
1662 DPRINT_ERROR("bad write offset 0x%08x\n", offset)do { } while (0);
1663 break;
1664 }
1665}
1666
1667static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
1668 unsigned size)
1669{
1670 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1671 int w, i;
1672 uint32_t ret = 0;
1673
1674 DPRINT_L2("read offset 0x%08x\n", offset)do { } while (0);
1675
1676 switch (offset) {
1677 case FIMD_VIDCON00x0000 ... FIMD_VIDCON30x000C:
1678 return s->vidcon[(offset - FIMD_VIDCON00x0000) >> 2];
1679 case FIMD_VIDTCON_START0x10 ... FIMD_VIDTCON_END0x1C:
1680 return s->vidtcon[(offset - FIMD_VIDTCON_START0x10) >> 2];
1681 case FIMD_WINCON_START0x0020 ... FIMD_WINCON_END0x0030:
1682 return s->window[(offset - FIMD_WINCON_START0x0020) >> 2].wincon;
1683 case FIMD_SHADOWCON0x0034:
1684 return s->shadowcon;
1685 case FIMD_WINCHMAP0x003C:
1686 return s->winchmap;
1687 case FIMD_VIDOSD_START0x0040 ... FIMD_VIDOSD_END0x0088:
1688 w = (offset - FIMD_VIDOSD_START0x0040) >> 4;
1689 i = ((offset - FIMD_VIDOSD_START0x0040) & 0xF) >> 2;
1690 switch (i) {
1691 case 0:
1692 ret = ((s->window[w].lefttop_x & FIMD_VIDOSD_COORD_MASK0x07FF) <<
1693 FIMD_VIDOSD_HOR_SHIFT11) |
1694 (s->window[w].lefttop_y & FIMD_VIDOSD_COORD_MASK0x07FF);
1695 break;
1696 case 1:
1697 ret = ((s->window[w].rightbot_x & FIMD_VIDOSD_COORD_MASK0x07FF) <<
1698 FIMD_VIDOSD_HOR_SHIFT11) |
1699 (s->window[w].rightbot_y & FIMD_VIDOSD_COORD_MASK0x07FF);
1700 break;
1701 case 2:
1702 if (w == 0) {
1703 ret = s->window[w].osdsize;
1704 } else {
1705 ret = (pack_upper_4(s->window[w].alpha_val[0]) <<
1706 FIMD_VIDOSD_AEN0_SHIFT12) |
1707 pack_upper_4(s->window[w].alpha_val[1]);
1708 }
1709 break;
1710 case 3:
1711 if (w != 1 && w != 2) {
1712 DPRINT_ERROR("bad read offset 0x%08x\n", offset)do { } while (0);
1713 return 0xBAADBAAD;
1714 }
1715 ret = s->window[w].osdsize;
1716 break;
1717 }
1718 return ret;
1719 case FIMD_VIDWADD0_START0x00A0 ... FIMD_VIDWADD0_END0x00C4:
1720 w = (offset - FIMD_VIDWADD0_START0x00A0) >> 3;
1721 i = ((offset - FIMD_VIDWADD0_START0x00A0) >> 2) & 1;
1722 return s->window[w].buf_start[i];
1723 case FIMD_VIDWADD1_START0x00D0 ... FIMD_VIDWADD1_END0x00F4:
1724 w = (offset - FIMD_VIDWADD1_START0x00D0) >> 3;
1725 i = ((offset - FIMD_VIDWADD1_START0x00D0) >> 2) & 1;
1726 return s->window[w].buf_end[i];
1727 case FIMD_VIDWADD2_START0x0100 ... FIMD_VIDWADD2_END0x0110:
1728 w = (offset - FIMD_VIDWADD2_START0x0100) >> 2;
1729 return s->window[w].virtpage_width | (s->window[w].virtpage_offsize <<
1730 FIMD_VIDWADD2_OFFSIZE_SHIFT13);
1731 case FIMD_VIDINTCON00x130 ... FIMD_VIDINTCON10x134:
1732 return s->vidintcon[(offset - FIMD_VIDINTCON00x130) >> 2];
1733 case FIMD_WKEYCON_START0x140 ... FIMD_WKEYCON_END0x15C:
1734 w = ((offset - FIMD_WKEYCON_START0x140) >> 3) + 1;
1735 i = ((offset - FIMD_WKEYCON_START0x140) >> 2) & 1;
1736 return s->window[w].keycon[i];
1737 case FIMD_WKEYALPHA_START0x160 ... FIMD_WKEYALPHA_END0x16C:
1738 w = ((offset - FIMD_WKEYALPHA_START0x160) >> 2) + 1;
1739 return s->window[w].keyalpha;
1740 case FIMD_DITHMODE0x170:
1741 return s->dithmode;
1742 case FIMD_WINMAP_START0x180 ... FIMD_WINMAP_END0x190:
1743 return s->window[(offset - FIMD_WINMAP_START0x180) >> 2].winmap;
1744 case FIMD_WPALCON_HIGH0x019C ... FIMD_WPALCON_LOW0x01A0:
1745 return s->wpalcon[(offset - FIMD_WPALCON_HIGH0x019C) >> 2];
1746 case FIMD_TRIGCON0x01A4:
1747 return s->trigcon;
1748 case FIMD_I80IFCON_START0x01B0 ... FIMD_I80IFCON_END0x01BC:
1749 return s->i80ifcon[(offset - FIMD_I80IFCON_START0x01B0) >> 2];
1750 case FIMD_COLORGAINCON0x01C0:
1751 return s->colorgaincon;
1752 case FIMD_LDI_CMDCON00x01D0 ... FIMD_LDI_CMDCON10x01D4:
1753 return s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON00x01D0) >> 2];
1754 case FIMD_SIFCCON00x01E0 ... FIMD_SIFCCON20x01E8:
1755 i = (offset - FIMD_SIFCCON00x01E0) >> 2;
1756 return s->sifccon[i];
1757 case FIMD_HUECOEFCR_START0x01EC ... FIMD_HUECOEFCR_END0x01F4:
1758 i = (offset - FIMD_HUECOEFCR_START0x01EC) >> 2;
1759 return s->huecoef_cr[i];
1760 case FIMD_HUECOEFCB_START0x01FC ... FIMD_HUECOEFCB_END0x0208:
1761 i = (offset - FIMD_HUECOEFCB_START0x01FC) >> 2;
1762 return s->huecoef_cb[i];
1763 case FIMD_HUEOFFSET0x020C:
1764 return s->hueoffset;
1765 case FIMD_VIDWALPHA_START0x21C ... FIMD_VIDWALPHA_END0x240:
1766 w = ((offset - FIMD_VIDWALPHA_START0x21C) >> 3);
1767 i = ((offset - FIMD_VIDWALPHA_START0x21C) >> 2) & 1;
1768 return s->window[w].alpha_val[i] &
1769 (w == 0 ? 0xFFFFFF : FIMD_VIDALPHA_ALPHA_LOWER0x000F0F0F);
1770 case FIMD_BLENDEQ_START0x0244 ... FIMD_BLENDEQ_END0x0250:
1771 return s->window[(offset - FIMD_BLENDEQ_START0x0244) >> 2].blendeq;
1772 case FIMD_BLENDCON0x0260:
1773 return s->blendcon;
1774 case FIMD_WRTQOSCON_START0x0264 ... FIMD_WRTQOSCON_END0x0274:
1775 return s->window[(offset - FIMD_WRTQOSCON_START0x0264) >> 2].rtqoscon;
1776 case FIMD_I80IFCMD_START0x0280 ... FIMD_I80IFCMD_END0x02AC:
1777 return s->i80ifcmd[(offset - FIMD_I80IFCMD_START0x0280) >> 2];
1778 case FIMD_VIDW0ADD0_B20x20A0 ... FIMD_VIDW4ADD0_B20x20C0:
1779 if (offset & 0x0004) {
1780 break;
1781 }
1782 return s->window[(offset - FIMD_VIDW0ADD0_B20x20A0) >> 3].buf_start[2];
1783 case FIMD_SHD_ADD0_START0x40A0 ... FIMD_SHD_ADD0_END0x40C0:
1784 if (offset & 0x0004) {
1785 break;
1786 }
1787 return s->window[(offset - FIMD_SHD_ADD0_START0x40A0) >> 3].shadow_buf_start;
1788 case FIMD_SHD_ADD1_START0x40D0 ... FIMD_SHD_ADD1_END0x40F0:
1789 if (offset & 0x0004) {
1790 break;
1791 }
1792 return s->window[(offset - FIMD_SHD_ADD1_START0x40D0) >> 3].shadow_buf_end;
1793 case FIMD_SHD_ADD2_START0x4100 ... FIMD_SHD_ADD2_END0x4110:
1794 return s->window[(offset - FIMD_SHD_ADD2_START0x4100) >> 2].shadow_buf_size;
1795 case FIMD_PAL_MEM_START0x2400 ... FIMD_PAL_MEM_END0x37FC:
1796 w = (offset - FIMD_PAL_MEM_START0x2400) >> 10;
1797 i = ((offset - FIMD_PAL_MEM_START0x2400) >> 2) & 0xFF;
1798 return s->window[w].palette[i];
1799 case FIMD_PALMEM_AL_START0x0400 ... FIMD_PALMEM_AL_END0x0BFC:
1800 /* Palette aliases for win 0,1 */
1801 w = (offset - FIMD_PALMEM_AL_START0x0400) >> 10;
1802 i = ((offset - FIMD_PALMEM_AL_START0x0400) >> 2) & 0xFF;
1803 return s->window[w].palette[i];
1804 }
1805
1806 DPRINT_ERROR("bad read offset 0x%08x\n", offset)do { } while (0);
1807 return 0xBAADBAAD;
1808}
1809
1810static const MemoryRegionOps exynos4210_fimd_mmio_ops = {
1811 .read = exynos4210_fimd_read,
1812 .write = exynos4210_fimd_write,
1813 .valid = {
1814 .min_access_size = 4,
1815 .max_access_size = 4,
1816 .unaligned = false0
1817 },
1818 .endianness = DEVICE_NATIVE_ENDIAN,
1819};
1820
1821static int exynos4210_fimd_load(void *opaque, int version_id)
1822{
1823 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1824 int w;
1825
1826 if (version_id != 1) {
1827 return -EINVAL22;
1828 }
1829
1830 for (w = 0; w < NUM_OF_WINDOWS5; w++) {
1831 exynos4210_fimd_update_win_bppmode(s, w);
1832 fimd_update_get_alpha(s, w);
1833 fimd_update_memory_section(s, w);
1834 }
1835
1836 /* Redraw the whole screen */
1837 exynos4210_update_resolution(s);
1838 exynos4210_fimd_invalidate(s);
1839 exynos4210_fimd_enable(s, (s->vidcon[0] & FIMD_VIDCON0_ENVID_MASK((1 << 0) | (1 << 1))) ==
1840 FIMD_VIDCON0_ENVID_MASK((1 << 0) | (1 << 1)));
1841 return 0;
1842}
1843
1844static const VMStateDescription exynos4210_fimd_window_vmstate = {
1845 .name = "exynos4210.fimd_window",
1846 .version_id = 1,
1847 .minimum_version_id = 1,
1848 .fields = (VMStateField[]) {
1849 VMSTATE_UINT32(wincon, Exynos4210fimdWindow){ .name = ("wincon"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, wincon) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow *)
0)->wincon)*)0)), },
1850 VMSTATE_UINT32_ARRAY(buf_start, Exynos4210fimdWindow, 3){ .name = ("buf_start"), .version_id = (0), .num = (3), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, buf_start) + ((uint32_t(*)[3])0 - (typeof(((Exynos4210fimdWindow
*)0)->buf_start)*)0)), },
1851 VMSTATE_UINT32_ARRAY(buf_end, Exynos4210fimdWindow, 3){ .name = ("buf_end"), .version_id = (0), .num = (3), .info =
&(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, buf_end) + ((uint32_t(*)[3])0 - (typeof(((Exynos4210fimdWindow
*)0)->buf_end)*)0)), },
1852 VMSTATE_UINT32_ARRAY(keycon, Exynos4210fimdWindow, 2){ .name = ("keycon"), .version_id = (0), .num = (2), .info = &
(vmstate_info_uint32), .size = sizeof(uint32_t), .flags = VMS_ARRAY
, .offset = (__builtin_offsetof(Exynos4210fimdWindow, keycon)
+ ((uint32_t(*)[2])0 - (typeof(((Exynos4210fimdWindow *)0)->
keycon)*)0)), },
1853 VMSTATE_UINT32(keyalpha, Exynos4210fimdWindow){ .name = ("keyalpha"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, keyalpha) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow *
)0)->keyalpha)*)0)), },
1854 VMSTATE_UINT32(winmap, Exynos4210fimdWindow){ .name = ("winmap"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, winmap) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow *)
0)->winmap)*)0)), },
1855 VMSTATE_UINT32(blendeq, Exynos4210fimdWindow){ .name = ("blendeq"), .version_id = (0), .field_exists = (((
void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, blendeq) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow *
)0)->blendeq)*)0)), },
1856 VMSTATE_UINT32(rtqoscon, Exynos4210fimdWindow){ .name = ("rtqoscon"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, rtqoscon) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow *
)0)->rtqoscon)*)0)), },
1857 VMSTATE_UINT32_ARRAY(palette, Exynos4210fimdWindow, 256){ .name = ("palette"), .version_id = (0), .num = (256), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, palette) + ((uint32_t(*)[256])0 - (typeof(((Exynos4210fimdWindow
*)0)->palette)*)0)), },
1858 VMSTATE_UINT32(shadow_buf_start, Exynos4210fimdWindow){ .name = ("shadow_buf_start"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, shadow_buf_start) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->shadow_buf_start)*)0)), },
1859 VMSTATE_UINT32(shadow_buf_end, Exynos4210fimdWindow){ .name = ("shadow_buf_end"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, shadow_buf_end) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->shadow_buf_end)*)0)), },
1860 VMSTATE_UINT32(shadow_buf_size, Exynos4210fimdWindow){ .name = ("shadow_buf_size"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, shadow_buf_size) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->shadow_buf_size)*)0)), },
1861 VMSTATE_UINT16(lefttop_x, Exynos4210fimdWindow){ .name = ("lefttop_x"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, lefttop_x) + ((uint16_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->lefttop_x)*)0)), },
1862 VMSTATE_UINT16(lefttop_y, Exynos4210fimdWindow){ .name = ("lefttop_y"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, lefttop_y) + ((uint16_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->lefttop_y)*)0)), },
1863 VMSTATE_UINT16(rightbot_x, Exynos4210fimdWindow){ .name = ("rightbot_x"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, rightbot_x) + ((uint16_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->rightbot_x)*)0)), },
1864 VMSTATE_UINT16(rightbot_y, Exynos4210fimdWindow){ .name = ("rightbot_y"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, rightbot_y) + ((uint16_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->rightbot_y)*)0)), },
1865 VMSTATE_UINT32(osdsize, Exynos4210fimdWindow){ .name = ("osdsize"), .version_id = (0), .field_exists = (((
void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, osdsize) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow *
)0)->osdsize)*)0)), },
1866 VMSTATE_UINT32_ARRAY(alpha_val, Exynos4210fimdWindow, 2){ .name = ("alpha_val"), .version_id = (0), .num = (2), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, alpha_val) + ((uint32_t(*)[2])0 - (typeof(((Exynos4210fimdWindow
*)0)->alpha_val)*)0)), },
1867 VMSTATE_UINT16(virtpage_width, Exynos4210fimdWindow){ .name = ("virtpage_width"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, virtpage_width) + ((uint16_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->virtpage_width)*)0)), },
1868 VMSTATE_UINT16(virtpage_offsize, Exynos4210fimdWindow){ .name = ("virtpage_offsize"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, virtpage_offsize) + ((uint16_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->virtpage_offsize)*)0)), },
1869 VMSTATE_END_OF_LIST(){}
1870 }
1871};
1872
1873static const VMStateDescription exynos4210_fimd_vmstate = {
1874 .name = "exynos4210.fimd",
1875 .version_id = 1,
1876 .minimum_version_id = 1,
1877 .post_load = exynos4210_fimd_load,
1878 .fields = (VMStateField[]) {
1879 VMSTATE_UINT32_ARRAY(vidcon, Exynos4210fimdState, 4){ .name = ("vidcon"), .version_id = (0), .num = (4), .info = &
(vmstate_info_uint32), .size = sizeof(uint32_t), .flags = VMS_ARRAY
, .offset = (__builtin_offsetof(Exynos4210fimdState, vidcon) +
((uint32_t(*)[4])0 - (typeof(((Exynos4210fimdState *)0)->
vidcon)*)0)), },
1880 VMSTATE_UINT32_ARRAY(vidtcon, Exynos4210fimdState, 4){ .name = ("vidtcon"), .version_id = (0), .num = (4), .info =
&(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, vidtcon) + ((uint32_t(*)[4])0 - (typeof(((Exynos4210fimdState
*)0)->vidtcon)*)0)), },
1881 VMSTATE_UINT32(shadowcon, Exynos4210fimdState){ .name = ("shadowcon"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, shadowcon) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState *
)0)->shadowcon)*)0)), },
1882 VMSTATE_UINT32(winchmap, Exynos4210fimdState){ .name = ("winchmap"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, winchmap) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState *
)0)->winchmap)*)0)), },
1883 VMSTATE_UINT32_ARRAY(vidintcon, Exynos4210fimdState, 2){ .name = ("vidintcon"), .version_id = (0), .num = (2), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, vidintcon) + ((uint32_t(*)[2])0 - (typeof(((Exynos4210fimdState
*)0)->vidintcon)*)0)), },
1884 VMSTATE_UINT32(dithmode, Exynos4210fimdState){ .name = ("dithmode"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, dithmode) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState *
)0)->dithmode)*)0)), },
1885 VMSTATE_UINT32_ARRAY(wpalcon, Exynos4210fimdState, 2){ .name = ("wpalcon"), .version_id = (0), .num = (2), .info =
&(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, wpalcon) + ((uint32_t(*)[2])0 - (typeof(((Exynos4210fimdState
*)0)->wpalcon)*)0)), },
1886 VMSTATE_UINT32(trigcon, Exynos4210fimdState){ .name = ("trigcon"), .version_id = (0), .field_exists = (((
void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, trigcon) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState *)
0)->trigcon)*)0)), },
1887 VMSTATE_UINT32_ARRAY(i80ifcon, Exynos4210fimdState, 4){ .name = ("i80ifcon"), .version_id = (0), .num = (4), .info =
&(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, i80ifcon) + ((uint32_t(*)[4])0 - (typeof(((Exynos4210fimdState
*)0)->i80ifcon)*)0)), },
1888 VMSTATE_UINT32(colorgaincon, Exynos4210fimdState){ .name = ("colorgaincon"), .version_id = (0), .field_exists =
(((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, colorgaincon) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState
*)0)->colorgaincon)*)0)), },
1889 VMSTATE_UINT32_ARRAY(ldi_cmdcon, Exynos4210fimdState, 2){ .name = ("ldi_cmdcon"), .version_id = (0), .num = (2), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, ldi_cmdcon) + ((uint32_t(*)[2])0 - (typeof(((Exynos4210fimdState
*)0)->ldi_cmdcon)*)0)), },
1890 VMSTATE_UINT32_ARRAY(sifccon, Exynos4210fimdState, 3){ .name = ("sifccon"), .version_id = (0), .num = (3), .info =
&(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, sifccon) + ((uint32_t(*)[3])0 - (typeof(((Exynos4210fimdState
*)0)->sifccon)*)0)), },
1891 VMSTATE_UINT32_ARRAY(huecoef_cr, Exynos4210fimdState, 4){ .name = ("huecoef_cr"), .version_id = (0), .num = (4), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, huecoef_cr) + ((uint32_t(*)[4])0 - (typeof(((Exynos4210fimdState
*)0)->huecoef_cr)*)0)), },
1892 VMSTATE_UINT32_ARRAY(huecoef_cb, Exynos4210fimdState, 4){ .name = ("huecoef_cb"), .version_id = (0), .num = (4), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, huecoef_cb) + ((uint32_t(*)[4])0 - (typeof(((Exynos4210fimdState
*)0)->huecoef_cb)*)0)), },
1893 VMSTATE_UINT32(hueoffset, Exynos4210fimdState){ .name = ("hueoffset"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, hueoffset) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState *
)0)->hueoffset)*)0)), },
1894 VMSTATE_UINT32_ARRAY(i80ifcmd, Exynos4210fimdState, 12){ .name = ("i80ifcmd"), .version_id = (0), .num = (12), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, i80ifcmd) + ((uint32_t(*)[12])0 - (typeof(((Exynos4210fimdState
*)0)->i80ifcmd)*)0)), },
1895 VMSTATE_UINT32(blendcon, Exynos4210fimdState){ .name = ("blendcon"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, blendcon) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState *
)0)->blendcon)*)0)), },
1896 VMSTATE_STRUCT_ARRAY(window, Exynos4210fimdState, 5, 1,{ .name = ("window"), .num = (5), .field_exists = (((void*)0)
), .version_id = (1), .vmsd = &(exynos4210_fimd_window_vmstate
), .size = sizeof(Exynos4210fimdWindow), .flags = VMS_STRUCT|
VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState,
window) + ((Exynos4210fimdWindow(*)[5])0 - (typeof(((Exynos4210fimdState
*)0)->window)*)0)),}
1897 exynos4210_fimd_window_vmstate, Exynos4210fimdWindow){ .name = ("window"), .num = (5), .field_exists = (((void*)0)
), .version_id = (1), .vmsd = &(exynos4210_fimd_window_vmstate
), .size = sizeof(Exynos4210fimdWindow), .flags = VMS_STRUCT|
VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState,
window) + ((Exynos4210fimdWindow(*)[5])0 - (typeof(((Exynos4210fimdState
*)0)->window)*)0)),},
1898 VMSTATE_END_OF_LIST(){}
1899 }
1900};
1901
1902static const GraphicHwOps exynos4210_fimd_ops = {
1903 .invalidate = exynos4210_fimd_invalidate,
1904 .gfx_update = exynos4210_fimd_update,
1905};
1906
1907static int exynos4210_fimd_init(SysBusDevice *dev)
1908{
1909 Exynos4210fimdState *s = EXYNOS4210_FIMD(dev)((Exynos4210fimdState *)object_dynamic_cast_assert(((Object *
)((dev))), ("exynos4210.fimd"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/exynos4210_fimd.c"
, 1909, __func__));
1910
1911 s->ifb = NULL((void*)0);
1912
1913 sysbus_init_irq(dev, &s->irq[0]);
1914 sysbus_init_irq(dev, &s->irq[1]);
1915 sysbus_init_irq(dev, &s->irq[2]);
1916
1917 memory_region_init_io(&s->iomem, OBJECT(s)((Object *)(s)), &exynos4210_fimd_mmio_ops, s,
1918 "exynos4210.fimd", FIMD_REGS_SIZE0x4114);
1919 sysbus_init_mmio(dev, &s->iomem);
1920 s->console = graphic_console_init(DEVICE(dev)((DeviceState *)object_dynamic_cast_assert(((Object *)((dev))
), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/exynos4210_fimd.c"
, 1920, __func__)), &exynos4210_fimd_ops, s);
1921
1922 return 0;
1923}
1924
1925static void exynos4210_fimd_class_init(ObjectClass *klass, void *data)
1926{
1927 DeviceClass *dc = DEVICE_CLASS(klass)((DeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/exynos4210_fimd.c"
, 1927, __func__));
1928 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass)((SysBusDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("sys-bus-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/display/exynos4210_fimd.c"
, 1928, __func__));
1929
1930 dc->vmsd = &exynos4210_fimd_vmstate;
1931 dc->reset = exynos4210_fimd_reset;
1932 k->init = exynos4210_fimd_init;
1933}
1934
1935static const TypeInfo exynos4210_fimd_info = {
1936 .name = TYPE_EXYNOS4210_FIMD"exynos4210.fimd",
1937 .parent = TYPE_SYS_BUS_DEVICE"sys-bus-device",
1938 .instance_size = sizeof(Exynos4210fimdState),
1939 .class_init = exynos4210_fimd_class_init,
1940};
1941
1942static void exynos4210_fimd_register_types(void)
1943{
1944 type_register_static(&exynos4210_fimd_info);
1945}
1946
1947type_init(exynos4210_fimd_register_types)static void __attribute__((constructor)) do_qemu_init_exynos4210_fimd_register_types
(void) { register_module_init(exynos4210_fimd_register_types,
MODULE_INIT_QOM); }