Bug Summary

File:hw/ppc/ppc405_boards.c
Location:line 356, column 9
Description:Value stored to 'initrd_base' is never read

Annotated Source Code

1/*
2 * QEMU PowerPC 405 evaluation boards emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#include "hw/hw.h"
25#include "hw/ppc/ppc.h"
26#include "ppc405.h"
27#include "hw/timer/m48t59.h"
28#include "hw/block/flash.h"
29#include "sysemu/sysemu.h"
30#include "sysemu/qtest.h"
31#include "block/block.h"
32#include "hw/boards.h"
33#include "qemu/log.h"
34#include "qemu/error-report.h"
35#include "hw/loader.h"
36#include "sysemu/blockdev.h"
37#include "exec/address-spaces.h"
38
39#define BIOS_FILENAME"ppc405_rom.bin" "ppc405_rom.bin"
40#define BIOS_SIZE(2048 * 1024) (2048 * 1024)
41
42#define KERNEL_LOAD_ADDR0x00000000 0x00000000
43#define INITRD_LOAD_ADDR0x01800000 0x01800000
44
45#define USE_FLASH_BIOS
46
47//#define DEBUG_BOARD_INIT
48
49/*****************************************************************************/
50/* PPC405EP reference board (IBM) */
51/* Standalone board with:
52 * - PowerPC 405EP CPU
53 * - SDRAM (0x00000000)
54 * - Flash (0xFFF80000)
55 * - SRAM (0xFFF00000)
56 * - NVRAM (0xF0000000)
57 * - FPGA (0xF0300000)
58 */
59typedef struct ref405ep_fpga_t ref405ep_fpga_t;
60struct ref405ep_fpga_t {
61 uint8_t reg0;
62 uint8_t reg1;
63};
64
65static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr)
66{
67 ref405ep_fpga_t *fpga;
68 uint32_t ret;
69
70 fpga = opaque;
71 switch (addr) {
72 case 0x0:
73 ret = fpga->reg0;
74 break;
75 case 0x1:
76 ret = fpga->reg1;
77 break;
78 default:
79 ret = 0;
80 break;
81 }
82
83 return ret;
84}
85
86static void ref405ep_fpga_writeb (void *opaque,
87 hwaddr addr, uint32_t value)
88{
89 ref405ep_fpga_t *fpga;
90
91 fpga = opaque;
92 switch (addr) {
93 case 0x0:
94 /* Read only */
95 break;
96 case 0x1:
97 fpga->reg1 = value;
98 break;
99 default:
100 break;
101 }
102}
103
104static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr)
105{
106 uint32_t ret;
107
108 ret = ref405ep_fpga_readb(opaque, addr) << 8;
109 ret |= ref405ep_fpga_readb(opaque, addr + 1);
110
111 return ret;
112}
113
114static void ref405ep_fpga_writew (void *opaque,
115 hwaddr addr, uint32_t value)
116{
117 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
118 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
119}
120
121static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr)
122{
123 uint32_t ret;
124
125 ret = ref405ep_fpga_readb(opaque, addr) << 24;
126 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
127 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
128 ret |= ref405ep_fpga_readb(opaque, addr + 3);
129
130 return ret;
131}
132
133static void ref405ep_fpga_writel (void *opaque,
134 hwaddr addr, uint32_t value)
135{
136 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
137 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
138 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
139 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
140}
141
142static const MemoryRegionOps ref405ep_fpga_ops = {
143 .old_mmio = {
144 .read = {
145 ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl,
146 },
147 .write = {
148 ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel,
149 },
150 },
151 .endianness = DEVICE_NATIVE_ENDIAN,
152};
153
154static void ref405ep_fpga_reset (void *opaque)
155{
156 ref405ep_fpga_t *fpga;
157
158 fpga = opaque;
159 fpga->reg0 = 0x00;
160 fpga->reg1 = 0x0F;
161}
162
163static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
164{
165 ref405ep_fpga_t *fpga;
166 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1)((MemoryRegion *) g_malloc_n ((1), sizeof (MemoryRegion)));
167
168 fpga = g_malloc0(sizeof(ref405ep_fpga_t));
169 memory_region_init_io(fpga_memory, NULL((void*)0), &ref405ep_fpga_ops, fpga,
170 "fpga", 0x00000100);
171 memory_region_add_subregion(sysmem, base, fpga_memory);
172 qemu_register_reset(&ref405ep_fpga_reset, fpga);
173}
174
175static void ref405ep_init(QEMUMachineInitArgs *args)
176{
177 ram_addr_t ram_size = args->ram_size;
178 const char *kernel_filename = args->kernel_filename;
179 const char *kernel_cmdline = args->kernel_cmdline;
180 const char *initrd_filename = args->initrd_filename;
181 char *filename;
182 ppc4xx_bd_info_t bd;
183 CPUPPCState *env;
184 qemu_irq *pic;
185 MemoryRegion *bios;
186 MemoryRegion *sram = g_new(MemoryRegion, 1)((MemoryRegion *) g_malloc_n ((1), sizeof (MemoryRegion)));
187 ram_addr_t bdloc;
188 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
189 hwaddr ram_bases[2], ram_sizes[2];
190 target_ulong sram_size;
191 long bios_size;
192 //int phy_addr = 0;
193 //static int phy_addr = 1;
194 target_ulong kernel_base, initrd_base;
195 long kernel_size, initrd_size;
196 int linux_boot;
197 int fl_idx, fl_sectors, len;
198 DriveInfo *dinfo;
199 MemoryRegion *sysmem = get_system_memory();
200
201 /* XXX: fix this */
202 memory_region_init_ram(&ram_memories[0], NULL((void*)0), "ef405ep.ram", 0x08000000);
203 vmstate_register_ram_global(&ram_memories[0]);
204 ram_bases[0] = 0;
205 ram_sizes[0] = 0x08000000;
206 memory_region_init(&ram_memories[1], NULL((void*)0), "ef405ep.ram1", 0);
207 ram_bases[1] = 0x00000000;
208 ram_sizes[1] = 0x00000000;
209 ram_size = 128 * 1024 * 1024;
210#ifdef DEBUG_BOARD_INIT
211 printf("%s: register cpu\n", __func__);
212#endif
213 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
214 33333333, &pic, kernel_filename == NULL((void*)0) ? 0 : 1);
215 /* allocate SRAM */
216 sram_size = 512 * 1024;
217 memory_region_init_ram(sram, NULL((void*)0), "ef405ep.sram", sram_size);
218 vmstate_register_ram_global(sram);
219 memory_region_add_subregion(sysmem, 0xFFF00000, sram);
220 /* allocate and load BIOS */
221#ifdef DEBUG_BOARD_INIT
222 printf("%s: register BIOS\n", __func__);
223#endif
224 fl_idx = 0;
225#ifdef USE_FLASH_BIOS
226 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
227 if (dinfo) {
228 bios_size = bdrv_getlength(dinfo->bdrv);
229 fl_sectors = (bios_size + 65535) >> 16;
230#ifdef DEBUG_BOARD_INIT
231 printf("Register parallel flash %d size %lx"
232 " at addr %lx '%s' %d\n",
233 fl_idx, bios_size, -bios_size,
234 bdrv_get_device_name(dinfo->bdrv), fl_sectors);
235#endif
236 pflash_cfi02_register((uint32_t)(-bios_size),
237 NULL((void*)0), "ef405ep.bios", bios_size,
238 dinfo->bdrv, 65536, fl_sectors, 1,
239 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
240 1);
241 fl_idx++;
242 } else
243#endif
244 {
245#ifdef DEBUG_BOARD_INIT
246 printf("Load BIOS from file\n");
247#endif
248 bios = g_new(MemoryRegion, 1)((MemoryRegion *) g_malloc_n ((1), sizeof (MemoryRegion)));
249 memory_region_init_ram(bios, NULL((void*)0), "ef405ep.bios", BIOS_SIZE(2048 * 1024));
250 vmstate_register_ram_global(bios);
251 if (bios_name == NULL((void*)0))
252 bios_name = BIOS_FILENAME"ppc405_rom.bin";
253 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS0, bios_name);
254 if (filename) {
255 bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
256 g_free(filename);
257 if (bios_size < 0 || bios_size > BIOS_SIZE(2048 * 1024)) {
258 error_report("Could not load PowerPC BIOS '%s'", bios_name);
259 exit(1);
260 }
261 bios_size = (bios_size + 0xfff) & ~0xfff;
262 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
263 } else if (!qtest_enabled() || kernel_filename != NULL((void*)0)) {
264 error_report("Could not load PowerPC BIOS '%s'", bios_name);
265 exit(1);
266 } else {
267 /* Avoid an uninitialized variable warning */
268 bios_size = -1;
269 }
270 memory_region_set_readonly(bios, true1);
271 }
272 /* Register FPGA */
273#ifdef DEBUG_BOARD_INIT
274 printf("%s: register FPGA\n", __func__);
275#endif
276 ref405ep_fpga_init(sysmem, 0xF0300000);
277 /* Register NVRAM */
278#ifdef DEBUG_BOARD_INIT
279 printf("%s: register NVRAM\n", __func__);
280#endif
281 m48t59_init(NULL((void*)0), 0xF0000000, 0, 8192, 8);
282 /* Load kernel */
283 linux_boot = (kernel_filename != NULL((void*)0));
284 if (linux_boot) {
285#ifdef DEBUG_BOARD_INIT
286 printf("%s: load kernel\n", __func__);
287#endif
288 memset(&bd, 0, sizeof(bd));
289 bd.bi_memstart = 0x00000000;
290 bd.bi_memsize = ram_size;
291 bd.bi_flashstart = -bios_size;
292 bd.bi_flashsize = -bios_size;
293 bd.bi_flashoffset = 0;
294 bd.bi_sramstart = 0xFFF00000;
295 bd.bi_sramsize = sram_size;
296 bd.bi_bootflags = 0;
297 bd.bi_intfreq = 133333333;
298 bd.bi_busfreq = 33333333;
299 bd.bi_baudrate = 115200;
300 bd.bi_s_version[0] = 'Q';
301 bd.bi_s_version[1] = 'M';
302 bd.bi_s_version[2] = 'U';
303 bd.bi_s_version[3] = '\0';
304 bd.bi_r_version[0] = 'Q';
305 bd.bi_r_version[1] = 'E';
306 bd.bi_r_version[2] = 'M';
307 bd.bi_r_version[3] = 'U';
308 bd.bi_r_version[4] = '\0';
309 bd.bi_procfreq = 133333333;
310 bd.bi_plb_busfreq = 33333333;
311 bd.bi_pci_busfreq = 33333333;
312 bd.bi_opbfreq = 33333333;
313 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
314 env->gpr[3] = bdloc;
315 kernel_base = KERNEL_LOAD_ADDR0x00000000;
316 /* now we can load the kernel */
317 kernel_size = load_image_targphys(kernel_filename, kernel_base,
318 ram_size - kernel_base);
319 if (kernel_size < 0) {
320 fprintf(stderrstderr, "qemu: could not load kernel '%s'\n",
321 kernel_filename);
322 exit(1);
323 }
324 printf("Load kernel size %ld at " TARGET_FMT_lx"%08x",
325 kernel_size, kernel_base);
326 /* load initrd */
327 if (initrd_filename) {
328 initrd_base = INITRD_LOAD_ADDR0x01800000;
329 initrd_size = load_image_targphys(initrd_filename, initrd_base,
330 ram_size - initrd_base);
331 if (initrd_size < 0) {
332 fprintf(stderrstderr, "qemu: could not load initial ram disk '%s'\n",
333 initrd_filename);
334 exit(1);
335 }
336 } else {
337 initrd_base = 0;
338 initrd_size = 0;
339 }
340 env->gpr[4] = initrd_base;
341 env->gpr[5] = initrd_size;
342 if (kernel_cmdline != NULL((void*)0)) {
343 len = strlen(kernel_cmdline);
344 bdloc -= ((len + 255) & ~255);
345 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
346 env->gpr[6] = bdloc;
347 env->gpr[7] = bdloc + len;
348 } else {
349 env->gpr[6] = 0;
350 env->gpr[7] = 0;
351 }
352 env->nip = KERNEL_LOAD_ADDR0x00000000;
353 } else {
354 kernel_base = 0;
355 kernel_size = 0;
356 initrd_base = 0;
Value stored to 'initrd_base' is never read
357 initrd_size = 0;
358 bdloc = 0;
359 }
360#ifdef DEBUG_BOARD_INIT
361 printf("bdloc " RAM_ADDR_FMT"%" "l" "x" "\n", bdloc);
362 printf("%s: Done\n", __func__);
363#endif
364}
365
366static QEMUMachine ref405ep_machine = {
367 .name = "ref405ep",
368 .desc = "ref405ep",
369 .init = ref405ep_init,
370};
371
372/*****************************************************************************/
373/* AMCC Taihu evaluation board */
374/* - PowerPC 405EP processor
375 * - SDRAM 128 MB at 0x00000000
376 * - Boot flash 2 MB at 0xFFE00000
377 * - Application flash 32 MB at 0xFC000000
378 * - 2 serial ports
379 * - 2 ethernet PHY
380 * - 1 USB 1.1 device 0x50000000
381 * - 1 LCD display 0x50100000
382 * - 1 CPLD 0x50100000
383 * - 1 I2C EEPROM
384 * - 1 I2C thermal sensor
385 * - a set of LEDs
386 * - bit-bang SPI port using GPIOs
387 * - 1 EBC interface connector 0 0x50200000
388 * - 1 cardbus controller + expansion slot.
389 * - 1 PCI expansion slot.
390 */
391typedef struct taihu_cpld_t taihu_cpld_t;
392struct taihu_cpld_t {
393 uint8_t reg0;
394 uint8_t reg1;
395};
396
397static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr)
398{
399 taihu_cpld_t *cpld;
400 uint32_t ret;
401
402 cpld = opaque;
403 switch (addr) {
404 case 0x0:
405 ret = cpld->reg0;
406 break;
407 case 0x1:
408 ret = cpld->reg1;
409 break;
410 default:
411 ret = 0;
412 break;
413 }
414
415 return ret;
416}
417
418static void taihu_cpld_writeb (void *opaque,
419 hwaddr addr, uint32_t value)
420{
421 taihu_cpld_t *cpld;
422
423 cpld = opaque;
424 switch (addr) {
425 case 0x0:
426 /* Read only */
427 break;
428 case 0x1:
429 cpld->reg1 = value;
430 break;
431 default:
432 break;
433 }
434}
435
436static uint32_t taihu_cpld_readw (void *opaque, hwaddr addr)
437{
438 uint32_t ret;
439
440 ret = taihu_cpld_readb(opaque, addr) << 8;
441 ret |= taihu_cpld_readb(opaque, addr + 1);
442
443 return ret;
444}
445
446static void taihu_cpld_writew (void *opaque,
447 hwaddr addr, uint32_t value)
448{
449 taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
450 taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
451}
452
453static uint32_t taihu_cpld_readl (void *opaque, hwaddr addr)
454{
455 uint32_t ret;
456
457 ret = taihu_cpld_readb(opaque, addr) << 24;
458 ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
459 ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
460 ret |= taihu_cpld_readb(opaque, addr + 3);
461
462 return ret;
463}
464
465static void taihu_cpld_writel (void *opaque,
466 hwaddr addr, uint32_t value)
467{
468 taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
469 taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
470 taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
471 taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
472}
473
474static const MemoryRegionOps taihu_cpld_ops = {
475 .old_mmio = {
476 .read = { taihu_cpld_readb, taihu_cpld_readw, taihu_cpld_readl, },
477 .write = { taihu_cpld_writeb, taihu_cpld_writew, taihu_cpld_writel, },
478 },
479 .endianness = DEVICE_NATIVE_ENDIAN,
480};
481
482static void taihu_cpld_reset (void *opaque)
483{
484 taihu_cpld_t *cpld;
485
486 cpld = opaque;
487 cpld->reg0 = 0x01;
488 cpld->reg1 = 0x80;
489}
490
491static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
492{
493 taihu_cpld_t *cpld;
494 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1)((MemoryRegion *) g_malloc_n ((1), sizeof (MemoryRegion)));
495
496 cpld = g_malloc0(sizeof(taihu_cpld_t));
497 memory_region_init_io(cpld_memory, NULL((void*)0), &taihu_cpld_ops, cpld, "cpld", 0x100);
498 memory_region_add_subregion(sysmem, base, cpld_memory);
499 qemu_register_reset(&taihu_cpld_reset, cpld);
500}
501
502static void taihu_405ep_init(QEMUMachineInitArgs *args)
503{
504 ram_addr_t ram_size = args->ram_size;
505 const char *kernel_filename = args->kernel_filename;
506 const char *initrd_filename = args->initrd_filename;
507 char *filename;
508 qemu_irq *pic;
509 MemoryRegion *sysmem = get_system_memory();
510 MemoryRegion *bios;
511 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
512 hwaddr ram_bases[2], ram_sizes[2];
513 long bios_size;
514 target_ulong kernel_base, initrd_base;
515 long kernel_size, initrd_size;
516 int linux_boot;
517 int fl_idx, fl_sectors;
518 DriveInfo *dinfo;
519
520 /* RAM is soldered to the board so the size cannot be changed */
521 memory_region_init_ram(&ram_memories[0], NULL((void*)0),
522 "taihu_405ep.ram-0", 0x04000000);
523 vmstate_register_ram_global(&ram_memories[0]);
524 ram_bases[0] = 0;
525 ram_sizes[0] = 0x04000000;
526 memory_region_init_ram(&ram_memories[1], NULL((void*)0),
527 "taihu_405ep.ram-1", 0x04000000);
528 vmstate_register_ram_global(&ram_memories[1]);
529 ram_bases[1] = 0x04000000;
530 ram_sizes[1] = 0x04000000;
531 ram_size = 0x08000000;
532#ifdef DEBUG_BOARD_INIT
533 printf("%s: register cpu\n", __func__);
534#endif
535 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
536 33333333, &pic, kernel_filename == NULL((void*)0) ? 0 : 1);
537 /* allocate and load BIOS */
538#ifdef DEBUG_BOARD_INIT
539 printf("%s: register BIOS\n", __func__);
540#endif
541 fl_idx = 0;
542#if defined(USE_FLASH_BIOS)
543 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
544 if (dinfo) {
545 bios_size = bdrv_getlength(dinfo->bdrv);
546 /* XXX: should check that size is 2MB */
547 // bios_size = 2 * 1024 * 1024;
548 fl_sectors = (bios_size + 65535) >> 16;
549#ifdef DEBUG_BOARD_INIT
550 printf("Register parallel flash %d size %lx"
551 " at addr %lx '%s' %d\n",
552 fl_idx, bios_size, -bios_size,
553 bdrv_get_device_name(dinfo->bdrv), fl_sectors);
554#endif
555 pflash_cfi02_register((uint32_t)(-bios_size),
556 NULL((void*)0), "taihu_405ep.bios", bios_size,
557 dinfo->bdrv, 65536, fl_sectors, 1,
558 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
559 1);
560 fl_idx++;
561 } else
562#endif
563 {
564#ifdef DEBUG_BOARD_INIT
565 printf("Load BIOS from file\n");
566#endif
567 if (bios_name == NULL((void*)0))
568 bios_name = BIOS_FILENAME"ppc405_rom.bin";
569 bios = g_new(MemoryRegion, 1)((MemoryRegion *) g_malloc_n ((1), sizeof (MemoryRegion)));
570 memory_region_init_ram(bios, NULL((void*)0), "taihu_405ep.bios", BIOS_SIZE(2048 * 1024));
571 vmstate_register_ram_global(bios);
572 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS0, bios_name);
573 if (filename) {
574 bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
575 g_free(filename);
576 if (bios_size < 0 || bios_size > BIOS_SIZE(2048 * 1024)) {
577 error_report("Could not load PowerPC BIOS '%s'", bios_name);
578 exit(1);
579 }
580 bios_size = (bios_size + 0xfff) & ~0xfff;
581 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
582 } else if (!qtest_enabled()) {
583 error_report("Could not load PowerPC BIOS '%s'", bios_name);
584 exit(1);
585 }
586 memory_region_set_readonly(bios, true1);
587 }
588 /* Register Linux flash */
589 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
590 if (dinfo) {
591 bios_size = bdrv_getlength(dinfo->bdrv);
592 /* XXX: should check that size is 32MB */
593 bios_size = 32 * 1024 * 1024;
594 fl_sectors = (bios_size + 65535) >> 16;
595#ifdef DEBUG_BOARD_INIT
596 printf("Register parallel flash %d size %lx"
597 " at addr " TARGET_FMT_lx"%08x" " '%s'\n",
598 fl_idx, bios_size, (target_ulong)0xfc000000,
599 bdrv_get_device_name(dinfo->bdrv));
600#endif
601 pflash_cfi02_register(0xfc000000, NULL((void*)0), "taihu_405ep.flash", bios_size,
602 dinfo->bdrv, 65536, fl_sectors, 1,
603 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
604 1);
605 fl_idx++;
606 }
607 /* Register CLPD & LCD display */
608#ifdef DEBUG_BOARD_INIT
609 printf("%s: register CPLD\n", __func__);
610#endif
611 taihu_cpld_init(sysmem, 0x50100000);
612 /* Load kernel */
613 linux_boot = (kernel_filename != NULL((void*)0));
614 if (linux_boot) {
615#ifdef DEBUG_BOARD_INIT
616 printf("%s: load kernel\n", __func__);
617#endif
618 kernel_base = KERNEL_LOAD_ADDR0x00000000;
619 /* now we can load the kernel */
620 kernel_size = load_image_targphys(kernel_filename, kernel_base,
621 ram_size - kernel_base);
622 if (kernel_size < 0) {
623 fprintf(stderrstderr, "qemu: could not load kernel '%s'\n",
624 kernel_filename);
625 exit(1);
626 }
627 /* load initrd */
628 if (initrd_filename) {
629 initrd_base = INITRD_LOAD_ADDR0x01800000;
630 initrd_size = load_image_targphys(initrd_filename, initrd_base,
631 ram_size - initrd_base);
632 if (initrd_size < 0) {
633 fprintf(stderrstderr,
634 "qemu: could not load initial ram disk '%s'\n",
635 initrd_filename);
636 exit(1);
637 }
638 } else {
639 initrd_base = 0;
640 initrd_size = 0;
641 }
642 } else {
643 kernel_base = 0;
644 kernel_size = 0;
645 initrd_base = 0;
646 initrd_size = 0;
647 }
648#ifdef DEBUG_BOARD_INIT
649 printf("%s: Done\n", __func__);
650#endif
651}
652
653static QEMUMachine taihu_machine = {
654 .name = "taihu",
655 .desc = "taihu",
656 .init = taihu_405ep_init,
657};
658
659static void ppc405_machine_init(void)
660{
661 qemu_register_machine(&ref405ep_machine);
662 qemu_register_machine(&taihu_machine);
663}
664
665machine_init(ppc405_machine_init)static void __attribute__((constructor)) do_qemu_init_ppc405_machine_init
(void) { register_module_init(ppc405_machine_init, MODULE_INIT_MACHINE
); };