Bug Summary

File:hw/arm/../exynos4210_fimd.c
Location:line 1288, column 17
Description:Value stored to 'is_dirty' is never read

Annotated Source Code

1/*
2 * Samsung exynos4210 Display Controller (FIMD)
3 *
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
5 * All rights reserved.
6 * Based on LCD controller for Samsung S5PC1xx-based board emulation
7 * by Kirill Batuzov <batuzovk@ispras.ru>
8 *
9 * Contributed by Mitsyanko Igor <i.mitsyanko@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25#include "qemu-common.h"
26#include "cpu-all.h"
27#include "sysbus.h"
28#include "console.h"
29#include "pixel_ops.h"
30#include "bswap.h"
31
32/* Debug messages configuration */
33#define EXYNOS4210_FIMD_DEBUG0 0
34#define EXYNOS4210_FIMD_MODE_TRACE0 0
35
36#if EXYNOS4210_FIMD_DEBUG0 == 0
37 #define DPRINT_L1(fmt, args...)do { } while (0) do { } while (0)
38 #define DPRINT_L2(fmt, args...)do { } while (0) do { } while (0)
39 #define DPRINT_ERROR(fmt, args...)do { } while (0) do { } while (0)
40#elif EXYNOS4210_FIMD_DEBUG0 == 1
41 #define DPRINT_L1(fmt, args...)do { } while (0) \
42 do {fprintf(stderrstderr, "QEMU FIMD: "fmt, ## args); } while (0)
43 #define DPRINT_L2(fmt, args...)do { } while (0) do { } while (0)
44 #define DPRINT_ERROR(fmt, args...)do { } while (0) \
45 do {fprintf(stderrstderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
46#else
47 #define DPRINT_L1(fmt, args...)do { } while (0) \
48 do {fprintf(stderrstderr, "QEMU FIMD: "fmt, ## args); } while (0)
49 #define DPRINT_L2(fmt, args...)do { } while (0) \
50 do {fprintf(stderrstderr, "QEMU FIMD: "fmt, ## args); } while (0)
51 #define DPRINT_ERROR(fmt, args...)do { } while (0) \
52 do {fprintf(stderrstderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
53#endif
54
55#if EXYNOS4210_FIMD_MODE_TRACE0 == 0
56 #define DPRINT_TRACE(fmt, args...)do { } while (0) do { } while (0)
57#else
58 #define DPRINT_TRACE(fmt, args...)do { } while (0) \
59 do {fprintf(stderrstderr, "QEMU FIMD: "fmt, ## args); } while (0)
60#endif
61
62#define NUM_OF_WINDOWS5 5
63#define FIMD_REGS_SIZE0x4114 0x4114
64
65/* Video main control registers */
66#define FIMD_VIDCON00x0000 0x0000
67#define FIMD_VIDCON10x0004 0x0004
68#define FIMD_VIDCON20x0008 0x0008
69#define FIMD_VIDCON30x000C 0x000C
70#define FIMD_VIDCON0_ENVID_F(1 << 0) (1 << 0)
71#define FIMD_VIDCON0_ENVID(1 << 1) (1 << 1)
72#define FIMD_VIDCON0_ENVID_MASK((1 << 0) | (1 << 1)) ((1 << 0) | (1 << 1))
73#define FIMD_VIDCON1_ROMASK0x07FFE000 0x07FFE000
74
75/* Video time control registers */
76#define FIMD_VIDTCON_START0x10 0x10
77#define FIMD_VIDTCON_END0x1C 0x1C
78#define FIMD_VIDTCON2_SIZE_MASK0x07FF 0x07FF
79#define FIMD_VIDTCON2_HOR_SHIFT0 0
80#define FIMD_VIDTCON2_VER_SHIFT11 11
81
82/* Window control registers */
83#define FIMD_WINCON_START0x0020 0x0020
84#define FIMD_WINCON_END0x0030 0x0030
85#define FIMD_WINCON_ROMASK0x82200000 0x82200000
86#define FIMD_WINCON_ENWIN(1 << 0) (1 << 0)
87#define FIMD_WINCON_BLD_PIX(1 << 6) (1 << 6)
88#define FIMD_WINCON_ALPHA_MUL(1 << 7) (1 << 7)
89#define FIMD_WINCON_ALPHA_SEL(1 << 1) (1 << 1)
90#define FIMD_WINCON_SWAP0x078000 0x078000
91#define FIMD_WINCON_SWAP_SHIFT15 15
92#define FIMD_WINCON_SWAP_WORD0x1 0x1
93#define FIMD_WINCON_SWAP_HWORD0x2 0x2
94#define FIMD_WINCON_SWAP_BYTE0x4 0x4
95#define FIMD_WINCON_SWAP_BITS0x8 0x8
96#define FIMD_WINCON_BUFSTAT_L(1 << 21) (1 << 21)
97#define FIMD_WINCON_BUFSTAT_H(1 << 31) (1 << 31)
98#define FIMD_WINCON_BUFSTATUS((1 << 21) | (1 << 31)) ((1 << 21) | (1 << 31))
99#define FIMD_WINCON_BUF0_STAT((0 << 21) | (0 << 31)) ((0 << 21) | (0 << 31))
100#define FIMD_WINCON_BUF1_STAT((1 << 21) | (0 << 31)) ((1 << 21) | (0 << 31))
101#define FIMD_WINCON_BUF2_STAT((0 << 21) | (1 << 31)) ((0 << 21) | (1 << 31))
102#define FIMD_WINCON_BUFSELECT((1 << 20) | (1 << 30)) ((1 << 20) | (1 << 30))
103#define FIMD_WINCON_BUF0_SEL((0 << 20) | (0 << 30)) ((0 << 20) | (0 << 30))
104#define FIMD_WINCON_BUF1_SEL((1 << 20) | (0 << 30)) ((1 << 20) | (0 << 30))
105#define FIMD_WINCON_BUF2_SEL((0 << 20) | (1 << 30)) ((0 << 20) | (1 << 30))
106#define FIMD_WINCON_BUFMODE(1 << 14) (1 << 14)
107#define IS_PALETTIZED_MODE(w)(w->wincon & 0xC) (w->wincon & 0xC)
108#define PAL_MODE_WITH_ALPHA(x)((x) == 7) ((x) == 7)
109#define WIN_BPP_MODE(w)((w->wincon >> 2) & 0xF) ((w->wincon >> 2) & 0xF)
110#define WIN_BPP_MODE_WITH_ALPHA(w)(((w->wincon >> 2) & 0xF) == 0xD || ((w->wincon
>> 2) & 0xF) == 0xE)
\
111 (WIN_BPP_MODE(w)((w->wincon >> 2) & 0xF) == 0xD || WIN_BPP_MODE(w)((w->wincon >> 2) & 0xF) == 0xE)
112
113/* Shadow control register */
114#define FIMD_SHADOWCON0x0034 0x0034
115#define FIMD_WINDOW_PROTECTED(s, w)((s) & (1 << (10 + (w)))) ((s) & (1 << (10 + (w))))
116/* Channel mapping control register */
117#define FIMD_WINCHMAP0x003C 0x003C
118
119/* Window position control registers */
120#define FIMD_VIDOSD_START0x0040 0x0040
121#define FIMD_VIDOSD_END0x0088 0x0088
122#define FIMD_VIDOSD_COORD_MASK0x07FF 0x07FF
123#define FIMD_VIDOSD_HOR_SHIFT11 11
124#define FIMD_VIDOSD_VER_SHIFT0 0
125#define FIMD_VIDOSD_ALPHA_AEN00xFFF000 0xFFF000
126#define FIMD_VIDOSD_AEN0_SHIFT12 12
127#define FIMD_VIDOSD_ALPHA_AEN10x000FFF 0x000FFF
128
129/* Frame buffer address registers */
130#define FIMD_VIDWADD0_START0x00A0 0x00A0
131#define FIMD_VIDWADD0_END0x00C4 0x00C4
132#define FIMD_VIDWADD0_END0x00C4 0x00C4
133#define FIMD_VIDWADD1_START0x00D0 0x00D0
134#define FIMD_VIDWADD1_END0x00F4 0x00F4
135#define FIMD_VIDWADD2_START0x0100 0x0100
136#define FIMD_VIDWADD2_END0x0110 0x0110
137#define FIMD_VIDWADD2_PAGEWIDTH0x1FFF 0x1FFF
138#define FIMD_VIDWADD2_OFFSIZE0x1FFF 0x1FFF
139#define FIMD_VIDWADD2_OFFSIZE_SHIFT13 13
140#define FIMD_VIDW0ADD0_B20x20A0 0x20A0
141#define FIMD_VIDW4ADD0_B20x20C0 0x20C0
142
143/* Video interrupt control registers */
144#define FIMD_VIDINTCON00x130 0x130
145#define FIMD_VIDINTCON10x134 0x134
146
147/* Window color key registers */
148#define FIMD_WKEYCON_START0x140 0x140
149#define FIMD_WKEYCON_END0x15C 0x15C
150#define FIMD_WKEYCON0_COMPKEY0x00FFFFFF 0x00FFFFFF
151#define FIMD_WKEYCON0_CTL_SHIFT24 24
152#define FIMD_WKEYCON0_DIRCON(1 << 24) (1 << 24)
153#define FIMD_WKEYCON0_KEYEN(1 << 25) (1 << 25)
154#define FIMD_WKEYCON0_KEYBLEN(1 << 26) (1 << 26)
155/* Window color key alpha control register */
156#define FIMD_WKEYALPHA_START0x160 0x160
157#define FIMD_WKEYALPHA_END0x16C 0x16C
158
159/* Dithering control register */
160#define FIMD_DITHMODE0x170 0x170
161
162/* Window alpha control registers */
163#define FIMD_VIDALPHA_ALPHA_LOWER0x000F0F0F 0x000F0F0F
164#define FIMD_VIDALPHA_ALPHA_UPPER0x00F0F0F0 0x00F0F0F0
165#define FIMD_VIDWALPHA_START0x21C 0x21C
166#define FIMD_VIDWALPHA_END0x240 0x240
167
168/* Window color map registers */
169#define FIMD_WINMAP_START0x180 0x180
170#define FIMD_WINMAP_END0x190 0x190
171#define FIMD_WINMAP_EN(1 << 24) (1 << 24)
172#define FIMD_WINMAP_COLOR_MASK0x00FFFFFF 0x00FFFFFF
173
174/* Window palette control registers */
175#define FIMD_WPALCON_HIGH0x019C 0x019C
176#define FIMD_WPALCON_LOW0x01A0 0x01A0
177#define FIMD_WPALCON_UPDATEEN(1 << 9) (1 << 9)
178#define FIMD_WPAL_W0PAL_L0x07 0x07
179#define FIMD_WPAL_W0PAL_L_SHT0 0
180#define FIMD_WPAL_W1PAL_L0x07 0x07
181#define FIMD_WPAL_W1PAL_L_SHT3 3
182#define FIMD_WPAL_W2PAL_L0x01 0x01
183#define FIMD_WPAL_W2PAL_L_SHT6 6
184#define FIMD_WPAL_W2PAL_H0x06 0x06
185#define FIMD_WPAL_W2PAL_H_SHT8 8
186#define FIMD_WPAL_W3PAL_L0x01 0x01
187#define FIMD_WPAL_W3PAL_L_SHT7 7
188#define FIMD_WPAL_W3PAL_H0x06 0x06
189#define FIMD_WPAL_W3PAL_H_SHT12 12
190#define FIMD_WPAL_W4PAL_L0x01 0x01
191#define FIMD_WPAL_W4PAL_L_SHT8 8
192#define FIMD_WPAL_W4PAL_H0x06 0x06
193#define FIMD_WPAL_W4PAL_H_SHT16 16
194
195/* Trigger control registers */
196#define FIMD_TRIGCON0x01A4 0x01A4
197#define FIMD_TRIGCON_ROMASK0x00000004 0x00000004
198
199/* LCD I80 Interface Control */
200#define FIMD_I80IFCON_START0x01B0 0x01B0
201#define FIMD_I80IFCON_END0x01BC 0x01BC
202/* Color gain control register */
203#define FIMD_COLORGAINCON0x01C0 0x01C0
204/* LCD i80 Interface Command Control */
205#define FIMD_LDI_CMDCON00x01D0 0x01D0
206#define FIMD_LDI_CMDCON10x01D4 0x01D4
207/* I80 System Interface Manual Command Control */
208#define FIMD_SIFCCON00x01E0 0x01E0
209#define FIMD_SIFCCON20x01E8 0x01E8
210
211/* Hue Control Registers */
212#define FIMD_HUECOEFCR_START0x01EC 0x01EC
213#define FIMD_HUECOEFCR_END0x01F4 0x01F4
214#define FIMD_HUECOEFCB_START0x01FC 0x01FC
215#define FIMD_HUECOEFCB_END0x0208 0x0208
216#define FIMD_HUEOFFSET0x020C 0x020C
217
218/* Video interrupt control registers */
219#define FIMD_VIDINT_INTFIFOPEND(1 << 0) (1 << 0)
220#define FIMD_VIDINT_INTFRMPEND(1 << 1) (1 << 1)
221#define FIMD_VIDINT_INTI80PEND(1 << 2) (1 << 2)
222#define FIMD_VIDINT_INTEN(1 << 0) (1 << 0)
223#define FIMD_VIDINT_INTFIFOEN(1 << 1) (1 << 1)
224#define FIMD_VIDINT_INTFRMEN(1 << 12) (1 << 12)
225#define FIMD_VIDINT_I80IFDONE(1 << 17) (1 << 17)
226
227/* Window blend equation control registers */
228#define FIMD_BLENDEQ_START0x0244 0x0244
229#define FIMD_BLENDEQ_END0x0250 0x0250
230#define FIMD_BLENDCON0x0260 0x0260
231#define FIMD_ALPHA_8BIT(1 << 0) (1 << 0)
232#define FIMD_BLENDEQ_COEF_MASK0xF 0xF
233
234/* Window RTQOS Control Registers */
235#define FIMD_WRTQOSCON_START0x0264 0x0264
236#define FIMD_WRTQOSCON_END0x0274 0x0274
237
238/* LCD I80 Interface Command */
239#define FIMD_I80IFCMD_START0x0280 0x0280
240#define FIMD_I80IFCMD_END0x02AC 0x02AC
241
242/* Shadow windows control registers */
243#define FIMD_SHD_ADD0_START0x40A0 0x40A0
244#define FIMD_SHD_ADD0_END0x40C0 0x40C0
245#define FIMD_SHD_ADD1_START0x40D0 0x40D0
246#define FIMD_SHD_ADD1_END0x40F0 0x40F0
247#define FIMD_SHD_ADD2_START0x4100 0x4100
248#define FIMD_SHD_ADD2_END0x4110 0x4110
249
250/* Palette memory */
251#define FIMD_PAL_MEM_START0x2400 0x2400
252#define FIMD_PAL_MEM_END0x37FC 0x37FC
253/* Palette memory aliases for windows 0 and 1 */
254#define FIMD_PALMEM_AL_START0x0400 0x0400
255#define FIMD_PALMEM_AL_END0x0BFC 0x0BFC
256
257typedef struct {
258 uint8_t r, g, b;
259 /* D[31..24]dummy, D[23..16]rAlpha, D[15..8]gAlpha, D[7..0]bAlpha */
260 uint32_t a;
261} rgba;
262#define RGBA_SIZE7 7
263
264typedef void pixel_to_rgb_func(uint32_t pixel, rgba *p);
265typedef struct Exynos4210fimdWindow Exynos4210fimdWindow;
266
267struct Exynos4210fimdWindow {
268 uint32_t wincon; /* Window control register */
269 uint32_t buf_start[3]; /* Start address for video frame buffer */
270 uint32_t buf_end[3]; /* End address for video frame buffer */
271 uint32_t keycon[2]; /* Window color key registers */
272 uint32_t keyalpha; /* Color key alpha control register */
273 uint32_t winmap; /* Window color map register */
274 uint32_t blendeq; /* Window blending equation control register */
275 uint32_t rtqoscon; /* Window RTQOS Control Registers */
276 uint32_t palette[256]; /* Palette RAM */
277 uint32_t shadow_buf_start; /* Start address of shadow frame buffer */
278 uint32_t shadow_buf_end; /* End address of shadow frame buffer */
279 uint32_t shadow_buf_size; /* Virtual shadow screen width */
280
281 pixel_to_rgb_func *pixel_to_rgb;
282 void (*draw_line)(Exynos4210fimdWindow *w, uint8_t *src, uint8_t *dst,
283 bool_Bool blend);
284 uint32_t (*get_alpha)(Exynos4210fimdWindow *w, uint32_t pix_a);
285 uint16_t lefttop_x, lefttop_y; /* VIDOSD0 register */
286 uint16_t rightbot_x, rightbot_y; /* VIDOSD1 register */
287 uint32_t osdsize; /* VIDOSD2&3 register */
288 uint32_t alpha_val[2]; /* VIDOSD2&3, VIDWALPHA registers */
289 uint16_t virtpage_width; /* VIDWADD2 register */
290 uint16_t virtpage_offsize; /* VIDWADD2 register */
291 MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */
292 uint8_t *host_fb_addr; /* Host pointer to window's framebuffer */
293 target_phys_addr_t fb_len; /* Framebuffer length */
294};
295
296typedef struct {
297 SysBusDevice busdev;
298 MemoryRegion iomem;
299 DisplayState *console;
300 qemu_irq irq[3];
301
302 uint32_t vidcon[4]; /* Video main control registers 0-3 */
303 uint32_t vidtcon[4]; /* Video time control registers 0-3 */
304 uint32_t shadowcon; /* Window shadow control register */
305 uint32_t winchmap; /* Channel mapping control register */
306 uint32_t vidintcon[2]; /* Video interrupt control registers */
307 uint32_t dithmode; /* Dithering control register */
308 uint32_t wpalcon[2]; /* Window palette control registers */
309 uint32_t trigcon; /* Trigger control register */
310 uint32_t i80ifcon[4]; /* I80 interface control registers */
311 uint32_t colorgaincon; /* Color gain control register */
312 uint32_t ldi_cmdcon[2]; /* LCD I80 interface command control */
313 uint32_t sifccon[3]; /* I80 System Interface Manual Command Control */
314 uint32_t huecoef_cr[4]; /* Hue control registers */
315 uint32_t huecoef_cb[4]; /* Hue control registers */
316 uint32_t hueoffset; /* Hue offset control register */
317 uint32_t blendcon; /* Blending control register */
318 uint32_t i80ifcmd[12]; /* LCD I80 Interface Command */
319
320 Exynos4210fimdWindow window[5]; /* Window-specific registers */
321 uint8_t *ifb; /* Internal frame buffer */
322 bool_Bool invalidate; /* Image needs to be redrawn */
323 bool_Bool enabled; /* Display controller is enabled */
324} Exynos4210fimdState;
325
326/* Perform byte/halfword/word swap of data according to WINCON */
327static inline void fimd_swap_data(unsigned int swap_ctl, uint64_t *data)
328{
329 int i;
330 uint64_t res;
331 uint64_t x = *data;
332
333 if (swap_ctl & FIMD_WINCON_SWAP_BITS0x8) {
334 res = 0;
335 for (i = 0; i < 64; i++) {
336 if (x & (1ULL << (64 - i))) {
337 res |= (1ULL << i);
338 }
339 }
340 x = res;
341 }
342
343 if (swap_ctl & FIMD_WINCON_SWAP_BYTE0x4) {
344 x = bswap64(x);
345 }
346
347 if (swap_ctl & FIMD_WINCON_SWAP_HWORD0x2) {
348 x = ((x & 0x000000000000FFFFULL) << 48) |
349 ((x & 0x00000000FFFF0000ULL) << 16) |
350 ((x & 0x0000FFFF00000000ULL) >> 16) |
351 ((x & 0xFFFF000000000000ULL) >> 48);
352 }
353
354 if (swap_ctl & FIMD_WINCON_SWAP_WORD0x1) {
355 x = ((x & 0x00000000FFFFFFFFULL) << 32) |
356 ((x & 0xFFFFFFFF00000000ULL) >> 32);
357 }
358
359 *data = x;
360}
361
362/* Conversion routines of Pixel data from frame buffer area to internal RGBA
363 * pixel representation.
364 * Every color component internally represented as 8-bit value. If original
365 * data has less than 8 bit for component, data is extended to 8 bit. For
366 * example, if blue component has only two possible values 0 and 1 it will be
367 * extended to 0 and 0xFF */
368
369/* One bit for alpha representation */
370#define DEF_PIXEL_TO_RGB_A1(N, R, G, B)static void N(uint32_t pixel, rgba *p) { p->b = ((pixel &
((1 << (B)) - 1)) << (8 - (B))) | ((pixel >>
(2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); pixel >>=
(B); p->g = (pixel & ((1 << (G)) - 1)) <<
(8 - (G)) | ((pixel >> (2 * (G) - 8)) & ((1 <<
(8 - (G))) - 1)); pixel >>= (G); p->r = (pixel &
((1 << (R)) - 1)) << (8 - (R)) | ((pixel >>
(2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); pixel >>=
(R); p->a = (pixel & 0x1); }
\
371static void N(uint32_t pixel, rgba *p) \
372{ \
373 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
374 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
375 pixel >>= (B); \
376 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
377 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
378 pixel >>= (G); \
379 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
380 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
381 pixel >>= (R); \
382 p->a = (pixel & 0x1); \
383}
384
385DEF_PIXEL_TO_RGB_A1(pixel_a444_to_rgb, 4, 4, 4)static void pixel_a444_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (4)) - 1)) << (8 - (4)))
| ((pixel >> (2 * (4) - 8)) & ((1 << (8 - (4
))) - 1)); pixel >>= (4); p->g = (pixel & ((1 <<
(4)) - 1)) << (8 - (4)) | ((pixel >> (2 * (4) - 8
)) & ((1 << (8 - (4))) - 1)); pixel >>= (4); p
->r = (pixel & ((1 << (4)) - 1)) << (8 - (
4)) | ((pixel >> (2 * (4) - 8)) & ((1 << (8 -
(4))) - 1)); pixel >>= (4); p->a = (pixel & 0x1
); }
386DEF_PIXEL_TO_RGB_A1(pixel_a555_to_rgb, 5, 5, 5)static void pixel_a555_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (5)) - 1)) << (8 - (5)))
| ((pixel >> (2 * (5) - 8)) & ((1 << (8 - (5
))) - 1)); pixel >>= (5); p->g = (pixel & ((1 <<
(5)) - 1)) << (8 - (5)) | ((pixel >> (2 * (5) - 8
)) & ((1 << (8 - (5))) - 1)); pixel >>= (5); p
->r = (pixel & ((1 << (5)) - 1)) << (8 - (
5)) | ((pixel >> (2 * (5) - 8)) & ((1 << (8 -
(5))) - 1)); pixel >>= (5); p->a = (pixel & 0x1
); }
387DEF_PIXEL_TO_RGB_A1(pixel_a666_to_rgb, 6, 6, 6)static void pixel_a666_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (6)) - 1)) << (8 - (6)))
| ((pixel >> (2 * (6) - 8)) & ((1 << (8 - (6
))) - 1)); pixel >>= (6); p->g = (pixel & ((1 <<
(6)) - 1)) << (8 - (6)) | ((pixel >> (2 * (6) - 8
)) & ((1 << (8 - (6))) - 1)); pixel >>= (6); p
->r = (pixel & ((1 << (6)) - 1)) << (8 - (
6)) | ((pixel >> (2 * (6) - 8)) & ((1 << (8 -
(6))) - 1)); pixel >>= (6); p->a = (pixel & 0x1
); }
388DEF_PIXEL_TO_RGB_A1(pixel_a665_to_rgb, 6, 6, 5)static void pixel_a665_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (5)) - 1)) << (8 - (5)))
| ((pixel >> (2 * (5) - 8)) & ((1 << (8 - (5
))) - 1)); pixel >>= (5); p->g = (pixel & ((1 <<
(6)) - 1)) << (8 - (6)) | ((pixel >> (2 * (6) - 8
)) & ((1 << (8 - (6))) - 1)); pixel >>= (6); p
->r = (pixel & ((1 << (6)) - 1)) << (8 - (
6)) | ((pixel >> (2 * (6) - 8)) & ((1 << (8 -
(6))) - 1)); pixel >>= (6); p->a = (pixel & 0x1
); }
389DEF_PIXEL_TO_RGB_A1(pixel_a888_to_rgb, 8, 8, 8)static void pixel_a888_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (8)) - 1)) << (8 - (8)))
| ((pixel >> (2 * (8) - 8)) & ((1 << (8 - (8
))) - 1)); pixel >>= (8); p->g = (pixel & ((1 <<
(8)) - 1)) << (8 - (8)) | ((pixel >> (2 * (8) - 8
)) & ((1 << (8 - (8))) - 1)); pixel >>= (8); p
->r = (pixel & ((1 << (8)) - 1)) << (8 - (
8)) | ((pixel >> (2 * (8) - 8)) & ((1 << (8 -
(8))) - 1)); pixel >>= (8); p->a = (pixel & 0x1
); }
390DEF_PIXEL_TO_RGB_A1(pixel_a887_to_rgb, 8, 8, 7)static void pixel_a887_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (7)) - 1)) << (8 - (7)))
| ((pixel >> (2 * (7) - 8)) & ((1 << (8 - (7
))) - 1)); pixel >>= (7); p->g = (pixel & ((1 <<
(8)) - 1)) << (8 - (8)) | ((pixel >> (2 * (8) - 8
)) & ((1 << (8 - (8))) - 1)); pixel >>= (8); p
->r = (pixel & ((1 << (8)) - 1)) << (8 - (
8)) | ((pixel >> (2 * (8) - 8)) & ((1 << (8 -
(8))) - 1)); pixel >>= (8); p->a = (pixel & 0x1
); }
391
392/* Alpha component is always zero */
393#define DEF_PIXEL_TO_RGB_A0(N, R, G, B)static void N(uint32_t pixel, rgba *p) { p->b = ((pixel &
((1 << (B)) - 1)) << (8 - (B))) | ((pixel >>
(2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); pixel >>=
(B); p->g = (pixel & ((1 << (G)) - 1)) <<
(8 - (G)) | ((pixel >> (2 * (G) - 8)) & ((1 <<
(8 - (G))) - 1)); pixel >>= (G); p->r = (pixel &
((1 << (R)) - 1)) << (8 - (R)) | ((pixel >>
(2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); p->a =
0x0; }
\
394static void N(uint32_t pixel, rgba *p) \
395{ \
396 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
397 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
398 pixel >>= (B); \
399 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
400 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
401 pixel >>= (G); \
402 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
403 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
404 p->a = 0x0; \
405}
406
407DEF_PIXEL_TO_RGB_A0(pixel_565_to_rgb, 5, 6, 5)static void pixel_565_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (5)) - 1)) << (8 - (5)))
| ((pixel >> (2 * (5) - 8)) & ((1 << (8 - (5
))) - 1)); pixel >>= (5); p->g = (pixel & ((1 <<
(6)) - 1)) << (8 - (6)) | ((pixel >> (2 * (6) - 8
)) & ((1 << (8 - (6))) - 1)); pixel >>= (6); p
->r = (pixel & ((1 << (5)) - 1)) << (8 - (
5)) | ((pixel >> (2 * (5) - 8)) & ((1 << (8 -
(5))) - 1)); p->a = 0x0; }
408DEF_PIXEL_TO_RGB_A0(pixel_555_to_rgb, 5, 5, 5)static void pixel_555_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (5)) - 1)) << (8 - (5)))
| ((pixel >> (2 * (5) - 8)) & ((1 << (8 - (5
))) - 1)); pixel >>= (5); p->g = (pixel & ((1 <<
(5)) - 1)) << (8 - (5)) | ((pixel >> (2 * (5) - 8
)) & ((1 << (8 - (5))) - 1)); pixel >>= (5); p
->r = (pixel & ((1 << (5)) - 1)) << (8 - (
5)) | ((pixel >> (2 * (5) - 8)) & ((1 << (8 -
(5))) - 1)); p->a = 0x0; }
409DEF_PIXEL_TO_RGB_A0(pixel_666_to_rgb, 6, 6, 6)static void pixel_666_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (6)) - 1)) << (8 - (6)))
| ((pixel >> (2 * (6) - 8)) & ((1 << (8 - (6
))) - 1)); pixel >>= (6); p->g = (pixel & ((1 <<
(6)) - 1)) << (8 - (6)) | ((pixel >> (2 * (6) - 8
)) & ((1 << (8 - (6))) - 1)); pixel >>= (6); p
->r = (pixel & ((1 << (6)) - 1)) << (8 - (
6)) | ((pixel >> (2 * (6) - 8)) & ((1 << (8 -
(6))) - 1)); p->a = 0x0; }
410DEF_PIXEL_TO_RGB_A0(pixel_888_to_rgb, 8, 8, 8)static void pixel_888_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (8)) - 1)) << (8 - (8)))
| ((pixel >> (2 * (8) - 8)) & ((1 << (8 - (8
))) - 1)); pixel >>= (8); p->g = (pixel & ((1 <<
(8)) - 1)) << (8 - (8)) | ((pixel >> (2 * (8) - 8
)) & ((1 << (8 - (8))) - 1)); pixel >>= (8); p
->r = (pixel & ((1 << (8)) - 1)) << (8 - (
8)) | ((pixel >> (2 * (8) - 8)) & ((1 << (8 -
(8))) - 1)); p->a = 0x0; }
411
412/* Alpha component has some meaningful value */
413#define DEF_PIXEL_TO_RGB_A(N, R, G, B, A)static void N(uint32_t pixel, rgba *p) { p->b = ((pixel &
((1 << (B)) - 1)) << (8 - (B))) | ((pixel >>
(2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); pixel >>=
(B); p->g = (pixel & ((1 << (G)) - 1)) <<
(8 - (G)) | ((pixel >> (2 * (G) - 8)) & ((1 <<
(8 - (G))) - 1)); pixel >>= (G); p->r = (pixel &
((1 << (R)) - 1)) << (8 - (R)) | ((pixel >>
(2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); pixel >>=
(R); p->a = (pixel & ((1 << (A)) - 1)) <<
(8 - (A)) | ((pixel >> (2 * (A) - 8)) & ((1 <<
(8 - (A))) - 1)); p->a = p->a | (p->a << 8) |
(p->a << 16); }
\
414static void N(uint32_t pixel, rgba *p) \
415{ \
416 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
417 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
418 pixel >>= (B); \
419 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
420 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
421 pixel >>= (G); \
422 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
423 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
424 pixel >>= (R); \
425 p->a = (pixel & ((1 << (A)) - 1)) << (8 - (A)) | \
426 ((pixel >> (2 * (A) - 8)) & ((1 << (8 - (A))) - 1)); \
427 p->a = p->a | (p->a << 8) | (p->a << 16); \
428}
429
430DEF_PIXEL_TO_RGB_A(pixel_4444_to_rgb, 4, 4, 4, 4)static void pixel_4444_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (4)) - 1)) << (8 - (4)))
| ((pixel >> (2 * (4) - 8)) & ((1 << (8 - (4
))) - 1)); pixel >>= (4); p->g = (pixel & ((1 <<
(4)) - 1)) << (8 - (4)) | ((pixel >> (2 * (4) - 8
)) & ((1 << (8 - (4))) - 1)); pixel >>= (4); p
->r = (pixel & ((1 << (4)) - 1)) << (8 - (
4)) | ((pixel >> (2 * (4) - 8)) & ((1 << (8 -
(4))) - 1)); pixel >>= (4); p->a = (pixel & ((1
<< (4)) - 1)) << (8 - (4)) | ((pixel >> (2
* (4) - 8)) & ((1 << (8 - (4))) - 1)); p->a = p
->a | (p->a << 8) | (p->a << 16); }
431DEF_PIXEL_TO_RGB_A(pixel_8888_to_rgb, 8, 8, 8, 8)static void pixel_8888_to_rgb(uint32_t pixel, rgba *p) { p->
b = ((pixel & ((1 << (8)) - 1)) << (8 - (8)))
| ((pixel >> (2 * (8) - 8)) & ((1 << (8 - (8
))) - 1)); pixel >>= (8); p->g = (pixel & ((1 <<
(8)) - 1)) << (8 - (8)) | ((pixel >> (2 * (8) - 8
)) & ((1 << (8 - (8))) - 1)); pixel >>= (8); p
->r = (pixel & ((1 << (8)) - 1)) << (8 - (
8)) | ((pixel >> (2 * (8) - 8)) & ((1 << (8 -
(8))) - 1)); pixel >>= (8); p->a = (pixel & ((1
<< (8)) - 1)) << (8 - (8)) | ((pixel >> (2
* (8) - 8)) & ((1 << (8 - (8))) - 1)); p->a = p
->a | (p->a << 8) | (p->a << 16); }
432
433/* Lookup table to extent 2-bit color component to 8 bit */
434static const uint8_t pixel_lutable_2b[4] = {
435 0x0, 0x55, 0xAA, 0xFF
436};
437/* Lookup table to extent 3-bit color component to 8 bit */
438static const uint8_t pixel_lutable_3b[8] = {
439 0x0, 0x24, 0x49, 0x6D, 0x92, 0xB6, 0xDB, 0xFF
440};
441/* Special case for a232 bpp mode */
442static void pixel_a232_to_rgb(uint32_t pixel, rgba *p)
443{
444 p->b = pixel_lutable_2b[(pixel & 0x3)];
445 pixel >>= 2;
446 p->g = pixel_lutable_3b[(pixel & 0x7)];
447 pixel >>= 3;
448 p->r = pixel_lutable_2b[(pixel & 0x3)];
449 pixel >>= 2;
450 p->a = (pixel & 0x1);
451}
452
453/* Special case for (5+1, 5+1, 5+1) mode. Data bit 15 is common LSB
454 * for all three color components */
455static void pixel_1555_to_rgb(uint32_t pixel, rgba *p)
456{
457 uint8_t comm = (pixel >> 15) & 1;
458 p->b = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
459 pixel >>= 5;
460 p->g = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
461 pixel >>= 5;
462 p->r = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
463 p->a = 0x0;
464}
465
466/* Put/get pixel to/from internal LCD Controller framebuffer */
467
468static int put_pixel_ifb(const rgba p, uint8_t *d)
469{
470 *(uint8_t *)d++ = p.r;
471 *(uint8_t *)d++ = p.g;
472 *(uint8_t *)d++ = p.b;
473 *(uint32_t *)d = p.a;
474 return RGBA_SIZE7;
475}
476
477static int get_pixel_ifb(const uint8_t *s, rgba *p)
478{
479 p->r = *(uint8_t *)s++;
480 p->g = *(uint8_t *)s++;
481 p->b = *(uint8_t *)s++;
482 p->a = (*(uint32_t *)s) & 0x00FFFFFF;
483 return RGBA_SIZE7;
484}
485
486static pixel_to_rgb_func *palette_data_format[8] = {
487 [0] = pixel_565_to_rgb,
488 [1] = pixel_a555_to_rgb,
489 [2] = pixel_666_to_rgb,
490 [3] = pixel_a665_to_rgb,
491 [4] = pixel_a666_to_rgb,
492 [5] = pixel_888_to_rgb,
493 [6] = pixel_a888_to_rgb,
494 [7] = pixel_8888_to_rgb
495};
496
497/* Returns Index in palette data formats table for given window number WINDOW */
498static uint32_t
499exynos4210_fimd_palette_format(Exynos4210fimdState *s, int window)
500{
501 uint32_t ret;
502
503 switch (window) {
504 case 0:
505 ret = (s->wpalcon[1] >> FIMD_WPAL_W0PAL_L_SHT0) & FIMD_WPAL_W0PAL_L0x07;
506 if (ret != 7) {
507 ret = 6 - ret;
508 }
509 break;
510 case 1:
511 ret = (s->wpalcon[1] >> FIMD_WPAL_W1PAL_L_SHT3) & FIMD_WPAL_W1PAL_L0x07;
512 if (ret != 7) {
513 ret = 6 - ret;
514 }
515 break;
516 case 2:
517 ret = ((s->wpalcon[0] >> FIMD_WPAL_W2PAL_H_SHT8) & FIMD_WPAL_W2PAL_H0x06) |
518 ((s->wpalcon[1] >> FIMD_WPAL_W2PAL_L_SHT6) & FIMD_WPAL_W2PAL_L0x01);
519 break;
520 case 3:
521 ret = ((s->wpalcon[0] >> FIMD_WPAL_W3PAL_H_SHT12) & FIMD_WPAL_W3PAL_H0x06) |
522 ((s->wpalcon[1] >> FIMD_WPAL_W3PAL_L_SHT7) & FIMD_WPAL_W3PAL_L0x01);
523 break;
524 case 4:
525 ret = ((s->wpalcon[0] >> FIMD_WPAL_W4PAL_H_SHT16) & FIMD_WPAL_W4PAL_H0x06) |
526 ((s->wpalcon[1] >> FIMD_WPAL_W4PAL_L_SHT8) & FIMD_WPAL_W4PAL_L0x01);
527 break;
528 default:
529 hw_error("exynos4210.fimd: incorrect window number %d\n", window);
530 ret = 0;
531 break;
532 }
533 return ret;
534}
535
536#define FIMD_1_MINUS_COLOR(x)((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | (
0xFF0000 - ((x) & 0xFF0000)))
\
537 ((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | \
538 (0xFF0000 - ((x) & 0xFF0000)))
539#define EXTEND_LOWER_HALFBYTE(x)(((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0)) (((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0))
540#define EXTEND_UPPER_HALFBYTE(x)(((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F)) (((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F))
541
542/* Multiply three lower bytes of two 32-bit words with each other.
543 * Each byte with values 0-255 is considered as a number with possible values
544 * in a range [0 - 1] */
545static inline uint32_t fimd_mult_each_byte(uint32_t a, uint32_t b)
546{
547 uint32_t tmp;
548 uint32_t ret;
549
550 ret = ((tmp = (((a & 0xFF) * (b & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF : tmp;
551 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF)) / 0xFF)) > 0xFF) ?
552 0xFF00 : tmp << 8;
553 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
554 0xFF0000 : tmp << 16;
555 return ret;
556}
557
558/* For each corresponding bytes of two 32-bit words: (a*b + c*d)
559 * Byte values 0-255 are mapped to a range [0 .. 1] */
560static inline uint32_t
561fimd_mult_and_sum_each_byte(uint32_t a, uint32_t b, uint32_t c, uint32_t d)
562{
563 uint32_t tmp;
564 uint32_t ret;
565
566 ret = ((tmp = (((a & 0xFF) * (b & 0xFF) + (c & 0xFF) * (d & 0xFF)) / 0xFF))
567 > 0xFF) ? 0xFF : tmp;
568 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF) + ((c >> 8) & 0xFF) *
569 ((d >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF00 : tmp << 8;
570 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF) +
571 ((c >> 16) & 0xFF) * ((d >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
572 0xFF0000 : tmp << 16;
573 return ret;
574}
575
576/* These routines cover all possible sources of window's transparent factor
577 * used in blending equation. Choice of routine is affected by WPALCON
578 * registers, BLENDCON register and window's WINCON register */
579
580static uint32_t fimd_get_alpha_pix(Exynos4210fimdWindow *w, uint32_t pix_a)
581{
582 return pix_a;
583}
584
585static uint32_t
586fimd_get_alpha_pix_extlow(Exynos4210fimdWindow *w, uint32_t pix_a)
587{
588 return EXTEND_LOWER_HALFBYTE(pix_a)(((pix_a) & 0xF0F0F) | (((pix_a) << 4) & 0xF0F0F0
))
;
589}
590
591static uint32_t
592fimd_get_alpha_pix_exthigh(Exynos4210fimdWindow *w, uint32_t pix_a)
593{
594 return EXTEND_UPPER_HALFBYTE(pix_a)(((pix_a) & 0xF0F0F0) | (((pix_a) >> 4) & 0xF0F0F
))
;
595}
596
597static uint32_t fimd_get_alpha_mult(Exynos4210fimdWindow *w, uint32_t pix_a)
598{
599 return fimd_mult_each_byte(pix_a, w->alpha_val[0]);
600}
601
602static uint32_t fimd_get_alpha_mult_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
603{
604 return fimd_mult_each_byte(EXTEND_LOWER_HALFBYTE(pix_a)(((pix_a) & 0xF0F0F) | (((pix_a) << 4) & 0xF0F0F0
))
,
605 EXTEND_UPPER_HALFBYTE(w->alpha_val[0])(((w->alpha_val[0]) & 0xF0F0F0) | (((w->alpha_val[0
]) >> 4) & 0xF0F0F))
);
606}
607
608static uint32_t fimd_get_alpha_aen(Exynos4210fimdWindow *w, uint32_t pix_a)
609{
610 return w->alpha_val[pix_a];
611}
612
613static uint32_t fimd_get_alpha_aen_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
614{
615 return EXTEND_UPPER_HALFBYTE(w->alpha_val[pix_a])(((w->alpha_val[pix_a]) & 0xF0F0F0) | (((w->alpha_val
[pix_a]) >> 4) & 0xF0F0F))
;
616}
617
618static uint32_t fimd_get_alpha_sel(Exynos4210fimdWindow *w, uint32_t pix_a)
619{
620 return w->alpha_val[(w->wincon & FIMD_WINCON_ALPHA_SEL(1 << 1)) ? 1 : 0];
621}
622
623static uint32_t fimd_get_alpha_sel_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
624{
625 return EXTEND_UPPER_HALFBYTE(w->alpha_val[(w->wincon &(((w->alpha_val[(w->wincon & (1 << 1)) ? 1 : 0
]) & 0xF0F0F0) | (((w->alpha_val[(w->wincon & (
1 << 1)) ? 1 : 0]) >> 4) & 0xF0F0F))
626 FIMD_WINCON_ALPHA_SEL) ? 1 : 0])(((w->alpha_val[(w->wincon & (1 << 1)) ? 1 : 0
]) & 0xF0F0F0) | (((w->alpha_val[(w->wincon & (
1 << 1)) ? 1 : 0]) >> 4) & 0xF0F0F))
;
627}
628
629/* Updates currently active alpha value get function for specified window */
630static void fimd_update_get_alpha(Exynos4210fimdState *s, int win)
631{
632 Exynos4210fimdWindow *w = &s->window[win];
633 const bool_Bool alpha_is_8bit = s->blendcon & FIMD_ALPHA_8BIT(1 << 0);
634
635 if (w->wincon & FIMD_WINCON_BLD_PIX(1 << 6)) {
636 if ((w->wincon & FIMD_WINCON_ALPHA_SEL(1 << 1)) && WIN_BPP_MODE_WITH_ALPHA(w)(((w->wincon >> 2) & 0xF) == 0xD || ((w->wincon
>> 2) & 0xF) == 0xE)
) {
637 /* In this case, alpha component contains meaningful value */
638 if (w->wincon & FIMD_WINCON_ALPHA_MUL(1 << 7)) {
639 w->get_alpha = alpha_is_8bit ?
640 fimd_get_alpha_mult : fimd_get_alpha_mult_ext;
641 } else {
642 w->get_alpha = alpha_is_8bit ?
643 fimd_get_alpha_pix : fimd_get_alpha_pix_extlow;
644 }
645 } else {
646 if (IS_PALETTIZED_MODE(w)(w->wincon & 0xC) &&
647 PAL_MODE_WITH_ALPHA(exynos4210_fimd_palette_format(s, win))((exynos4210_fimd_palette_format(s, win)) == 7)) {
648 /* Alpha component has 8-bit numeric value */
649 w->get_alpha = alpha_is_8bit ?
650 fimd_get_alpha_pix : fimd_get_alpha_pix_exthigh;
651 } else {
652 /* Alpha has only two possible values (AEN) */
653 w->get_alpha = alpha_is_8bit ?
654 fimd_get_alpha_aen : fimd_get_alpha_aen_ext;
655 }
656 }
657 } else {
658 w->get_alpha = alpha_is_8bit ? fimd_get_alpha_sel :
659 fimd_get_alpha_sel_ext;
660 }
661}
662
663/* Blends current window's (w) pixel (foreground pixel *ret) with background
664 * window (w_blend) pixel p_bg according to formula:
665 * NEW_COLOR = a_coef x FG_PIXEL_COLOR + b_coef x BG_PIXEL_COLOR
666 * NEW_ALPHA = p_coef x FG_ALPHA + q_coef x BG_ALPHA
667 */
668static void
669exynos4210_fimd_blend_pixel(Exynos4210fimdWindow *w, rgba p_bg, rgba *ret)
670{
671 rgba p_fg = *ret;
672 uint32_t bg_color = ((p_bg.r & 0xFF) << 16) | ((p_bg.g & 0xFF) << 8) |
673 (p_bg.b & 0xFF);
674 uint32_t fg_color = ((p_fg.r & 0xFF) << 16) | ((p_fg.g & 0xFF) << 8) |
675 (p_fg.b & 0xFF);
676 uint32_t alpha_fg = p_fg.a;
677 int i;
678 /* It is possible that blending equation parameters a and b do not
679 * depend on window BLENEQ register. Account for this with first_coef */
680 enum { A_COEF = 0, B_COEF = 1, P_COEF = 2, Q_COEF = 3, COEF_NUM = 4};
681 uint32_t first_coef = A_COEF;
682 uint32_t blend_param[COEF_NUM];
683
684 if (w->keycon[0] & FIMD_WKEYCON0_KEYEN(1 << 25)) {
685 uint32_t colorkey = (w->keycon[1] &
686 ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY0x00FFFFFF)) & FIMD_WKEYCON0_COMPKEY0x00FFFFFF;
687
688 if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON(1 << 24)) &&
689 (bg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY0x00FFFFFF)) == colorkey) {
690 /* Foreground pixel is displayed */
691 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN(1 << 26)) {
692 alpha_fg = w->keyalpha;
693 blend_param[A_COEF] = alpha_fg;
694 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg)((0xFF - ((alpha_fg) & 0xFF)) | (0xFF00 - ((alpha_fg) &
0xFF00)) | (0xFF0000 - ((alpha_fg) & 0xFF0000)))
;
695 } else {
696 alpha_fg = 0;
697 blend_param[A_COEF] = 0xFFFFFF;
698 blend_param[B_COEF] = 0x0;
699 }
700 first_coef = P_COEF;
701 } else if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON(1 << 24)) == 0 &&
702 (fg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY0x00FFFFFF)) == colorkey) {
703 /* Background pixel is displayed */
704 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN(1 << 26)) {
705 alpha_fg = w->keyalpha;
706 blend_param[A_COEF] = alpha_fg;
707 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg)((0xFF - ((alpha_fg) & 0xFF)) | (0xFF00 - ((alpha_fg) &
0xFF00)) | (0xFF0000 - ((alpha_fg) & 0xFF0000)))
;
708 } else {
709 alpha_fg = 0;
710 blend_param[A_COEF] = 0x0;
711 blend_param[B_COEF] = 0xFFFFFF;
712 }
713 first_coef = P_COEF;
714 }
715 }
716
717 for (i = first_coef; i < COEF_NUM; i++) {
718 switch ((w->blendeq >> i * 6) & FIMD_BLENDEQ_COEF_MASK0xF) {
719 case 0:
720 blend_param[i] = 0;
721 break;
722 case 1:
723 blend_param[i] = 0xFFFFFF;
724 break;
725 case 2:
726 blend_param[i] = alpha_fg;
727 break;
728 case 3:
729 blend_param[i] = FIMD_1_MINUS_COLOR(alpha_fg)((0xFF - ((alpha_fg) & 0xFF)) | (0xFF00 - ((alpha_fg) &
0xFF00)) | (0xFF0000 - ((alpha_fg) & 0xFF0000)))
;
730 break;
731 case 4:
732 blend_param[i] = p_bg.a;
733 break;
734 case 5:
735 blend_param[i] = FIMD_1_MINUS_COLOR(p_bg.a)((0xFF - ((p_bg.a) & 0xFF)) | (0xFF00 - ((p_bg.a) & 0xFF00
)) | (0xFF0000 - ((p_bg.a) & 0xFF0000)))
;
736 break;
737 case 6:
738 blend_param[i] = w->alpha_val[0];
739 break;
740 case 10:
741 blend_param[i] = fg_color;
742 break;
743 case 11:
744 blend_param[i] = FIMD_1_MINUS_COLOR(fg_color)((0xFF - ((fg_color) & 0xFF)) | (0xFF00 - ((fg_color) &
0xFF00)) | (0xFF0000 - ((fg_color) & 0xFF0000)))
;
745 break;
746 case 12:
747 blend_param[i] = bg_color;
748 break;
749 case 13:
750 blend_param[i] = FIMD_1_MINUS_COLOR(bg_color)((0xFF - ((bg_color) & 0xFF)) | (0xFF00 - ((bg_color) &
0xFF00)) | (0xFF0000 - ((bg_color) & 0xFF0000)))
;
751 break;
752 default:
753 hw_error("exynos4210.fimd: blend equation coef illegal value\n");
754 break;
755 }
756 }
757
758 fg_color = fimd_mult_and_sum_each_byte(bg_color, blend_param[B_COEF],
759 fg_color, blend_param[A_COEF]);
760 ret->b = fg_color & 0xFF;
761 fg_color >>= 8;
762 ret->g = fg_color & 0xFF;
763 fg_color >>= 8;
764 ret->r = fg_color & 0xFF;
765 ret->a = fimd_mult_and_sum_each_byte(alpha_fg, blend_param[P_COEF],
766 p_bg.a, blend_param[Q_COEF]);
767}
768
769/* These routines read data from video frame buffer in system RAM, convert
770 * this data to display controller internal representation, if necessary,
771 * perform pixel blending with data, currently presented in internal buffer.
772 * Result is stored in display controller internal frame buffer. */
773
774/* Draw line with index in palette table in RAM frame buffer data */
775#define DEF_DRAW_LINE_PALETTE(N)static void draw_line_palette_N(Exynos4210fimdWindow *w, uint8_t
*src, uint8_t *dst, _Bool blend) { int width = w->rightbot_x
- w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w
->wincon & 0x078000) >> 15; uint64_t data; rgba p
, p_old; int i; do { data = ldq_le_p((uint8_t *)(intptr_t)(((
void *)src))); src += 8; fimd_swap_data(swap, &data); for
(i = (64 / (N) - 1); i >= 0; i--) { w->pixel_to_rgb(w->
palette[(data >> ((N) * i)) & ((1ULL << (N)) -
1)], &p); p.a = w->get_alpha(w, p.a); if (blend) { ifb
+= get_pixel_ifb(ifb, &p_old); exynos4210_fimd_blend_pixel
(w, p_old, &p); } dst += put_pixel_ifb(p, dst); } width -=
(64 / (N)); } while (width > 0); }
\
776static void glue(draw_line_palette_, N)draw_line_palette_N(Exynos4210fimdWindow *w, uint8_t *src, \
777 uint8_t *dst, bool_Bool blend) \
778{ \
779 int width = w->rightbot_x - w->lefttop_x + 1; \
780 uint8_t *ifb = dst; \
781 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP0x078000) >> FIMD_WINCON_SWAP_SHIFT15; \
782 uint64_t data; \
783 rgba p, p_old; \
784 int i; \
785 do { \
786 data = ldq_raw((void *)src)ldq_le_p((uint8_t *)(intptr_t)(((void *)src))); \
787 src += 8; \
788 fimd_swap_data(swap, &data); \
789 for (i = (64 / (N) - 1); i >= 0; i--) { \
790 w->pixel_to_rgb(w->palette[(data >> ((N) * i)) & \
791 ((1ULL << (N)) - 1)], &p); \
792 p.a = w->get_alpha(w, p.a); \
793 if (blend) { \
794 ifb += get_pixel_ifb(ifb, &p_old); \
795 exynos4210_fimd_blend_pixel(w, p_old, &p); \
796 } \
797 dst += put_pixel_ifb(p, dst); \
798 } \
799 width -= (64 / (N)); \
800 } while (width > 0); \
801}
802
803/* Draw line with direct color value in RAM frame buffer data */
804#define DEF_DRAW_LINE_NOPALETTE(N)static void draw_line_N(Exynos4210fimdWindow *w, uint8_t *src
, uint8_t *dst, _Bool blend) { int width = w->rightbot_x -
w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w->
wincon & 0x078000) >> 15; uint64_t data; rgba p, p_old
; int i; do { data = ldq_le_p((uint8_t *)(intptr_t)(((void *)
src))); src += 8; fimd_swap_data(swap, &data); for (i = (
64 / (N) - 1); i >= 0; i--) { w->pixel_to_rgb((data >>
((N) * i)) & ((1ULL << (N)) - 1), &p); p.a = w
->get_alpha(w, p.a); if (blend) { ifb += get_pixel_ifb(ifb
, &p_old); exynos4210_fimd_blend_pixel(w, p_old, &p);
} dst += put_pixel_ifb(p, dst); } width -= (64 / (N)); } while
(width > 0); }
\
805static void glue(draw_line_, N)draw_line_N(Exynos4210fimdWindow *w, uint8_t *src, \
806 uint8_t *dst, bool_Bool blend) \
807{ \
808 int width = w->rightbot_x - w->lefttop_x + 1; \
809 uint8_t *ifb = dst; \
810 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP0x078000) >> FIMD_WINCON_SWAP_SHIFT15; \
811 uint64_t data; \
812 rgba p, p_old; \
813 int i; \
814 do { \
815 data = ldq_raw((void *)src)ldq_le_p((uint8_t *)(intptr_t)(((void *)src))); \
816 src += 8; \
817 fimd_swap_data(swap, &data); \
818 for (i = (64 / (N) - 1); i >= 0; i--) { \
819 w->pixel_to_rgb((data >> ((N) * i)) & ((1ULL << (N)) - 1), &p); \
820 p.a = w->get_alpha(w, p.a); \
821 if (blend) { \
822 ifb += get_pixel_ifb(ifb, &p_old); \
823 exynos4210_fimd_blend_pixel(w, p_old, &p); \
824 } \
825 dst += put_pixel_ifb(p, dst); \
826 } \
827 width -= (64 / (N)); \
828 } while (width > 0); \
829}
830
831DEF_DRAW_LINE_PALETTE(1)static void draw_line_palette_1(Exynos4210fimdWindow *w, uint8_t
*src, uint8_t *dst, _Bool blend) { int width = w->rightbot_x
- w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w
->wincon & 0x078000) >> 15; uint64_t data; rgba p
, p_old; int i; do { data = ldq_le_p((uint8_t *)(intptr_t)(((
void *)src))); src += 8; fimd_swap_data(swap, &data); for
(i = (64 / (1) - 1); i >= 0; i--) { w->pixel_to_rgb(w->
palette[(data >> ((1) * i)) & ((1ULL << (1)) -
1)], &p); p.a = w->get_alpha(w, p.a); if (blend) { ifb
+= get_pixel_ifb(ifb, &p_old); exynos4210_fimd_blend_pixel
(w, p_old, &p); } dst += put_pixel_ifb(p, dst); } width -=
(64 / (1)); } while (width > 0); }
832DEF_DRAW_LINE_PALETTE(2)static void draw_line_palette_2(Exynos4210fimdWindow *w, uint8_t
*src, uint8_t *dst, _Bool blend) { int width = w->rightbot_x
- w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w
->wincon & 0x078000) >> 15; uint64_t data; rgba p
, p_old; int i; do { data = ldq_le_p((uint8_t *)(intptr_t)(((
void *)src))); src += 8; fimd_swap_data(swap, &data); for
(i = (64 / (2) - 1); i >= 0; i--) { w->pixel_to_rgb(w->
palette[(data >> ((2) * i)) & ((1ULL << (2)) -
1)], &p); p.a = w->get_alpha(w, p.a); if (blend) { ifb
+= get_pixel_ifb(ifb, &p_old); exynos4210_fimd_blend_pixel
(w, p_old, &p); } dst += put_pixel_ifb(p, dst); } width -=
(64 / (2)); } while (width > 0); }
833DEF_DRAW_LINE_PALETTE(4)static void draw_line_palette_4(Exynos4210fimdWindow *w, uint8_t
*src, uint8_t *dst, _Bool blend) { int width = w->rightbot_x
- w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w
->wincon & 0x078000) >> 15; uint64_t data; rgba p
, p_old; int i; do { data = ldq_le_p((uint8_t *)(intptr_t)(((
void *)src))); src += 8; fimd_swap_data(swap, &data); for
(i = (64 / (4) - 1); i >= 0; i--) { w->pixel_to_rgb(w->
palette[(data >> ((4) * i)) & ((1ULL << (4)) -
1)], &p); p.a = w->get_alpha(w, p.a); if (blend) { ifb
+= get_pixel_ifb(ifb, &p_old); exynos4210_fimd_blend_pixel
(w, p_old, &p); } dst += put_pixel_ifb(p, dst); } width -=
(64 / (4)); } while (width > 0); }
834DEF_DRAW_LINE_PALETTE(8)static void draw_line_palette_8(Exynos4210fimdWindow *w, uint8_t
*src, uint8_t *dst, _Bool blend) { int width = w->rightbot_x
- w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w
->wincon & 0x078000) >> 15; uint64_t data; rgba p
, p_old; int i; do { data = ldq_le_p((uint8_t *)(intptr_t)(((
void *)src))); src += 8; fimd_swap_data(swap, &data); for
(i = (64 / (8) - 1); i >= 0; i--) { w->pixel_to_rgb(w->
palette[(data >> ((8) * i)) & ((1ULL << (8)) -
1)], &p); p.a = w->get_alpha(w, p.a); if (blend) { ifb
+= get_pixel_ifb(ifb, &p_old); exynos4210_fimd_blend_pixel
(w, p_old, &p); } dst += put_pixel_ifb(p, dst); } width -=
(64 / (8)); } while (width > 0); }
835DEF_DRAW_LINE_NOPALETTE(8)static void draw_line_8(Exynos4210fimdWindow *w, uint8_t *src
, uint8_t *dst, _Bool blend) { int width = w->rightbot_x -
w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w->
wincon & 0x078000) >> 15; uint64_t data; rgba p, p_old
; int i; do { data = ldq_le_p((uint8_t *)(intptr_t)(((void *)
src))); src += 8; fimd_swap_data(swap, &data); for (i = (
64 / (8) - 1); i >= 0; i--) { w->pixel_to_rgb((data >>
((8) * i)) & ((1ULL << (8)) - 1), &p); p.a = w
->get_alpha(w, p.a); if (blend) { ifb += get_pixel_ifb(ifb
, &p_old); exynos4210_fimd_blend_pixel(w, p_old, &p);
} dst += put_pixel_ifb(p, dst); } width -= (64 / (8)); } while
(width > 0); }
/* 8bpp mode has palette and non-palette versions */
836DEF_DRAW_LINE_NOPALETTE(16)static void draw_line_16(Exynos4210fimdWindow *w, uint8_t *src
, uint8_t *dst, _Bool blend) { int width = w->rightbot_x -
w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w->
wincon & 0x078000) >> 15; uint64_t data; rgba p, p_old
; int i; do { data = ldq_le_p((uint8_t *)(intptr_t)(((void *)
src))); src += 8; fimd_swap_data(swap, &data); for (i = (
64 / (16) - 1); i >= 0; i--) { w->pixel_to_rgb((data >>
((16) * i)) & ((1ULL << (16)) - 1), &p); p.a =
w->get_alpha(w, p.a); if (blend) { ifb += get_pixel_ifb(ifb
, &p_old); exynos4210_fimd_blend_pixel(w, p_old, &p);
} dst += put_pixel_ifb(p, dst); } width -= (64 / (16)); } while
(width > 0); }
837DEF_DRAW_LINE_NOPALETTE(32)static void draw_line_32(Exynos4210fimdWindow *w, uint8_t *src
, uint8_t *dst, _Bool blend) { int width = w->rightbot_x -
w->lefttop_x + 1; uint8_t *ifb = dst; uint8_t swap = (w->
wincon & 0x078000) >> 15; uint64_t data; rgba p, p_old
; int i; do { data = ldq_le_p((uint8_t *)(intptr_t)(((void *)
src))); src += 8; fimd_swap_data(swap, &data); for (i = (
64 / (32) - 1); i >= 0; i--) { w->pixel_to_rgb((data >>
((32) * i)) & ((1ULL << (32)) - 1), &p); p.a =
w->get_alpha(w, p.a); if (blend) { ifb += get_pixel_ifb(ifb
, &p_old); exynos4210_fimd_blend_pixel(w, p_old, &p);
} dst += put_pixel_ifb(p, dst); } width -= (64 / (32)); } while
(width > 0); }
838
839/* Special draw line routine for window color map case */
840static void draw_line_mapcolor(Exynos4210fimdWindow *w, uint8_t *src,
841 uint8_t *dst, bool_Bool blend)
842{
843 rgba p, p_old;
844 uint8_t *ifb = dst;
845 int width = w->rightbot_x - w->lefttop_x + 1;
846 uint32_t map_color = w->winmap & FIMD_WINMAP_COLOR_MASK0x00FFFFFF;
847
848 do {
849 pixel_888_to_rgb(map_color, &p);
850 p.a = w->get_alpha(w, p.a);
851 if (blend) {
852 ifb += get_pixel_ifb(ifb, &p_old);
853 exynos4210_fimd_blend_pixel(w, p_old, &p);
854 }
855 dst += put_pixel_ifb(p, dst);
856 } while (--width);
857}
858
859/* Write RGB to QEMU's GraphicConsole framebuffer */
860
861static int put_to_qemufb_pixel8(const rgba p, uint8_t *d)
862{
863 uint32_t pixel = rgb_to_pixel8(p.r, p.g, p.b);
864 *(uint8_t *)d = pixel;
865 return 1;
866}
867
868static int put_to_qemufb_pixel15(const rgba p, uint8_t *d)
869{
870 uint32_t pixel = rgb_to_pixel15(p.r, p.g, p.b);
871 *(uint16_t *)d = pixel;
872 return 2;
873}
874
875static int put_to_qemufb_pixel16(const rgba p, uint8_t *d)
876{
877 uint32_t pixel = rgb_to_pixel16(p.r, p.g, p.b);
878 *(uint16_t *)d = pixel;
879 return 2;
880}
881
882static int put_to_qemufb_pixel24(const rgba p, uint8_t *d)
883{
884 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);
885 *(uint8_t *)d++ = (pixel >> 0) & 0xFF;
886 *(uint8_t *)d++ = (pixel >> 8) & 0xFF;
887 *(uint8_t *)d++ = (pixel >> 16) & 0xFF;
888 return 3;
889}
890
891static int put_to_qemufb_pixel32(const rgba p, uint8_t *d)
892{
893 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);
894 *(uint32_t *)d = pixel;
895 return 4;
896}
897
898/* Routine to copy pixel from internal buffer to QEMU buffer */
899static int (*put_pixel_toqemu)(const rgba p, uint8_t *pixel);
900static inline void fimd_update_putpix_qemu(int bpp)
901{
902 switch (bpp) {
903 case 8:
904 put_pixel_toqemu = put_to_qemufb_pixel8;
905 break;
906 case 15:
907 put_pixel_toqemu = put_to_qemufb_pixel15;
908 break;
909 case 16:
910 put_pixel_toqemu = put_to_qemufb_pixel16;
911 break;
912 case 24:
913 put_pixel_toqemu = put_to_qemufb_pixel24;
914 break;
915 case 32:
916 put_pixel_toqemu = put_to_qemufb_pixel32;
917 break;
918 default:
919 hw_error("exynos4210.fimd: unsupported BPP (%d)", bpp);
920 break;
921 }
922}
923
924/* Routine to copy a line from internal frame buffer to QEMU display */
925static void fimd_copy_line_toqemu(int width, uint8_t *src, uint8_t *dst)
926{
927 rgba p;
928
929 do {
930 src += get_pixel_ifb(src, &p);
931 dst += put_pixel_toqemu(p, dst);
932 } while (--width);
933}
934
935/* Parse BPPMODE_F = WINCON1[5:2] bits */
936static void exynos4210_fimd_update_win_bppmode(Exynos4210fimdState *s, int win)
937{
938 Exynos4210fimdWindow *w = &s->window[win];
939
940 if (w->winmap & FIMD_WINMAP_EN(1 << 24)) {
941 w->draw_line = draw_line_mapcolor;
942 return;
943 }
944
945 switch (WIN_BPP_MODE(w)((w->wincon >> 2) & 0xF)) {
946 case 0:
947 w->draw_line = draw_line_palette_1;
948 w->pixel_to_rgb =
949 palette_data_format[exynos4210_fimd_palette_format(s, win)];
950 break;
951 case 1:
952 w->draw_line = draw_line_palette_2;
953 w->pixel_to_rgb =
954 palette_data_format[exynos4210_fimd_palette_format(s, win)];
955 break;
956 case 2:
957 w->draw_line = draw_line_palette_4;
958 w->pixel_to_rgb =
959 palette_data_format[exynos4210_fimd_palette_format(s, win)];
960 break;
961 case 3:
962 w->draw_line = draw_line_palette_8;
963 w->pixel_to_rgb =
964 palette_data_format[exynos4210_fimd_palette_format(s, win)];
965 break;
966 case 4:
967 w->draw_line = draw_line_8;
968 w->pixel_to_rgb = pixel_a232_to_rgb;
969 break;
970 case 5:
971 w->draw_line = draw_line_16;
972 w->pixel_to_rgb = pixel_565_to_rgb;
973 break;
974 case 6:
975 w->draw_line = draw_line_16;
976 w->pixel_to_rgb = pixel_a555_to_rgb;
977 break;
978 case 7:
979 w->draw_line = draw_line_16;
980 w->pixel_to_rgb = pixel_1555_to_rgb;
981 break;
982 case 8:
983 w->draw_line = draw_line_32;
984 w->pixel_to_rgb = pixel_666_to_rgb;
985 break;
986 case 9:
987 w->draw_line = draw_line_32;
988 w->pixel_to_rgb = pixel_a665_to_rgb;
989 break;
990 case 10:
991 w->draw_line = draw_line_32;
992 w->pixel_to_rgb = pixel_a666_to_rgb;
993 break;
994 case 11:
995 w->draw_line = draw_line_32;
996 w->pixel_to_rgb = pixel_888_to_rgb;
997 break;
998 case 12:
999 w->draw_line = draw_line_32;
1000 w->pixel_to_rgb = pixel_a887_to_rgb;
1001 break;
1002 case 13:
1003 w->draw_line = draw_line_32;
1004 if ((w->wincon & FIMD_WINCON_BLD_PIX(1 << 6)) && (w->wincon &
1005 FIMD_WINCON_ALPHA_SEL(1 << 1))) {
1006 w->pixel_to_rgb = pixel_8888_to_rgb;
1007 } else {
1008 w->pixel_to_rgb = pixel_a888_to_rgb;
1009 }
1010 break;
1011 case 14:
1012 w->draw_line = draw_line_16;
1013 if ((w->wincon & FIMD_WINCON_BLD_PIX(1 << 6)) && (w->wincon &
1014 FIMD_WINCON_ALPHA_SEL(1 << 1))) {
1015 w->pixel_to_rgb = pixel_4444_to_rgb;
1016 } else {
1017 w->pixel_to_rgb = pixel_a444_to_rgb;
1018 }
1019 break;
1020 case 15:
1021 w->draw_line = draw_line_16;
1022 w->pixel_to_rgb = pixel_555_to_rgb;
1023 break;
1024 }
1025}
1026
1027#if EXYNOS4210_FIMD_MODE_TRACE0 > 0
1028static const char *exynos4210_fimd_get_bppmode(int mode_code)
1029{
1030 switch (mode_code) {
1031 case 0:
1032 return "1 bpp";
1033 case 1:
1034 return "2 bpp";
1035 case 2:
1036 return "4 bpp";
1037 case 3:
1038 return "8 bpp (palettized)";
1039 case 4:
1040 return "8 bpp (non-palettized, A: 1-R:2-G:3-B:2)";
1041 case 5:
1042 return "16 bpp (non-palettized, R:5-G:6-B:5)";
1043 case 6:
1044 return "16 bpp (non-palettized, A:1-R:5-G:5-B:5)";
1045 case 7:
1046 return "16 bpp (non-palettized, I :1-R:5-G:5-B:5)";
1047 case 8:
1048 return "Unpacked 18 bpp (non-palettized, R:6-G:6-B:6)";
1049 case 9:
1050 return "Unpacked 18bpp (non-palettized,A:1-R:6-G:6-B:5)";
1051 case 10:
1052 return "Unpacked 19bpp (non-palettized,A:1-R:6-G:6-B:6)";
1053 case 11:
1054 return "Unpacked 24 bpp (non-palettized R:8-G:8-B:8)";
1055 case 12:
1056 return "Unpacked 24 bpp (non-palettized A:1-R:8-G:8-B:7)";
1057 case 13:
1058 return "Unpacked 25 bpp (non-palettized A:1-R:8-G:8-B:8)";
1059 case 14:
1060 return "Unpacked 13 bpp (non-palettized A:1-R:4-G:4-B:4)";
1061 case 15:
1062 return "Unpacked 15 bpp (non-palettized R:5-G:5-B:5)";
1063 default:
1064 return "Non-existing bpp mode";
1065 }
1066}
1067
1068static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
1069 int win_num, uint32_t val)
1070{
1071 Exynos4210fimdWindow *w = &s->window[win_num];
1072
1073 if (w->winmap & FIMD_WINMAP_EN(1 << 24)) {
1074 printf("QEMU FIMD: Window %d is mapped with MAPCOLOR=0x%x\n",
1075 win_num, w->winmap & 0xFFFFFF);
1076 return;
1077 }
1078
1079 if ((val != 0xFFFFFFFF) && ((w->wincon >> 2) & 0xF) == ((val >> 2) & 0xF)) {
1080 return;
1081 }
1082 printf("QEMU FIMD: Window %d BPP mode set to %s\n", win_num,
1083 exynos4210_fimd_get_bppmode((val >> 2) & 0xF));
1084}
1085#else
1086static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
1087 int win_num, uint32_t val)
1088{
1089
1090}
1091#endif
1092
1093static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w)
1094{
1095 switch (w->wincon & FIMD_WINCON_BUFSTATUS((1 << 21) | (1 << 31))) {
1096 case FIMD_WINCON_BUF0_STAT((0 << 21) | (0 << 31)):
1097 return 0;
1098 case FIMD_WINCON_BUF1_STAT((1 << 21) | (0 << 31)):
1099 return 1;
1100 case FIMD_WINCON_BUF2_STAT((0 << 21) | (1 << 31)):
1101 return 2;
1102 default:
1103 DPRINT_ERROR("Non-existent buffer index\n")do { } while (0);
1104 return 0;
1105 }
1106}
1107
1108/* Updates specified window's MemorySection based on values of WINCON,
1109 * VIDOSDA, VIDOSDB, VIDWADDx and SHADOWCON registers */
1110static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
1111{
1112 Exynos4210fimdWindow *w = &s->window[win];
1113 target_phys_addr_t fb_start_addr, fb_mapped_len;
1114
1115 if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN(1 << 0)) ||
1116 FIMD_WINDOW_PROTECTED(s->shadowcon, win)((s->shadowcon) & (1 << (10 + (win))))) {
1117 return;
1118 }
1119
1120 if (w->host_fb_addr) {
1121 cpu_physical_memory_unmap(w->host_fb_addr, w->fb_len, 0, 0);
1122 w->host_fb_addr = NULL((void*)0);
1123 w->fb_len = 0;
1124 }
1125
1126 fb_start_addr = w->buf_start[fimd_get_buffer_id(w)];
1127 /* Total number of bytes of virtual screen used by current window */
1128 w->fb_len = fb_mapped_len = (w->virtpage_width + w->virtpage_offsize) *
1129 (w->rightbot_y - w->lefttop_y + 1);
1130 w->mem_section = memory_region_find(sysbus_address_space(&s->busdev),
1131 fb_start_addr, w->fb_len);
1132 assert(w->mem_section.mr)((w->mem_section.mr) ? (void) (0) : __assert_fail ("w->mem_section.mr"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/../exynos4210_fimd.c"
, 1132, __PRETTY_FUNCTION__))
;
1133 assert(w->mem_section.offset_within_address_space == fb_start_addr)((w->mem_section.offset_within_address_space == fb_start_addr
) ? (void) (0) : __assert_fail ("w->mem_section.offset_within_address_space == fb_start_addr"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/arm/../exynos4210_fimd.c"
, 1133, __PRETTY_FUNCTION__))
;
1134 DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n",do { } while (0)
1135 win, fb_start_addr, w->fb_len)do { } while (0);
1136
1137 if (w->mem_section.size != w->fb_len ||
1138 !memory_region_is_ram(w->mem_section.mr)) {
1139 DPRINT_ERROR("Failed to find window %u framebuffer region\n", win)do { } while (0);
1140 goto error_return;
1141 }
1142
1143 w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len, 0);
1144 if (!w->host_fb_addr) {
1145 DPRINT_ERROR("Failed to map window %u framebuffer\n", win)do { } while (0);
1146 goto error_return;
1147 }
1148
1149 if (fb_mapped_len != w->fb_len) {
1150 DPRINT_ERROR("Window %u mapped framebuffer length is less then "do { } while (0)
1151 "expected\n", win)do { } while (0);
1152 cpu_physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0);
1153 goto error_return;
1154 }
1155 return;
1156
1157error_return:
1158 w->mem_section.mr = NULL((void*)0);
1159 w->mem_section.size = 0;
1160 w->host_fb_addr = NULL((void*)0);
1161 w->fb_len = 0;
1162}
1163
1164static void exynos4210_fimd_enable(Exynos4210fimdState *s, bool_Bool enabled)
1165{
1166 if (enabled && !s->enabled) {
1167 unsigned w;
1168 s->enabled = true1;
1169 for (w = 0; w < NUM_OF_WINDOWS5; w++) {
1170 fimd_update_memory_section(s, w);
1171 }
1172 }
1173 s->enabled = enabled;
1174 DPRINT_TRACE("display controller %s\n", enabled ? "enabled" : "disabled")do { } while (0);
1175}
1176
1177static inline uint32_t unpack_upper_4(uint32_t x)
1178{
1179 return ((x & 0xF00) << 12) | ((x & 0xF0) << 8) | ((x & 0xF) << 4);
1180}
1181
1182static inline uint32_t pack_upper_4(uint32_t x)
1183{
1184 return (((x & 0xF00000) >> 12) | ((x & 0xF000) >> 8) |
1185 ((x & 0xF0) >> 4)) & 0xFFF;
1186}
1187
1188static void exynos4210_fimd_update_irq(Exynos4210fimdState *s)
1189{
1190 if (!(s->vidintcon[0] & FIMD_VIDINT_INTEN(1 << 0))) {
1191 qemu_irq_lower(s->irq[0]);
1192 qemu_irq_lower(s->irq[1]);
1193 qemu_irq_lower(s->irq[2]);
1194 return;
1195 }
1196 if ((s->vidintcon[0] & FIMD_VIDINT_INTFIFOEN(1 << 1)) &&
1197 (s->vidintcon[1] & FIMD_VIDINT_INTFIFOPEND(1 << 0))) {
1198 qemu_irq_raise(s->irq[0]);
1199 } else {
1200 qemu_irq_lower(s->irq[0]);
1201 }
1202 if ((s->vidintcon[0] & FIMD_VIDINT_INTFRMEN(1 << 12)) &&
1203 (s->vidintcon[1] & FIMD_VIDINT_INTFRMPEND(1 << 1))) {
1204 qemu_irq_raise(s->irq[1]);
1205 } else {
1206 qemu_irq_lower(s->irq[1]);
1207 }
1208 if ((s->vidintcon[0] & FIMD_VIDINT_I80IFDONE(1 << 17)) &&
1209 (s->vidintcon[1] & FIMD_VIDINT_INTI80PEND(1 << 2))) {
1210 qemu_irq_raise(s->irq[2]);
1211 } else {
1212 qemu_irq_lower(s->irq[2]);
1213 }
1214}
1215
1216static void exynos4210_fimd_invalidate(void *opaque)
1217{
1218 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1219 s->invalidate = true1;
1220}
1221
1222static void exynos4210_update_resolution(Exynos4210fimdState *s)
1223{
1224 /* LCD resolution is stored in VIDEO TIME CONTROL REGISTER 2 */
1225 uint32_t width = ((s->vidtcon[2] >> FIMD_VIDTCON2_HOR_SHIFT0) &
1226 FIMD_VIDTCON2_SIZE_MASK0x07FF) + 1;
1227 uint32_t height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT11) &
1228 FIMD_VIDTCON2_SIZE_MASK0x07FF) + 1;
1229
1230 if (s->ifb == NULL((void*)0) || ds_get_width(s->console) != width ||
1231 ds_get_height(s->console) != height) {
1232 DPRINT_L1("Resolution changed from %ux%u to %ux%u\n",do { } while (0)
1233 ds_get_width(s->console), ds_get_height(s->console), width, height)do { } while (0);
1234 qemu_console_resize(s->console, width, height);
1235 s->ifb = g_realloc(s->ifb, width * height * RGBA_SIZE7 + 1);
1236 memset(s->ifb, 0, width * height * RGBA_SIZE7 + 1);
1237 exynos4210_fimd_invalidate(s);
1238 }
1239}
1240
1241static void exynos4210_fimd_update(void *opaque)
1242{
1243 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1244 Exynos4210fimdWindow *w;
1245 int i, line;
1246 target_phys_addr_t fb_line_addr, inc_size;
1247 int scrn_height;
1248 int first_line = -1, last_line = -1, scrn_width;
1249 bool_Bool blend = false0;
1250 uint8_t *host_fb_addr;
1251 bool_Bool is_dirty = false0;
1252 const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK0x07FF) + 1;
1253 const int global_height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT11) &
1254 FIMD_VIDTCON2_SIZE_MASK0x07FF) + 1;
1255
1256 if (!s || !s->console || !ds_get_bits_per_pixel(s->console) ||
1257 !s->enabled) {
1258 return;
1259 }
1260 exynos4210_update_resolution(s);
1261
1262 for (i = 0; i < NUM_OF_WINDOWS5; i++) {
1263 w = &s->window[i];
1264 if ((w->wincon & FIMD_WINCON_ENWIN(1 << 0)) && w->host_fb_addr) {
1265 scrn_height = w->rightbot_y - w->lefttop_y + 1;
1266 scrn_width = w->virtpage_width;
1267 /* Total width of virtual screen page in bytes */
1268 inc_size = scrn_width + w->virtpage_offsize;
1269 memory_region_sync_dirty_bitmap(w->mem_section.mr);
1270 host_fb_addr = w->host_fb_addr;
1271 fb_line_addr = w->mem_section.offset_within_region;
1272
1273 for (line = 0; line < scrn_height; line++) {
1274 is_dirty = memory_region_get_dirty(w->mem_section.mr,
1275 fb_line_addr, scrn_width, DIRTY_MEMORY_VGA0);
1276
1277 if (s->invalidate || is_dirty) {
1278 if (first_line == -1) {
1279 first_line = line;
1280 }
1281 last_line = line;
1282 w->draw_line(w, host_fb_addr, s->ifb +
1283 w->lefttop_x * RGBA_SIZE7 + (w->lefttop_y + line) *
1284 global_width * RGBA_SIZE7, blend);
1285 }
1286 host_fb_addr += inc_size;
1287 fb_line_addr += inc_size;
1288 is_dirty = false0;
Value stored to 'is_dirty' is never read
1289 }
1290 memory_region_reset_dirty(w->mem_section.mr,
1291 w->mem_section.offset_within_region,
1292 w->fb_len, DIRTY_MEMORY_VGA0);
1293 blend = true1;
1294 }
1295 }
1296
1297 /* Copy resulting image to QEMU_CONSOLE. */
1298 if (first_line >= 0) {
1299 uint8_t *d;
1300 int bpp;
1301
1302 bpp = ds_get_bits_per_pixel(s->console);
1303 fimd_update_putpix_qemu(bpp);
1304 bpp = (bpp + 1) >> 3;
1305 d = ds_get_data(s->console);
1306 for (line = first_line; line <= last_line; line++) {
1307 fimd_copy_line_toqemu(global_width, s->ifb + global_width * line *
1308 RGBA_SIZE7, d + global_width * line * bpp);
1309 }
1310 dpy_update(s->console, 0, 0, global_width, global_height);
1311 }
1312 s->invalidate = false0;
1313 s->vidintcon[1] |= FIMD_VIDINT_INTFRMPEND(1 << 1);
1314 if ((s->vidcon[0] & FIMD_VIDCON0_ENVID_F(1 << 0)) == 0) {
1315 exynos4210_fimd_enable(s, false0);
1316 }
1317 exynos4210_fimd_update_irq(s);
1318}
1319
1320static void exynos4210_fimd_reset(DeviceState *d)
1321{
1322 Exynos4210fimdState *s = DO_UPCAST(Exynos4210fimdState, busdev.qdev, d)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(Exynos4210fimdState, busdev.qdev)]; ({ const
typeof(((Exynos4210fimdState *) 0)->busdev.qdev) *__mptr =
(d); (Exynos4210fimdState *) ((char *) __mptr - __builtin_offsetof
(Exynos4210fimdState, busdev.qdev));});}))
;
1323 unsigned w;
1324
1325 DPRINT_TRACE("Display controller reset\n")do { } while (0);
1326 /* Set all display controller registers to 0 */
1327 memset(&s->vidcon, 0, (uint8_t *)&s->window - (uint8_t *)&s->vidcon);
1328 for (w = 0; w < NUM_OF_WINDOWS5; w++) {
1329 memset(&s->window[w], 0, sizeof(Exynos4210fimdWindow));
1330 s->window[w].blendeq = 0xC2;
1331 exynos4210_fimd_update_win_bppmode(s, w);
1332 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
1333 fimd_update_get_alpha(s, w);
1334 }
1335
1336 if (s->ifb != NULL((void*)0)) {
1337 g_free(s->ifb);
1338 }
1339 s->ifb = NULL((void*)0);
1340
1341 exynos4210_fimd_invalidate(s);
1342 exynos4210_fimd_enable(s, false0);
1343 /* Some registers have non-zero initial values */
1344 s->winchmap = 0x7D517D51;
1345 s->colorgaincon = 0x10040100;
1346 s->huecoef_cr[0] = s->huecoef_cr[3] = 0x01000100;
1347 s->huecoef_cb[0] = s->huecoef_cb[3] = 0x01000100;
1348 s->hueoffset = 0x01800080;
1349}
1350
1351static void exynos4210_fimd_write(void *opaque, target_phys_addr_t offset,
1352 uint64_t val, unsigned size)
1353{
1354 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1355 unsigned w, i;
1356 uint32_t old_value;
1357
1358 DPRINT_L2("write offset 0x%08x, value=%llu(0x%08llx)\n", offset,do { } while (0)
1359 (long long unsigned int)val, (long long unsigned int)val)do { } while (0);
1360
1361 switch (offset) {
1362 case FIMD_VIDCON00x0000:
1363 if ((val & FIMD_VIDCON0_ENVID_MASK((1 << 0) | (1 << 1))) == FIMD_VIDCON0_ENVID_MASK((1 << 0) | (1 << 1))) {
1364 exynos4210_fimd_enable(s, true1);
1365 } else {
1366 if ((val & FIMD_VIDCON0_ENVID(1 << 1)) == 0) {
1367 exynos4210_fimd_enable(s, false0);
1368 }
1369 }
1370 s->vidcon[0] = val;
1371 break;
1372 case FIMD_VIDCON10x0004:
1373 /* Leave read-only bits as is */
1374 val = (val & (~FIMD_VIDCON1_ROMASK0x07FFE000)) |
1375 (s->vidcon[1] & FIMD_VIDCON1_ROMASK0x07FFE000);
1376 s->vidcon[1] = val;
1377 break;
1378 case FIMD_VIDCON20x0008 ... FIMD_VIDCON30x000C:
1379 s->vidcon[(offset) >> 2] = val;
1380 break;
1381 case FIMD_VIDTCON_START0x10 ... FIMD_VIDTCON_END0x1C:
1382 s->vidtcon[(offset - FIMD_VIDTCON_START0x10) >> 2] = val;
1383 break;
1384 case FIMD_WINCON_START0x0020 ... FIMD_WINCON_END0x0030:
1385 w = (offset - FIMD_WINCON_START0x0020) >> 2;
1386 /* Window's current buffer ID */
1387 i = fimd_get_buffer_id(&s->window[w]);
1388 old_value = s->window[w].wincon;
1389 val = (val & ~FIMD_WINCON_ROMASK0x82200000) |
1390 (s->window[w].wincon & FIMD_WINCON_ROMASK0x82200000);
1391 if (w == 0) {
1392 /* Window 0 wincon ALPHA_MUL bit must always be 0 */
1393 val &= ~FIMD_WINCON_ALPHA_MUL(1 << 7);
1394 }
1395 exynos4210_fimd_trace_bppmode(s, w, val);
1396 switch (val & FIMD_WINCON_BUFSELECT((1 << 20) | (1 << 30))) {
1397 case FIMD_WINCON_BUF0_SEL((0 << 20) | (0 << 30)):
1398 val &= ~FIMD_WINCON_BUFSTATUS((1 << 21) | (1 << 31));
1399 break;
1400 case FIMD_WINCON_BUF1_SEL((1 << 20) | (0 << 30)):
1401 val = (val & ~FIMD_WINCON_BUFSTAT_H(1 << 31)) | FIMD_WINCON_BUFSTAT_L(1 << 21);
1402 break;
1403 case FIMD_WINCON_BUF2_SEL((0 << 20) | (1 << 30)):
1404 if (val & FIMD_WINCON_BUFMODE(1 << 14)) {
1405 val = (val & ~FIMD_WINCON_BUFSTAT_L(1 << 21)) | FIMD_WINCON_BUFSTAT_H(1 << 31);
1406 }
1407 break;
1408 default:
1409 break;
1410 }
1411 s->window[w].wincon = val;
1412 exynos4210_fimd_update_win_bppmode(s, w);
1413 fimd_update_get_alpha(s, w);
1414 if ((i != fimd_get_buffer_id(&s->window[w])) ||
1415 (!(old_value & FIMD_WINCON_ENWIN(1 << 0)) && (s->window[w].wincon &
1416 FIMD_WINCON_ENWIN(1 << 0)))) {
1417 fimd_update_memory_section(s, w);
1418 }
1419 break;
1420 case FIMD_SHADOWCON0x0034:
1421 old_value = s->shadowcon;
1422 s->shadowcon = val;
1423 for (w = 0; w < NUM_OF_WINDOWS5; w++) {
1424 if (FIMD_WINDOW_PROTECTED(old_value, w)((old_value) & (1 << (10 + (w)))) &&
1425 !FIMD_WINDOW_PROTECTED(s->shadowcon, w)((s->shadowcon) & (1 << (10 + (w))))) {
1426 fimd_update_memory_section(s, w);
1427 }
1428 }
1429 break;
1430 case FIMD_WINCHMAP0x003C:
1431 s->winchmap = val;
1432 break;
1433 case FIMD_VIDOSD_START0x0040 ... FIMD_VIDOSD_END0x0088:
1434 w = (offset - FIMD_VIDOSD_START0x0040) >> 4;
1435 i = ((offset - FIMD_VIDOSD_START0x0040) & 0xF) >> 2;
1436 switch (i) {
1437 case 0:
1438 old_value = s->window[w].lefttop_y;
1439 s->window[w].lefttop_x = (val >> FIMD_VIDOSD_HOR_SHIFT11) &
1440 FIMD_VIDOSD_COORD_MASK0x07FF;
1441 s->window[w].lefttop_y = (val >> FIMD_VIDOSD_VER_SHIFT0) &
1442 FIMD_VIDOSD_COORD_MASK0x07FF;
1443 if (s->window[w].lefttop_y != old_value) {
1444 fimd_update_memory_section(s, w);
1445 }
1446 break;
1447 case 1:
1448 old_value = s->window[w].rightbot_y;
1449 s->window[w].rightbot_x = (val >> FIMD_VIDOSD_HOR_SHIFT11) &
1450 FIMD_VIDOSD_COORD_MASK0x07FF;
1451 s->window[w].rightbot_y = (val >> FIMD_VIDOSD_VER_SHIFT0) &
1452 FIMD_VIDOSD_COORD_MASK0x07FF;
1453 if (s->window[w].rightbot_y != old_value) {
1454 fimd_update_memory_section(s, w);
1455 }
1456 break;
1457 case 2:
1458 if (w == 0) {
1459 s->window[w].osdsize = val;
1460 } else {
1461 s->window[w].alpha_val[0] =
1462 unpack_upper_4((val & FIMD_VIDOSD_ALPHA_AEN00xFFF000) >>
1463 FIMD_VIDOSD_AEN0_SHIFT12) |
1464 (s->window[w].alpha_val[0] & FIMD_VIDALPHA_ALPHA_LOWER0x000F0F0F);
1465 s->window[w].alpha_val[1] =
1466 unpack_upper_4(val & FIMD_VIDOSD_ALPHA_AEN10x000FFF) |
1467 (s->window[w].alpha_val[1] & FIMD_VIDALPHA_ALPHA_LOWER0x000F0F0F);
1468 }
1469 break;
1470 case 3:
1471 if (w != 1 && w != 2) {
1472 DPRINT_ERROR("Bad write offset 0x%08x\n", offset)do { } while (0);
1473 return;
1474 }
1475 s->window[w].osdsize = val;
1476 break;
1477 }
1478 break;
1479 case FIMD_VIDWADD0_START0x00A0 ... FIMD_VIDWADD0_END0x00C4:
1480 w = (offset - FIMD_VIDWADD0_START0x00A0) >> 3;
1481 i = ((offset - FIMD_VIDWADD0_START0x00A0) >> 2) & 1;
1482 if (i == fimd_get_buffer_id(&s->window[w]) &&
1483 s->window[w].buf_start[i] != val) {
1484 s->window[w].buf_start[i] = val;
1485 fimd_update_memory_section(s, w);
1486 break;
1487 }
1488 s->window[w].buf_start[i] = val;
1489 break;
1490 case FIMD_VIDWADD1_START0x00D0 ... FIMD_VIDWADD1_END0x00F4:
1491 w = (offset - FIMD_VIDWADD1_START0x00D0) >> 3;
1492 i = ((offset - FIMD_VIDWADD1_START0x00D0) >> 2) & 1;
1493 s->window[w].buf_end[i] = val;
1494 break;
1495 case FIMD_VIDWADD2_START0x0100 ... FIMD_VIDWADD2_END0x0110:
1496 w = (offset - FIMD_VIDWADD2_START0x0100) >> 2;
1497 if (((val & FIMD_VIDWADD2_PAGEWIDTH0x1FFF) != s->window[w].virtpage_width) ||
1498 (((val >> FIMD_VIDWADD2_OFFSIZE_SHIFT13) & FIMD_VIDWADD2_OFFSIZE0x1FFF) !=
1499 s->window[w].virtpage_offsize)) {
1500 s->window[w].virtpage_width = val & FIMD_VIDWADD2_PAGEWIDTH0x1FFF;
1501 s->window[w].virtpage_offsize =
1502 (val >> FIMD_VIDWADD2_OFFSIZE_SHIFT13) & FIMD_VIDWADD2_OFFSIZE0x1FFF;
1503 fimd_update_memory_section(s, w);
1504 }
1505 break;
1506 case FIMD_VIDINTCON00x130:
1507 s->vidintcon[0] = val;
1508 break;
1509 case FIMD_VIDINTCON10x134:
1510 s->vidintcon[1] &= ~(val & 7);
1511 exynos4210_fimd_update_irq(s);
1512 break;
1513 case FIMD_WKEYCON_START0x140 ... FIMD_WKEYCON_END0x15C:
1514 w = ((offset - FIMD_WKEYCON_START0x140) >> 3) + 1;
1515 i = ((offset - FIMD_WKEYCON_START0x140) >> 2) & 1;
1516 s->window[w].keycon[i] = val;
1517 break;
1518 case FIMD_WKEYALPHA_START0x160 ... FIMD_WKEYALPHA_END0x16C:
1519 w = ((offset - FIMD_WKEYALPHA_START0x160) >> 2) + 1;
1520 s->window[w].keyalpha = val;
1521 break;
1522 case FIMD_DITHMODE0x170:
1523 s->dithmode = val;
1524 break;
1525 case FIMD_WINMAP_START0x180 ... FIMD_WINMAP_END0x190:
1526 w = (offset - FIMD_WINMAP_START0x180) >> 2;
1527 old_value = s->window[w].winmap;
1528 s->window[w].winmap = val;
1529 if ((val & FIMD_WINMAP_EN(1 << 24)) ^ (old_value & FIMD_WINMAP_EN(1 << 24))) {
1530 exynos4210_fimd_invalidate(s);
1531 exynos4210_fimd_update_win_bppmode(s, w);
1532 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
1533 exynos4210_fimd_update(s);
1534 }
1535 break;
1536 case FIMD_WPALCON_HIGH0x019C ... FIMD_WPALCON_LOW0x01A0:
1537 i = (offset - FIMD_WPALCON_HIGH0x019C) >> 2;
1538 s->wpalcon[i] = val;
1539 if (s->wpalcon[1] & FIMD_WPALCON_UPDATEEN(1 << 9)) {
1540 for (w = 0; w < NUM_OF_WINDOWS5; w++) {
1541 exynos4210_fimd_update_win_bppmode(s, w);
1542 fimd_update_get_alpha(s, w);
1543 }
1544 }
1545 break;
1546 case FIMD_TRIGCON0x01A4:
1547 val = (val & ~FIMD_TRIGCON_ROMASK0x00000004) | (s->trigcon & FIMD_TRIGCON_ROMASK0x00000004);
1548 s->trigcon = val;
1549 break;
1550 case FIMD_I80IFCON_START0x01B0 ... FIMD_I80IFCON_END0x01BC:
1551 s->i80ifcon[(offset - FIMD_I80IFCON_START0x01B0) >> 2] = val;
1552 break;
1553 case FIMD_COLORGAINCON0x01C0:
1554 s->colorgaincon = val;
1555 break;
1556 case FIMD_LDI_CMDCON00x01D0 ... FIMD_LDI_CMDCON10x01D4:
1557 s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON00x01D0) >> 2] = val;
1558 break;
1559 case FIMD_SIFCCON00x01E0 ... FIMD_SIFCCON20x01E8:
1560 i = (offset - FIMD_SIFCCON00x01E0) >> 2;
1561 if (i != 2) {
1562 s->sifccon[i] = val;
1563 }
1564 break;
1565 case FIMD_HUECOEFCR_START0x01EC ... FIMD_HUECOEFCR_END0x01F4:
1566 i = (offset - FIMD_HUECOEFCR_START0x01EC) >> 2;
1567 s->huecoef_cr[i] = val;
1568 break;
1569 case FIMD_HUECOEFCB_START0x01FC ... FIMD_HUECOEFCB_END0x0208:
1570 i = (offset - FIMD_HUECOEFCB_START0x01FC) >> 2;
1571 s->huecoef_cb[i] = val;
1572 break;
1573 case FIMD_HUEOFFSET0x020C:
1574 s->hueoffset = val;
1575 break;
1576 case FIMD_VIDWALPHA_START0x21C ... FIMD_VIDWALPHA_END0x240:
1577 w = ((offset - FIMD_VIDWALPHA_START0x21C) >> 3);
1578 i = ((offset - FIMD_VIDWALPHA_START0x21C) >> 2) & 1;
1579 if (w == 0) {
1580 s->window[w].alpha_val[i] = val;
1581 } else {
1582 s->window[w].alpha_val[i] = (val & FIMD_VIDALPHA_ALPHA_LOWER0x000F0F0F) |
1583 (s->window[w].alpha_val[i] & FIMD_VIDALPHA_ALPHA_UPPER0x00F0F0F0);
1584 }
1585 break;
1586 case FIMD_BLENDEQ_START0x0244 ... FIMD_BLENDEQ_END0x0250:
1587 s->window[(offset - FIMD_BLENDEQ_START0x0244) >> 2].blendeq = val;
1588 break;
1589 case FIMD_BLENDCON0x0260:
1590 old_value = s->blendcon;
1591 s->blendcon = val;
1592 if ((s->blendcon & FIMD_ALPHA_8BIT(1 << 0)) != (old_value & FIMD_ALPHA_8BIT(1 << 0))) {
1593 for (w = 0; w < NUM_OF_WINDOWS5; w++) {
1594 fimd_update_get_alpha(s, w);
1595 }
1596 }
1597 break;
1598 case FIMD_WRTQOSCON_START0x0264 ... FIMD_WRTQOSCON_END0x0274:
1599 s->window[(offset - FIMD_WRTQOSCON_START0x0264) >> 2].rtqoscon = val;
1600 break;
1601 case FIMD_I80IFCMD_START0x0280 ... FIMD_I80IFCMD_END0x02AC:
1602 s->i80ifcmd[(offset - FIMD_I80IFCMD_START0x0280) >> 2] = val;
1603 break;
1604 case FIMD_VIDW0ADD0_B20x20A0 ... FIMD_VIDW4ADD0_B20x20C0:
1605 if (offset & 0x0004) {
1606 DPRINT_ERROR("bad write offset 0x%08x\n", offset)do { } while (0);
1607 break;
1608 }
1609 w = (offset - FIMD_VIDW0ADD0_B20x20A0) >> 3;
1610 if (fimd_get_buffer_id(&s->window[w]) == 2 &&
1611 s->window[w].buf_start[2] != val) {
1612 s->window[w].buf_start[2] = val;
1613 fimd_update_memory_section(s, w);
1614 break;
1615 }
1616 s->window[w].buf_start[2] = val;
1617 break;
1618 case FIMD_SHD_ADD0_START0x40A0 ... FIMD_SHD_ADD0_END0x40C0:
1619 if (offset & 0x0004) {
1620 DPRINT_ERROR("bad write offset 0x%08x\n", offset)do { } while (0);
1621 break;
1622 }
1623 s->window[(offset - FIMD_SHD_ADD0_START0x40A0) >> 3].shadow_buf_start = val;
1624 break;
1625 case FIMD_SHD_ADD1_START0x40D0 ... FIMD_SHD_ADD1_END0x40F0:
1626 if (offset & 0x0004) {
1627 DPRINT_ERROR("bad write offset 0x%08x\n", offset)do { } while (0);
1628 break;
1629 }
1630 s->window[(offset - FIMD_SHD_ADD1_START0x40D0) >> 3].shadow_buf_end = val;
1631 break;
1632 case FIMD_SHD_ADD2_START0x4100 ... FIMD_SHD_ADD2_END0x4110:
1633 s->window[(offset - FIMD_SHD_ADD2_START0x4100) >> 2].shadow_buf_size = val;
1634 break;
1635 case FIMD_PAL_MEM_START0x2400 ... FIMD_PAL_MEM_END0x37FC:
1636 w = (offset - FIMD_PAL_MEM_START0x2400) >> 10;
1637 i = ((offset - FIMD_PAL_MEM_START0x2400) >> 2) & 0xFF;
1638 s->window[w].palette[i] = val;
1639 break;
1640 case FIMD_PALMEM_AL_START0x0400 ... FIMD_PALMEM_AL_END0x0BFC:
1641 /* Palette memory aliases for windows 0 and 1 */
1642 w = (offset - FIMD_PALMEM_AL_START0x0400) >> 10;
1643 i = ((offset - FIMD_PALMEM_AL_START0x0400) >> 2) & 0xFF;
1644 s->window[w].palette[i] = val;
1645 break;
1646 default:
1647 DPRINT_ERROR("bad write offset 0x%08x\n", offset)do { } while (0);
1648 break;
1649 }
1650}
1651
1652static uint64_t exynos4210_fimd_read(void *opaque, target_phys_addr_t offset,
1653 unsigned size)
1654{
1655 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1656 int w, i;
1657 uint32_t ret = 0;
1658
1659 DPRINT_L2("read offset 0x%08x\n", offset)do { } while (0);
1660
1661 switch (offset) {
1662 case FIMD_VIDCON00x0000 ... FIMD_VIDCON30x000C:
1663 return s->vidcon[(offset - FIMD_VIDCON00x0000) >> 2];
1664 case FIMD_VIDTCON_START0x10 ... FIMD_VIDTCON_END0x1C:
1665 return s->vidtcon[(offset - FIMD_VIDTCON_START0x10) >> 2];
1666 case FIMD_WINCON_START0x0020 ... FIMD_WINCON_END0x0030:
1667 return s->window[(offset - FIMD_WINCON_START0x0020) >> 2].wincon;
1668 case FIMD_SHADOWCON0x0034:
1669 return s->shadowcon;
1670 case FIMD_WINCHMAP0x003C:
1671 return s->winchmap;
1672 case FIMD_VIDOSD_START0x0040 ... FIMD_VIDOSD_END0x0088:
1673 w = (offset - FIMD_VIDOSD_START0x0040) >> 4;
1674 i = ((offset - FIMD_VIDOSD_START0x0040) & 0xF) >> 2;
1675 switch (i) {
1676 case 0:
1677 ret = ((s->window[w].lefttop_x & FIMD_VIDOSD_COORD_MASK0x07FF) <<
1678 FIMD_VIDOSD_HOR_SHIFT11) |
1679 (s->window[w].lefttop_y & FIMD_VIDOSD_COORD_MASK0x07FF);
1680 break;
1681 case 1:
1682 ret = ((s->window[w].rightbot_x & FIMD_VIDOSD_COORD_MASK0x07FF) <<
1683 FIMD_VIDOSD_HOR_SHIFT11) |
1684 (s->window[w].rightbot_y & FIMD_VIDOSD_COORD_MASK0x07FF);
1685 break;
1686 case 2:
1687 if (w == 0) {
1688 ret = s->window[w].osdsize;
1689 } else {
1690 ret = (pack_upper_4(s->window[w].alpha_val[0]) <<
1691 FIMD_VIDOSD_AEN0_SHIFT12) |
1692 pack_upper_4(s->window[w].alpha_val[1]);
1693 }
1694 break;
1695 case 3:
1696 if (w != 1 && w != 2) {
1697 DPRINT_ERROR("bad read offset 0x%08x\n", offset)do { } while (0);
1698 return 0xBAADBAAD;
1699 }
1700 ret = s->window[w].osdsize;
1701 break;
1702 }
1703 return ret;
1704 case FIMD_VIDWADD0_START0x00A0 ... FIMD_VIDWADD0_END0x00C4:
1705 w = (offset - FIMD_VIDWADD0_START0x00A0) >> 3;
1706 i = ((offset - FIMD_VIDWADD0_START0x00A0) >> 2) & 1;
1707 return s->window[w].buf_start[i];
1708 case FIMD_VIDWADD1_START0x00D0 ... FIMD_VIDWADD1_END0x00F4:
1709 w = (offset - FIMD_VIDWADD1_START0x00D0) >> 3;
1710 i = ((offset - FIMD_VIDWADD1_START0x00D0) >> 2) & 1;
1711 return s->window[w].buf_end[i];
1712 case FIMD_VIDWADD2_START0x0100 ... FIMD_VIDWADD2_END0x0110:
1713 w = (offset - FIMD_VIDWADD2_START0x0100) >> 2;
1714 return s->window[w].virtpage_width | (s->window[w].virtpage_offsize <<
1715 FIMD_VIDWADD2_OFFSIZE_SHIFT13);
1716 case FIMD_VIDINTCON00x130 ... FIMD_VIDINTCON10x134:
1717 return s->vidintcon[(offset - FIMD_VIDINTCON00x130) >> 2];
1718 case FIMD_WKEYCON_START0x140 ... FIMD_WKEYCON_END0x15C:
1719 w = ((offset - FIMD_WKEYCON_START0x140) >> 3) + 1;
1720 i = ((offset - FIMD_WKEYCON_START0x140) >> 2) & 1;
1721 return s->window[w].keycon[i];
1722 case FIMD_WKEYALPHA_START0x160 ... FIMD_WKEYALPHA_END0x16C:
1723 w = ((offset - FIMD_WKEYALPHA_START0x160) >> 2) + 1;
1724 return s->window[w].keyalpha;
1725 case FIMD_DITHMODE0x170:
1726 return s->dithmode;
1727 case FIMD_WINMAP_START0x180 ... FIMD_WINMAP_END0x190:
1728 return s->window[(offset - FIMD_WINMAP_START0x180) >> 2].winmap;
1729 case FIMD_WPALCON_HIGH0x019C ... FIMD_WPALCON_LOW0x01A0:
1730 return s->wpalcon[(offset - FIMD_WPALCON_HIGH0x019C) >> 2];
1731 case FIMD_TRIGCON0x01A4:
1732 return s->trigcon;
1733 case FIMD_I80IFCON_START0x01B0 ... FIMD_I80IFCON_END0x01BC:
1734 return s->i80ifcon[(offset - FIMD_I80IFCON_START0x01B0) >> 2];
1735 case FIMD_COLORGAINCON0x01C0:
1736 return s->colorgaincon;
1737 case FIMD_LDI_CMDCON00x01D0 ... FIMD_LDI_CMDCON10x01D4:
1738 return s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON00x01D0) >> 2];
1739 case FIMD_SIFCCON00x01E0 ... FIMD_SIFCCON20x01E8:
1740 i = (offset - FIMD_SIFCCON00x01E0) >> 2;
1741 return s->sifccon[i];
1742 case FIMD_HUECOEFCR_START0x01EC ... FIMD_HUECOEFCR_END0x01F4:
1743 i = (offset - FIMD_HUECOEFCR_START0x01EC) >> 2;
1744 return s->huecoef_cr[i];
1745 case FIMD_HUECOEFCB_START0x01FC ... FIMD_HUECOEFCB_END0x0208:
1746 i = (offset - FIMD_HUECOEFCB_START0x01FC) >> 2;
1747 return s->huecoef_cb[i];
1748 case FIMD_HUEOFFSET0x020C:
1749 return s->hueoffset;
1750 case FIMD_VIDWALPHA_START0x21C ... FIMD_VIDWALPHA_END0x240:
1751 w = ((offset - FIMD_VIDWALPHA_START0x21C) >> 3);
1752 i = ((offset - FIMD_VIDWALPHA_START0x21C) >> 2) & 1;
1753 return s->window[w].alpha_val[i] &
1754 (w == 0 ? 0xFFFFFF : FIMD_VIDALPHA_ALPHA_LOWER0x000F0F0F);
1755 case FIMD_BLENDEQ_START0x0244 ... FIMD_BLENDEQ_END0x0250:
1756 return s->window[(offset - FIMD_BLENDEQ_START0x0244) >> 2].blendeq;
1757 case FIMD_BLENDCON0x0260:
1758 return s->blendcon;
1759 case FIMD_WRTQOSCON_START0x0264 ... FIMD_WRTQOSCON_END0x0274:
1760 return s->window[(offset - FIMD_WRTQOSCON_START0x0264) >> 2].rtqoscon;
1761 case FIMD_I80IFCMD_START0x0280 ... FIMD_I80IFCMD_END0x02AC:
1762 return s->i80ifcmd[(offset - FIMD_I80IFCMD_START0x0280) >> 2];
1763 case FIMD_VIDW0ADD0_B20x20A0 ... FIMD_VIDW4ADD0_B20x20C0:
1764 if (offset & 0x0004) {
1765 break;
1766 }
1767 return s->window[(offset - FIMD_VIDW0ADD0_B20x20A0) >> 3].buf_start[2];
1768 case FIMD_SHD_ADD0_START0x40A0 ... FIMD_SHD_ADD0_END0x40C0:
1769 if (offset & 0x0004) {
1770 break;
1771 }
1772 return s->window[(offset - FIMD_SHD_ADD0_START0x40A0) >> 3].shadow_buf_start;
1773 case FIMD_SHD_ADD1_START0x40D0 ... FIMD_SHD_ADD1_END0x40F0:
1774 if (offset & 0x0004) {
1775 break;
1776 }
1777 return s->window[(offset - FIMD_SHD_ADD1_START0x40D0) >> 3].shadow_buf_end;
1778 case FIMD_SHD_ADD2_START0x4100 ... FIMD_SHD_ADD2_END0x4110:
1779 return s->window[(offset - FIMD_SHD_ADD2_START0x4100) >> 2].shadow_buf_size;
1780 case FIMD_PAL_MEM_START0x2400 ... FIMD_PAL_MEM_END0x37FC:
1781 w = (offset - FIMD_PAL_MEM_START0x2400) >> 10;
1782 i = ((offset - FIMD_PAL_MEM_START0x2400) >> 2) & 0xFF;
1783 return s->window[w].palette[i];
1784 case FIMD_PALMEM_AL_START0x0400 ... FIMD_PALMEM_AL_END0x0BFC:
1785 /* Palette aliases for win 0,1 */
1786 w = (offset - FIMD_PALMEM_AL_START0x0400) >> 10;
1787 i = ((offset - FIMD_PALMEM_AL_START0x0400) >> 2) & 0xFF;
1788 return s->window[w].palette[i];
1789 }
1790
1791 DPRINT_ERROR("bad read offset 0x%08x\n", offset)do { } while (0);
1792 return 0xBAADBAAD;
1793}
1794
1795static const MemoryRegionOps exynos4210_fimd_mmio_ops = {
1796 .read = exynos4210_fimd_read,
1797 .write = exynos4210_fimd_write,
1798 .valid = {
1799 .min_access_size = 4,
1800 .max_access_size = 4,
1801 .unaligned = false0
1802 },
1803 .endianness = DEVICE_NATIVE_ENDIAN,
1804};
1805
1806static int exynos4210_fimd_load(void *opaque, int version_id)
1807{
1808 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1809 int w;
1810
1811 if (version_id != 1) {
1812 return -EINVAL22;
1813 }
1814
1815 for (w = 0; w < NUM_OF_WINDOWS5; w++) {
1816 exynos4210_fimd_update_win_bppmode(s, w);
1817 fimd_update_get_alpha(s, w);
1818 fimd_update_memory_section(s, w);
1819 }
1820
1821 /* Redraw the whole screen */
1822 exynos4210_update_resolution(s);
1823 exynos4210_fimd_invalidate(s);
1824 exynos4210_fimd_enable(s, (s->vidcon[0] & FIMD_VIDCON0_ENVID_MASK((1 << 0) | (1 << 1))) ==
1825 FIMD_VIDCON0_ENVID_MASK((1 << 0) | (1 << 1)));
1826 return 0;
1827}
1828
1829static const VMStateDescription exynos4210_fimd_window_vmstate = {
1830 .name = "exynos4210.fimd_window",
1831 .version_id = 1,
1832 .minimum_version_id = 1,
1833 .fields = (VMStateField[]) {
1834 VMSTATE_UINT32(wincon, Exynos4210fimdWindow){ .name = ("wincon"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, wincon) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow *)
0)->wincon)*)0)), }
,
1835 VMSTATE_UINT32_ARRAY(buf_start, Exynos4210fimdWindow, 3){ .name = ("buf_start"), .version_id = (0), .num = (3), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, buf_start) + ((uint32_t(*)[3])0 - (typeof(((Exynos4210fimdWindow
*)0)->buf_start)*)0)), }
,
1836 VMSTATE_UINT32_ARRAY(buf_end, Exynos4210fimdWindow, 3){ .name = ("buf_end"), .version_id = (0), .num = (3), .info =
&(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, buf_end) + ((uint32_t(*)[3])0 - (typeof(((Exynos4210fimdWindow
*)0)->buf_end)*)0)), }
,
1837 VMSTATE_UINT32_ARRAY(keycon, Exynos4210fimdWindow, 2){ .name = ("keycon"), .version_id = (0), .num = (2), .info = &
(vmstate_info_uint32), .size = sizeof(uint32_t), .flags = VMS_ARRAY
, .offset = (__builtin_offsetof(Exynos4210fimdWindow, keycon)
+ ((uint32_t(*)[2])0 - (typeof(((Exynos4210fimdWindow *)0)->
keycon)*)0)), }
,
1838 VMSTATE_UINT32(keyalpha, Exynos4210fimdWindow){ .name = ("keyalpha"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, keyalpha) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow *
)0)->keyalpha)*)0)), }
,
1839 VMSTATE_UINT32(winmap, Exynos4210fimdWindow){ .name = ("winmap"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, winmap) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow *)
0)->winmap)*)0)), }
,
1840 VMSTATE_UINT32(blendeq, Exynos4210fimdWindow){ .name = ("blendeq"), .version_id = (0), .field_exists = (((
void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, blendeq) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow *
)0)->blendeq)*)0)), }
,
1841 VMSTATE_UINT32(rtqoscon, Exynos4210fimdWindow){ .name = ("rtqoscon"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, rtqoscon) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow *
)0)->rtqoscon)*)0)), }
,
1842 VMSTATE_UINT32_ARRAY(palette, Exynos4210fimdWindow, 256){ .name = ("palette"), .version_id = (0), .num = (256), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, palette) + ((uint32_t(*)[256])0 - (typeof(((Exynos4210fimdWindow
*)0)->palette)*)0)), }
,
1843 VMSTATE_UINT32(shadow_buf_start, Exynos4210fimdWindow){ .name = ("shadow_buf_start"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, shadow_buf_start) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->shadow_buf_start)*)0)), }
,
1844 VMSTATE_UINT32(shadow_buf_end, Exynos4210fimdWindow){ .name = ("shadow_buf_end"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, shadow_buf_end) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->shadow_buf_end)*)0)), }
,
1845 VMSTATE_UINT32(shadow_buf_size, Exynos4210fimdWindow){ .name = ("shadow_buf_size"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, shadow_buf_size) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->shadow_buf_size)*)0)), }
,
1846 VMSTATE_UINT16(lefttop_x, Exynos4210fimdWindow){ .name = ("lefttop_x"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, lefttop_x) + ((uint16_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->lefttop_x)*)0)), }
,
1847 VMSTATE_UINT16(lefttop_y, Exynos4210fimdWindow){ .name = ("lefttop_y"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, lefttop_y) + ((uint16_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->lefttop_y)*)0)), }
,
1848 VMSTATE_UINT16(rightbot_x, Exynos4210fimdWindow){ .name = ("rightbot_x"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, rightbot_x) + ((uint16_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->rightbot_x)*)0)), }
,
1849 VMSTATE_UINT16(rightbot_y, Exynos4210fimdWindow){ .name = ("rightbot_y"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, rightbot_y) + ((uint16_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->rightbot_y)*)0)), }
,
1850 VMSTATE_UINT32(osdsize, Exynos4210fimdWindow){ .name = ("osdsize"), .version_id = (0), .field_exists = (((
void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, osdsize) + ((uint32_t*)0 - (typeof(((Exynos4210fimdWindow *
)0)->osdsize)*)0)), }
,
1851 VMSTATE_UINT32_ARRAY(alpha_val, Exynos4210fimdWindow, 2){ .name = ("alpha_val"), .version_id = (0), .num = (2), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, alpha_val) + ((uint32_t(*)[2])0 - (typeof(((Exynos4210fimdWindow
*)0)->alpha_val)*)0)), }
,
1852 VMSTATE_UINT16(virtpage_width, Exynos4210fimdWindow){ .name = ("virtpage_width"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, virtpage_width) + ((uint16_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->virtpage_width)*)0)), }
,
1853 VMSTATE_UINT16(virtpage_offsize, Exynos4210fimdWindow){ .name = ("virtpage_offsize"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(uint16_t), .info = &(vmstate_info_uint16
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdWindow
, virtpage_offsize) + ((uint16_t*)0 - (typeof(((Exynos4210fimdWindow
*)0)->virtpage_offsize)*)0)), }
,
1854 VMSTATE_END_OF_LIST(){}
1855 }
1856};
1857
1858static const VMStateDescription exynos4210_fimd_vmstate = {
1859 .name = "exynos4210.fimd",
1860 .version_id = 1,
1861 .minimum_version_id = 1,
1862 .post_load = exynos4210_fimd_load,
1863 .fields = (VMStateField[]) {
1864 VMSTATE_UINT32_ARRAY(vidcon, Exynos4210fimdState, 4){ .name = ("vidcon"), .version_id = (0), .num = (4), .info = &
(vmstate_info_uint32), .size = sizeof(uint32_t), .flags = VMS_ARRAY
, .offset = (__builtin_offsetof(Exynos4210fimdState, vidcon) +
((uint32_t(*)[4])0 - (typeof(((Exynos4210fimdState *)0)->
vidcon)*)0)), }
,
1865 VMSTATE_UINT32_ARRAY(vidtcon, Exynos4210fimdState, 4){ .name = ("vidtcon"), .version_id = (0), .num = (4), .info =
&(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, vidtcon) + ((uint32_t(*)[4])0 - (typeof(((Exynos4210fimdState
*)0)->vidtcon)*)0)), }
,
1866 VMSTATE_UINT32(shadowcon, Exynos4210fimdState){ .name = ("shadowcon"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, shadowcon) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState *
)0)->shadowcon)*)0)), }
,
1867 VMSTATE_UINT32(winchmap, Exynos4210fimdState){ .name = ("winchmap"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, winchmap) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState *
)0)->winchmap)*)0)), }
,
1868 VMSTATE_UINT32_ARRAY(vidintcon, Exynos4210fimdState, 2){ .name = ("vidintcon"), .version_id = (0), .num = (2), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, vidintcon) + ((uint32_t(*)[2])0 - (typeof(((Exynos4210fimdState
*)0)->vidintcon)*)0)), }
,
1869 VMSTATE_UINT32(dithmode, Exynos4210fimdState){ .name = ("dithmode"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, dithmode) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState *
)0)->dithmode)*)0)), }
,
1870 VMSTATE_UINT32_ARRAY(wpalcon, Exynos4210fimdState, 2){ .name = ("wpalcon"), .version_id = (0), .num = (2), .info =
&(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, wpalcon) + ((uint32_t(*)[2])0 - (typeof(((Exynos4210fimdState
*)0)->wpalcon)*)0)), }
,
1871 VMSTATE_UINT32(trigcon, Exynos4210fimdState){ .name = ("trigcon"), .version_id = (0), .field_exists = (((
void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, trigcon) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState *)
0)->trigcon)*)0)), }
,
1872 VMSTATE_UINT32_ARRAY(i80ifcon, Exynos4210fimdState, 4){ .name = ("i80ifcon"), .version_id = (0), .num = (4), .info =
&(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, i80ifcon) + ((uint32_t(*)[4])0 - (typeof(((Exynos4210fimdState
*)0)->i80ifcon)*)0)), }
,
1873 VMSTATE_UINT32(colorgaincon, Exynos4210fimdState){ .name = ("colorgaincon"), .version_id = (0), .field_exists =
(((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, colorgaincon) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState
*)0)->colorgaincon)*)0)), }
,
1874 VMSTATE_UINT32_ARRAY(ldi_cmdcon, Exynos4210fimdState, 2){ .name = ("ldi_cmdcon"), .version_id = (0), .num = (2), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, ldi_cmdcon) + ((uint32_t(*)[2])0 - (typeof(((Exynos4210fimdState
*)0)->ldi_cmdcon)*)0)), }
,
1875 VMSTATE_UINT32_ARRAY(sifccon, Exynos4210fimdState, 3){ .name = ("sifccon"), .version_id = (0), .num = (3), .info =
&(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, sifccon) + ((uint32_t(*)[3])0 - (typeof(((Exynos4210fimdState
*)0)->sifccon)*)0)), }
,
1876 VMSTATE_UINT32_ARRAY(huecoef_cr, Exynos4210fimdState, 4){ .name = ("huecoef_cr"), .version_id = (0), .num = (4), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, huecoef_cr) + ((uint32_t(*)[4])0 - (typeof(((Exynos4210fimdState
*)0)->huecoef_cr)*)0)), }
,
1877 VMSTATE_UINT32_ARRAY(huecoef_cb, Exynos4210fimdState, 4){ .name = ("huecoef_cb"), .version_id = (0), .num = (4), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, huecoef_cb) + ((uint32_t(*)[4])0 - (typeof(((Exynos4210fimdState
*)0)->huecoef_cb)*)0)), }
,
1878 VMSTATE_UINT32(hueoffset, Exynos4210fimdState){ .name = ("hueoffset"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, hueoffset) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState *
)0)->hueoffset)*)0)), }
,
1879 VMSTATE_UINT32_ARRAY(i80ifcmd, Exynos4210fimdState, 12){ .name = ("i80ifcmd"), .version_id = (0), .num = (12), .info
= &(vmstate_info_uint32), .size = sizeof(uint32_t), .flags
= VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState
, i80ifcmd) + ((uint32_t(*)[12])0 - (typeof(((Exynos4210fimdState
*)0)->i80ifcmd)*)0)), }
,
1880 VMSTATE_UINT32(blendcon, Exynos4210fimdState){ .name = ("blendcon"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(Exynos4210fimdState
, blendcon) + ((uint32_t*)0 - (typeof(((Exynos4210fimdState *
)0)->blendcon)*)0)), }
,
1881 VMSTATE_STRUCT_ARRAY(window, Exynos4210fimdState, 5, 1,{ .name = ("window"), .num = (5), .field_exists = (((void*)0)
), .version_id = (1), .vmsd = &(exynos4210_fimd_window_vmstate
), .size = sizeof(Exynos4210fimdWindow), .flags = VMS_STRUCT|
VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState,
window) + ((Exynos4210fimdWindow(*)[5])0 - (typeof(((Exynos4210fimdState
*)0)->window)*)0)),}
1882 exynos4210_fimd_window_vmstate, Exynos4210fimdWindow){ .name = ("window"), .num = (5), .field_exists = (((void*)0)
), .version_id = (1), .vmsd = &(exynos4210_fimd_window_vmstate
), .size = sizeof(Exynos4210fimdWindow), .flags = VMS_STRUCT|
VMS_ARRAY, .offset = (__builtin_offsetof(Exynos4210fimdState,
window) + ((Exynos4210fimdWindow(*)[5])0 - (typeof(((Exynos4210fimdState
*)0)->window)*)0)),}
,
1883 VMSTATE_END_OF_LIST(){}
1884 }
1885};
1886
1887static int exynos4210_fimd_init(SysBusDevice *dev)
1888{
1889 Exynos4210fimdState *s = FROM_SYSBUS(Exynos4210fimdState, dev)( __extension__ ( { char __attribute__((unused)) offset_must_be_zero
[ -__builtin_offsetof(Exynos4210fimdState, busdev)]; ({ const
typeof(((Exynos4210fimdState *) 0)->busdev) *__mptr = (dev
); (Exynos4210fimdState *) ((char *) __mptr - __builtin_offsetof
(Exynos4210fimdState, busdev));});}))
;
1890
1891 s->ifb = NULL((void*)0);
1892
1893 sysbus_init_irq(dev, &s->irq[0]);
1894 sysbus_init_irq(dev, &s->irq[1]);
1895 sysbus_init_irq(dev, &s->irq[2]);
1896
1897 memory_region_init_io(&s->iomem, &exynos4210_fimd_mmio_ops, s,
1898 "exynos4210.fimd", FIMD_REGS_SIZE0x4114);
1899 sysbus_init_mmio(dev, &s->iomem);
1900 s->console = graphic_console_init(exynos4210_fimd_update,
1901 exynos4210_fimd_invalidate, NULL((void*)0), NULL((void*)0), s);
1902
1903 return 0;
1904}
1905
1906static void exynos4210_fimd_class_init(ObjectClass *klass, void *data)
1907{
1908 DeviceClass *dc = DEVICE_CLASS(klass)((DeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("device")))
;
1909 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass)((SysBusDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("sys-bus-device")))
;
1910
1911 dc->vmsd = &exynos4210_fimd_vmstate;
1912 dc->reset = exynos4210_fimd_reset;
1913 k->init = exynos4210_fimd_init;
1914}
1915
1916static TypeInfo exynos4210_fimd_info = {
1917 .name = "exynos4210.fimd",
1918 .parent = TYPE_SYS_BUS_DEVICE"sys-bus-device",
1919 .instance_size = sizeof(Exynos4210fimdState),
1920 .class_init = exynos4210_fimd_class_init,
1921};
1922
1923static void exynos4210_fimd_register_types(void)
1924{
1925 type_register_static(&exynos4210_fimd_info);
1926}
1927
1928type_init(exynos4210_fimd_register_types)static void __attribute__((constructor)) do_qemu_init_exynos4210_fimd_register_types
(void) { register_module_init(exynos4210_fimd_register_types,
MODULE_INIT_QOM); }