Bug Summary

File:hw/usb/hcd-xhci.c
Location:line 1599, column 9
Description:Value stored to 'ep' is never read

Annotated Source Code

1/*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21#include "hw/hw.h"
22#include "qemu/timer.h"
23#include "hw/usb.h"
24#include "hw/pci/pci.h"
25#include "hw/pci/msi.h"
26#include "hw/pci/msix.h"
27#include "trace.h"
28
29//#define DEBUG_XHCI
30//#define DEBUG_DATA
31
32#ifdef DEBUG_XHCI
33#define DPRINTF(...)do {} while (0) fprintf(stderrstderr, __VA_ARGS__)
34#else
35#define DPRINTF(...)do {} while (0) do {} while (0)
36#endif
37#define FIXME(_msg)do { fprintf(stderr, "FIXME %s:%d %s\n", __func__, 37, _msg);
abort(); } while (0)
do { fprintf(stderrstderr, "FIXME %s:%d %s\n", \
38 __func__, __LINE__38, _msg); abort(); } while (0)
39
40#define MAXPORTS_215 15
41#define MAXPORTS_315 15
42
43#define MAXPORTS(15 +15) (MAXPORTS_215+MAXPORTS_315)
44#define MAXSLOTS64 64
45#define MAXINTRS16 16
46
47#define TD_QUEUE24 24
48
49/* Very pessimistic, let's hope it's enough for all cases */
50#define EV_QUEUE(((3*24)+16)*64) (((3*TD_QUEUE24)+16)*MAXSLOTS64)
51/* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
53#define ER_FULL_HACK
54
55#define LEN_CAP0x40 0x40
56#define LEN_OPER(0x400 + 0x10 * (15 +15)) (0x400 + 0x10 * MAXPORTS(15 +15))
57#define LEN_RUNTIME((16 + 1) * 0x20) ((MAXINTRS16 + 1) * 0x20)
58#define LEN_DOORBELL((64 + 1) * 0x20) ((MAXSLOTS64 + 1) * 0x20)
59
60#define OFF_OPER0x40 LEN_CAP0x40
61#define OFF_RUNTIME0x1000 0x1000
62#define OFF_DOORBELL0x2000 0x2000
63#define OFF_MSIX_TABLE0x3000 0x3000
64#define OFF_MSIX_PBA0x3800 0x3800
65/* must be power of 2 */
66#define LEN_REGS0x4000 0x4000
67
68#if (OFF_OPER0x40 + LEN_OPER(0x400 + 0x10 * (15 +15))) > OFF_RUNTIME0x1000
69#error Increase OFF_RUNTIME0x1000
70#endif
71#if (OFF_RUNTIME0x1000 + LEN_RUNTIME((16 + 1) * 0x20)) > OFF_DOORBELL0x2000
72#error Increase OFF_DOORBELL0x2000
73#endif
74#if (OFF_DOORBELL0x2000 + LEN_DOORBELL((64 + 1) * 0x20)) > LEN_REGS0x4000
75# error Increase LEN_REGS0x4000
76#endif
77
78/* bit definitions */
79#define USBCMD_RS(1<<0) (1<<0)
80#define USBCMD_HCRST(1<<1) (1<<1)
81#define USBCMD_INTE(1<<2) (1<<2)
82#define USBCMD_HSEE(1<<3) (1<<3)
83#define USBCMD_LHCRST(1<<7) (1<<7)
84#define USBCMD_CSS(1<<8) (1<<8)
85#define USBCMD_CRS(1<<9) (1<<9)
86#define USBCMD_EWE(1<<10) (1<<10)
87#define USBCMD_EU3S(1<<11) (1<<11)
88
89#define USBSTS_HCH(1<<0) (1<<0)
90#define USBSTS_HSE(1<<2) (1<<2)
91#define USBSTS_EINT(1<<3) (1<<3)
92#define USBSTS_PCD(1<<4) (1<<4)
93#define USBSTS_SSS(1<<8) (1<<8)
94#define USBSTS_RSS(1<<9) (1<<9)
95#define USBSTS_SRE(1<<10) (1<<10)
96#define USBSTS_CNR(1<<11) (1<<11)
97#define USBSTS_HCE(1<<12) (1<<12)
98
99
100#define PORTSC_CCS(1<<0) (1<<0)
101#define PORTSC_PED(1<<1) (1<<1)
102#define PORTSC_OCA(1<<3) (1<<3)
103#define PORTSC_PR(1<<4) (1<<4)
104#define PORTSC_PLS_SHIFT5 5
105#define PORTSC_PLS_MASK0xf 0xf
106#define PORTSC_PP(1<<9) (1<<9)
107#define PORTSC_SPEED_SHIFT10 10
108#define PORTSC_SPEED_MASK0xf 0xf
109#define PORTSC_SPEED_FULL(1<<10) (1<<10)
110#define PORTSC_SPEED_LOW(2<<10) (2<<10)
111#define PORTSC_SPEED_HIGH(3<<10) (3<<10)
112#define PORTSC_SPEED_SUPER(4<<10) (4<<10)
113#define PORTSC_PIC_SHIFT14 14
114#define PORTSC_PIC_MASK0x3 0x3
115#define PORTSC_LWS(1<<16) (1<<16)
116#define PORTSC_CSC(1<<17) (1<<17)
117#define PORTSC_PEC(1<<18) (1<<18)
118#define PORTSC_WRC(1<<19) (1<<19)
119#define PORTSC_OCC(1<<20) (1<<20)
120#define PORTSC_PRC(1<<21) (1<<21)
121#define PORTSC_PLC(1<<22) (1<<22)
122#define PORTSC_CEC(1<<23) (1<<23)
123#define PORTSC_CAS(1<<24) (1<<24)
124#define PORTSC_WCE(1<<25) (1<<25)
125#define PORTSC_WDE(1<<26) (1<<26)
126#define PORTSC_WOE(1<<27) (1<<27)
127#define PORTSC_DR(1<<30) (1<<30)
128#define PORTSC_WPR(1<<31) (1<<31)
129
130#define CRCR_RCS(1<<0) (1<<0)
131#define CRCR_CS(1<<1) (1<<1)
132#define CRCR_CA(1<<2) (1<<2)
133#define CRCR_CRR(1<<3) (1<<3)
134
135#define IMAN_IP(1<<0) (1<<0)
136#define IMAN_IE(1<<1) (1<<1)
137
138#define ERDP_EHB(1<<3) (1<<3)
139
140#define TRB_SIZE16 16
141typedef struct XHCITRB {
142 uint64_t parameter;
143 uint32_t status;
144 uint32_t control;
145 dma_addr_t addr;
146 bool_Bool ccs;
147} XHCITRB;
148
149enum {
150 PLS_U0 = 0,
151 PLS_U1 = 1,
152 PLS_U2 = 2,
153 PLS_U3 = 3,
154 PLS_DISABLED = 4,
155 PLS_RX_DETECT = 5,
156 PLS_INACTIVE = 6,
157 PLS_POLLING = 7,
158 PLS_RECOVERY = 8,
159 PLS_HOT_RESET = 9,
160 PLS_COMPILANCE_MODE = 10,
161 PLS_TEST_MODE = 11,
162 PLS_RESUME = 15,
163};
164
165typedef enum TRBType {
166 TRB_RESERVED = 0,
167 TR_NORMAL,
168 TR_SETUP,
169 TR_DATA,
170 TR_STATUS,
171 TR_ISOCH,
172 TR_LINK,
173 TR_EVDATA,
174 TR_NOOP,
175 CR_ENABLE_SLOT,
176 CR_DISABLE_SLOT,
177 CR_ADDRESS_DEVICE,
178 CR_CONFIGURE_ENDPOINT,
179 CR_EVALUATE_CONTEXT,
180 CR_RESET_ENDPOINT,
181 CR_STOP_ENDPOINT,
182 CR_SET_TR_DEQUEUE,
183 CR_RESET_DEVICE,
184 CR_FORCE_EVENT,
185 CR_NEGOTIATE_BW,
186 CR_SET_LATENCY_TOLERANCE,
187 CR_GET_PORT_BANDWIDTH,
188 CR_FORCE_HEADER,
189 CR_NOOP,
190 ER_TRANSFER = 32,
191 ER_COMMAND_COMPLETE,
192 ER_PORT_STATUS_CHANGE,
193 ER_BANDWIDTH_REQUEST,
194 ER_DOORBELL,
195 ER_HOST_CONTROLLER,
196 ER_DEVICE_NOTIFICATION,
197 ER_MFINDEX_WRAP,
198 /* vendor specific bits */
199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
202} TRBType;
203
204#define CR_LINKTR_LINK TR_LINK
205
206typedef enum TRBCCode {
207 CC_INVALID = 0,
208 CC_SUCCESS,
209 CC_DATA_BUFFER_ERROR,
210 CC_BABBLE_DETECTED,
211 CC_USB_TRANSACTION_ERROR,
212 CC_TRB_ERROR,
213 CC_STALL_ERROR,
214 CC_RESOURCE_ERROR,
215 CC_BANDWIDTH_ERROR,
216 CC_NO_SLOTS_ERROR,
217 CC_INVALID_STREAM_TYPE_ERROR,
218 CC_SLOT_NOT_ENABLED_ERROR,
219 CC_EP_NOT_ENABLED_ERROR,
220 CC_SHORT_PACKET,
221 CC_RING_UNDERRUN,
222 CC_RING_OVERRUN,
223 CC_VF_ER_FULL,
224 CC_PARAMETER_ERROR,
225 CC_BANDWIDTH_OVERRUN,
226 CC_CONTEXT_STATE_ERROR,
227 CC_NO_PING_RESPONSE_ERROR,
228 CC_EVENT_RING_FULL_ERROR,
229 CC_INCOMPATIBLE_DEVICE_ERROR,
230 CC_MISSED_SERVICE_ERROR,
231 CC_COMMAND_RING_STOPPED,
232 CC_COMMAND_ABORTED,
233 CC_STOPPED,
234 CC_STOPPED_LENGTH_INVALID,
235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
236 CC_ISOCH_BUFFER_OVERRUN = 31,
237 CC_EVENT_LOST_ERROR,
238 CC_UNDEFINED_ERROR,
239 CC_INVALID_STREAM_ID_ERROR,
240 CC_SECONDARY_BANDWIDTH_ERROR,
241 CC_SPLIT_TRANSACTION_ERROR
242} TRBCCode;
243
244#define TRB_C(1<<0) (1<<0)
245#define TRB_TYPE_SHIFT10 10
246#define TRB_TYPE_MASK0x3f 0x3f
247#define TRB_TYPE(t)(((t).control >> 10) & 0x3f) (((t).control >> TRB_TYPE_SHIFT10) & TRB_TYPE_MASK0x3f)
248
249#define TRB_EV_ED(1<<2) (1<<2)
250
251#define TRB_TR_ENT(1<<1) (1<<1)
252#define TRB_TR_ISP(1<<2) (1<<2)
253#define TRB_TR_NS(1<<3) (1<<3)
254#define TRB_TR_CH(1<<4) (1<<4)
255#define TRB_TR_IOC(1<<5) (1<<5)
256#define TRB_TR_IDT(1<<6) (1<<6)
257#define TRB_TR_TBC_SHIFT7 7
258#define TRB_TR_TBC_MASK0x3 0x3
259#define TRB_TR_BEI(1<<9) (1<<9)
260#define TRB_TR_TLBPC_SHIFT16 16
261#define TRB_TR_TLBPC_MASK0xf 0xf
262#define TRB_TR_FRAMEID_SHIFT20 20
263#define TRB_TR_FRAMEID_MASK0x7ff 0x7ff
264#define TRB_TR_SIA(1<<31) (1<<31)
265
266#define TRB_TR_DIR(1<<16) (1<<16)
267
268#define TRB_CR_SLOTID_SHIFT24 24
269#define TRB_CR_SLOTID_MASK0xff 0xff
270#define TRB_CR_EPID_SHIFT16 16
271#define TRB_CR_EPID_MASK0x1f 0x1f
272
273#define TRB_CR_BSR(1<<9) (1<<9)
274#define TRB_CR_DC(1<<9) (1<<9)
275
276#define TRB_LK_TC(1<<1) (1<<1)
277
278#define TRB_INTR_SHIFT22 22
279#define TRB_INTR_MASK0x3ff 0x3ff
280#define TRB_INTR(t)(((t).status >> 22) & 0x3ff) (((t).status >> TRB_INTR_SHIFT22) & TRB_INTR_MASK0x3ff)
281
282#define EP_TYPE_MASK0x7 0x7
283#define EP_TYPE_SHIFT3 3
284
285#define EP_STATE_MASK0x7 0x7
286#define EP_DISABLED(0<<0) (0<<0)
287#define EP_RUNNING(1<<0) (1<<0)
288#define EP_HALTED(2<<0) (2<<0)
289#define EP_STOPPED(3<<0) (3<<0)
290#define EP_ERROR(4<<0) (4<<0)
291
292#define SLOT_STATE_MASK0x1f 0x1f
293#define SLOT_STATE_SHIFT27 27
294#define SLOT_STATE(s)(((s)>>27)&0x1f) (((s)>>SLOT_STATE_SHIFT27)&SLOT_STATE_MASK0x1f)
295#define SLOT_ENABLED0 0
296#define SLOT_DEFAULT1 1
297#define SLOT_ADDRESSED2 2
298#define SLOT_CONFIGURED3 3
299
300#define SLOT_CONTEXT_ENTRIES_MASK0x1f 0x1f
301#define SLOT_CONTEXT_ENTRIES_SHIFT27 27
302
303typedef struct XHCIState XHCIState;
304typedef struct XHCIStreamContext XHCIStreamContext;
305typedef struct XHCIEPContext XHCIEPContext;
306
307#define get_field(data, field)(((data) >> field_SHIFT) & field_MASK) \
308 (((data) >> field##_SHIFT) & field##_MASK)
309
310#define set_field(data, newval, field)do { uint32_t val = *data; val &= ~( field_MASK << field_SHIFT
); val |= ((newval) & field_MASK) << field_SHIFT; *
data = val; } while (0)
do { \
311 uint32_t val = *data; \
312 val &= ~(field##_MASK << field##_SHIFT); \
313 val |= ((newval) & field##_MASK) << field##_SHIFT; \
314 *data = val; \
315 } while (0)
316
317typedef enum EPType {
318 ET_INVALID = 0,
319 ET_ISO_OUT,
320 ET_BULK_OUT,
321 ET_INTR_OUT,
322 ET_CONTROL,
323 ET_ISO_IN,
324 ET_BULK_IN,
325 ET_INTR_IN,
326} EPType;
327
328typedef struct XHCIRing {
329 dma_addr_t dequeue;
330 bool_Bool ccs;
331} XHCIRing;
332
333typedef struct XHCIPort {
334 XHCIState *xhci;
335 uint32_t portsc;
336 uint32_t portnr;
337 USBPort *uport;
338 uint32_t speedmask;
339 char name[16];
340 MemoryRegion mem;
341} XHCIPort;
342
343typedef struct XHCITransfer {
344 XHCIState *xhci;
345 USBPacket packet;
346 QEMUSGList sgl;
347 bool_Bool running_async;
348 bool_Bool running_retry;
349 bool_Bool complete;
350 bool_Bool int_req;
351 unsigned int iso_pkts;
352 unsigned int slotid;
353 unsigned int epid;
354 unsigned int streamid;
355 bool_Bool in_xfer;
356 bool_Bool iso_xfer;
357 bool_Bool timed_xfer;
358
359 unsigned int trb_count;
360 unsigned int trb_alloced;
361 XHCITRB *trbs;
362
363 TRBCCode status;
364
365 unsigned int pkts;
366 unsigned int pktsize;
367 unsigned int cur_pkt;
368
369 uint64_t mfindex_kick;
370} XHCITransfer;
371
372struct XHCIStreamContext {
373 dma_addr_t pctx;
374 unsigned int sct;
375 XHCIRing ring;
376};
377
378struct XHCIEPContext {
379 XHCIState *xhci;
380 unsigned int slotid;
381 unsigned int epid;
382
383 XHCIRing ring;
384 unsigned int next_xfer;
385 unsigned int comp_xfer;
386 XHCITransfer transfers[TD_QUEUE24];
387 XHCITransfer *retry;
388 EPType type;
389 dma_addr_t pctx;
390 unsigned int max_psize;
391 uint32_t state;
392
393 /* streams */
394 unsigned int max_pstreams;
395 bool_Bool lsa;
396 unsigned int nr_pstreams;
397 XHCIStreamContext *pstreams;
398
399 /* iso xfer scheduling */
400 unsigned int interval;
401 int64_t mfindex_last;
402 QEMUTimer *kick_timer;
403};
404
405typedef struct XHCISlot {
406 bool_Bool enabled;
407 bool_Bool addressed;
408 dma_addr_t ctx;
409 USBPort *uport;
410 XHCIEPContext * eps[31];
411} XHCISlot;
412
413typedef struct XHCIEvent {
414 TRBType type;
415 TRBCCode ccode;
416 uint64_t ptr;
417 uint32_t length;
418 uint32_t flags;
419 uint8_t slotid;
420 uint8_t epid;
421} XHCIEvent;
422
423typedef struct XHCIInterrupter {
424 uint32_t iman;
425 uint32_t imod;
426 uint32_t erstsz;
427 uint32_t erstba_low;
428 uint32_t erstba_high;
429 uint32_t erdp_low;
430 uint32_t erdp_high;
431
432 bool_Bool msix_used, er_pcs, er_full;
433
434 dma_addr_t er_start;
435 uint32_t er_size;
436 unsigned int er_ep_idx;
437
438 XHCIEvent ev_buffer[EV_QUEUE(((3*24)+16)*64)];
439 unsigned int ev_buffer_put;
440 unsigned int ev_buffer_get;
441
442} XHCIInterrupter;
443
444struct XHCIState {
445 /*< private >*/
446 PCIDevice parent_obj;
447 /*< public >*/
448
449 USBBus bus;
450 MemoryRegion mem;
451 MemoryRegion mem_cap;
452 MemoryRegion mem_oper;
453 MemoryRegion mem_runtime;
454 MemoryRegion mem_doorbell;
455
456 /* properties */
457 uint32_t numports_2;
458 uint32_t numports_3;
459 uint32_t numintrs;
460 uint32_t numslots;
461 uint32_t flags;
462
463 /* Operational Registers */
464 uint32_t usbcmd;
465 uint32_t usbsts;
466 uint32_t dnctrl;
467 uint32_t crcr_low;
468 uint32_t crcr_high;
469 uint32_t dcbaap_low;
470 uint32_t dcbaap_high;
471 uint32_t config;
472
473 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)(((15) > (15)) ? (15) : (15))];
474 XHCIPort ports[MAXPORTS(15 +15)];
475 XHCISlot slots[MAXSLOTS64];
476 uint32_t numports;
477
478 /* Runtime Registers */
479 int64_t mfindex_start;
480 QEMUTimer *mfwrap_timer;
481 XHCIInterrupter intr[MAXINTRS16];
482
483 XHCIRing cmd_ring;
484};
485
486#define TYPE_XHCI"nec-usb-xhci" "nec-usb-xhci"
487
488#define XHCI(obj)((XHCIState *)object_dynamic_cast_assert(((Object *)((obj))),
("nec-usb-xhci"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 488, __func__))
\
489 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)((XHCIState *)object_dynamic_cast_assert(((Object *)((obj))),
("nec-usb-xhci"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 489, __func__))
490
491typedef struct XHCIEvRingSeg {
492 uint32_t addr_low;
493 uint32_t addr_high;
494 uint32_t size;
495 uint32_t rsvd;
496} XHCIEvRingSeg;
497
498enum xhci_flags {
499 XHCI_FLAG_USE_MSI = 1,
500 XHCI_FLAG_USE_MSI_X,
501};
502
503static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
504 unsigned int epid, unsigned int streamid);
505static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
506 unsigned int epid);
507static void xhci_xfer_report(XHCITransfer *xfer);
508static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
509static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
510static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci,
511 unsigned int slotid, unsigned int epid);
512
513static const char *TRBType_names[] = {
514 [TRB_RESERVED] = "TRB_RESERVED",
515 [TR_NORMAL] = "TR_NORMAL",
516 [TR_SETUP] = "TR_SETUP",
517 [TR_DATA] = "TR_DATA",
518 [TR_STATUS] = "TR_STATUS",
519 [TR_ISOCH] = "TR_ISOCH",
520 [TR_LINK] = "TR_LINK",
521 [TR_EVDATA] = "TR_EVDATA",
522 [TR_NOOP] = "TR_NOOP",
523 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
524 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
525 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
526 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
527 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
528 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
529 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
530 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
531 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
532 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
533 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
534 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
535 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
536 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
537 [CR_NOOP] = "CR_NOOP",
538 [ER_TRANSFER] = "ER_TRANSFER",
539 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
540 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
541 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
542 [ER_DOORBELL] = "ER_DOORBELL",
543 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
544 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
545 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
546 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
547 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
548 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
549};
550
551static const char *TRBCCode_names[] = {
552 [CC_INVALID] = "CC_INVALID",
553 [CC_SUCCESS] = "CC_SUCCESS",
554 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
555 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
556 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
557 [CC_TRB_ERROR] = "CC_TRB_ERROR",
558 [CC_STALL_ERROR] = "CC_STALL_ERROR",
559 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
560 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
561 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
562 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
563 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
564 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
565 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
566 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
567 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
568 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
569 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
570 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
571 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
572 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
573 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
574 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
575 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
576 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
577 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
578 [CC_STOPPED] = "CC_STOPPED",
579 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
580 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
581 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
582 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
583 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
584 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
585 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
586 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
587 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
588};
589
590static const char *ep_state_names[] = {
591 [EP_DISABLED(0<<0)] = "disabled",
592 [EP_RUNNING(1<<0)] = "running",
593 [EP_HALTED(2<<0)] = "halted",
594 [EP_STOPPED(3<<0)] = "stopped",
595 [EP_ERROR(4<<0)] = "error",
596};
597
598static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
599{
600 if (index >= llen || list[index] == NULL((void*)0)) {
601 return "???";
602 }
603 return list[index];
604}
605
606static const char *trb_name(XHCITRB *trb)
607{
608 return lookup_name(TRB_TYPE(*trb)(((*trb).control >> 10) & 0x3f), TRBType_names,
609 ARRAY_SIZE(TRBType_names)(sizeof(TRBType_names) / sizeof((TRBType_names)[0])));
610}
611
612static const char *event_name(XHCIEvent *event)
613{
614 return lookup_name(event->ccode, TRBCCode_names,
615 ARRAY_SIZE(TRBCCode_names)(sizeof(TRBCCode_names) / sizeof((TRBCCode_names)[0])));
616}
617
618static const char *ep_state_name(uint32_t state)
619{
620 return lookup_name(state, ep_state_names,
621 ARRAY_SIZE(ep_state_names)(sizeof(ep_state_names) / sizeof((ep_state_names)[0])));
622}
623
624static uint64_t xhci_mfindex_get(XHCIState *xhci)
625{
626 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
627 return (now - xhci->mfindex_start) / 125000;
628}
629
630static void xhci_mfwrap_update(XHCIState *xhci)
631{
632 const uint32_t bits = USBCMD_RS(1<<0) | USBCMD_EWE(1<<10);
633 uint32_t mfindex, left;
634 int64_t now;
635
636 if ((xhci->usbcmd & bits) == bits) {
637 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
638 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
639 left = 0x4000 - mfindex;
640 timer_mod(xhci->mfwrap_timer, now + left * 125000);
641 } else {
642 timer_del(xhci->mfwrap_timer);
643 }
644}
645
646static void xhci_mfwrap_timer(void *opaque)
647{
648 XHCIState *xhci = opaque;
649 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
650
651 xhci_event(xhci, &wrap, 0);
652 xhci_mfwrap_update(xhci);
653}
654
655static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
656{
657 if (sizeof(dma_addr_t) == 4) {
658 return low;
659 } else {
660 return low | (((dma_addr_t)high << 16) << 16);
661 }
662}
663
664static inline dma_addr_t xhci_mask64(uint64_t addr)
665{
666 if (sizeof(dma_addr_t) == 4) {
667 return addr & 0xffffffff;
668 } else {
669 return addr;
670 }
671}
672
673static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
674 uint32_t *buf, size_t len)
675{
676 int i;
677
678 assert((len % sizeof(uint32_t)) == 0)(((len % sizeof(uint32_t)) == 0) ? (void) (0) : __assert_fail
("(len % sizeof(uint32_t)) == 0", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 678, __PRETTY_FUNCTION__))
;
679
680 pci_dma_read(PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 680, __func__))
, addr, buf, len);
681
682 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
683 buf[i] = le32_to_cpu(buf[i]);
684 }
685}
686
687static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
688 uint32_t *buf, size_t len)
689{
690 int i;
691 uint32_t tmp[len / sizeof(uint32_t)];
692
693 assert((len % sizeof(uint32_t)) == 0)(((len % sizeof(uint32_t)) == 0) ? (void) (0) : __assert_fail
("(len % sizeof(uint32_t)) == 0", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 693, __PRETTY_FUNCTION__))
;
694
695 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
696 tmp[i] = cpu_to_le32(buf[i]);
697 }
698 pci_dma_write(PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 698, __func__))
, addr, tmp, len);
699}
700
701static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
702{
703 int index;
704
705 if (!uport->dev) {
706 return NULL((void*)0);
707 }
708 switch (uport->dev->speed) {
709 case USB_SPEED_LOW0:
710 case USB_SPEED_FULL1:
711 case USB_SPEED_HIGH2:
712 index = uport->index;
713 break;
714 case USB_SPEED_SUPER3:
715 index = uport->index + xhci->numports_2;
716 break;
717 default:
718 return NULL((void*)0);
719 }
720 return &xhci->ports[index];
721}
722
723static void xhci_intx_update(XHCIState *xhci)
724{
725 PCIDevice *pci_dev = PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 725, __func__))
;
726 int level = 0;
727
728 if (msix_enabled(pci_dev) ||
729 msi_enabled(pci_dev)) {
730 return;
731 }
732
733 if (xhci->intr[0].iman & IMAN_IP(1<<0) &&
734 xhci->intr[0].iman & IMAN_IE(1<<1) &&
735 xhci->usbcmd & USBCMD_INTE(1<<2)) {
736 level = 1;
737 }
738
739 trace_usb_xhci_irq_intx(level);
740 pci_set_irq(pci_dev, level);
741}
742
743static void xhci_msix_update(XHCIState *xhci, int v)
744{
745 PCIDevice *pci_dev = PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 745, __func__))
;
746 bool_Bool enabled;
747
748 if (!msix_enabled(pci_dev)) {
749 return;
750 }
751
752 enabled = xhci->intr[v].iman & IMAN_IE(1<<1);
753 if (enabled == xhci->intr[v].msix_used) {
754 return;
755 }
756
757 if (enabled) {
758 trace_usb_xhci_irq_msix_use(v);
759 msix_vector_use(pci_dev, v);
760 xhci->intr[v].msix_used = true1;
761 } else {
762 trace_usb_xhci_irq_msix_unuse(v);
763 msix_vector_unuse(pci_dev, v);
764 xhci->intr[v].msix_used = false0;
765 }
766}
767
768static void xhci_intr_raise(XHCIState *xhci, int v)
769{
770 PCIDevice *pci_dev = PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 770, __func__))
;
771
772 xhci->intr[v].erdp_low |= ERDP_EHB(1<<3);
773 xhci->intr[v].iman |= IMAN_IP(1<<0);
774 xhci->usbsts |= USBSTS_EINT(1<<3);
775
776 if (!(xhci->intr[v].iman & IMAN_IE(1<<1))) {
777 return;
778 }
779
780 if (!(xhci->usbcmd & USBCMD_INTE(1<<2))) {
781 return;
782 }
783
784 if (msix_enabled(pci_dev)) {
785 trace_usb_xhci_irq_msix(v);
786 msix_notify(pci_dev, v);
787 return;
788 }
789
790 if (msi_enabled(pci_dev)) {
791 trace_usb_xhci_irq_msi(v);
792 msi_notify(pci_dev, v);
793 return;
794 }
795
796 if (v == 0) {
797 trace_usb_xhci_irq_intx(1);
798 pci_irq_assert(pci_dev);
799 }
800}
801
802static inline int xhci_running(XHCIState *xhci)
803{
804 return !(xhci->usbsts & USBSTS_HCH(1<<0)) && !xhci->intr[0].er_full;
805}
806
807static void xhci_die(XHCIState *xhci)
808{
809 xhci->usbsts |= USBSTS_HCE(1<<12);
810 fprintf(stderrstderr, "xhci: asserted controller error\n");
811}
812
813static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
814{
815 PCIDevice *pci_dev = PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 815, __func__))
;
816 XHCIInterrupter *intr = &xhci->intr[v];
817 XHCITRB ev_trb;
818 dma_addr_t addr;
819
820 ev_trb.parameter = cpu_to_le64(event->ptr);
821 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
822 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
823 event->flags | (event->type << TRB_TYPE_SHIFT10);
824 if (intr->er_pcs) {
825 ev_trb.control |= TRB_C(1<<0);
826 }
827 ev_trb.control = cpu_to_le32(ev_trb.control);
828
829 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
830 event_name(event), ev_trb.parameter,
831 ev_trb.status, ev_trb.control);
832
833 addr = intr->er_start + TRB_SIZE16*intr->er_ep_idx;
834 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE16);
835
836 intr->er_ep_idx++;
837 if (intr->er_ep_idx >= intr->er_size) {
838 intr->er_ep_idx = 0;
839 intr->er_pcs = !intr->er_pcs;
840 }
841}
842
843static void xhci_events_update(XHCIState *xhci, int v)
844{
845 XHCIInterrupter *intr = &xhci->intr[v];
846 dma_addr_t erdp;
847 unsigned int dp_idx;
848 bool_Bool do_irq = 0;
849
850 if (xhci->usbsts & USBSTS_HCH(1<<0)) {
851 return;
852 }
853
854 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
855 if (erdp < intr->er_start ||
856 erdp >= (intr->er_start + TRB_SIZE16*intr->er_size)) {
857 fprintf(stderrstderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"%" "l" "x""\n", erdp);
858 fprintf(stderrstderr, "xhci: ER[%d] at "DMA_ADDR_FMT"%" "l" "x"" len %d\n",
859 v, intr->er_start, intr->er_size);
860 xhci_die(xhci);
861 return;
862 }
863 dp_idx = (erdp - intr->er_start) / TRB_SIZE16;
864 assert(dp_idx < intr->er_size)((dp_idx < intr->er_size) ? (void) (0) : __assert_fail (
"dp_idx < intr->er_size", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 864, __PRETTY_FUNCTION__))
;
865
866 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
867 * deadlocks when the ER is full. Hack it by holding off events until
868 * the driver decides to free at least half of the ring */
869 if (intr->er_full) {
870 int er_free = dp_idx - intr->er_ep_idx;
871 if (er_free <= 0) {
872 er_free += intr->er_size;
873 }
874 if (er_free < (intr->er_size/2)) {
875 DPRINTF("xhci_events_update(): event ring still "do {} while (0)
876 "more than half full (hack)\n")do {} while (0);
877 return;
878 }
879 }
880
881 while (intr->ev_buffer_put != intr->ev_buffer_get) {
882 assert(intr->er_full)((intr->er_full) ? (void) (0) : __assert_fail ("intr->er_full"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 882
, __PRETTY_FUNCTION__))
;
883 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) {
884 DPRINTF("xhci_events_update(): event ring full again\n")do {} while (0);
885#ifndef ER_FULL_HACK
886 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
887 xhci_write_event(xhci, &full, v);
888#endif
889 do_irq = 1;
890 break;
891 }
892 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get];
893 xhci_write_event(xhci, event, v);
894 intr->ev_buffer_get++;
895 do_irq = 1;
896 if (intr->ev_buffer_get == EV_QUEUE(((3*24)+16)*64)) {
897 intr->ev_buffer_get = 0;
898 }
899 }
900
901 if (do_irq) {
902 xhci_intr_raise(xhci, v);
903 }
904
905 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) {
906 DPRINTF("xhci_events_update(): event ring no longer full\n")do {} while (0);
907 intr->er_full = 0;
908 }
909}
910
911static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
912{
913 XHCIInterrupter *intr;
914 dma_addr_t erdp;
915 unsigned int dp_idx;
916
917 if (v >= xhci->numintrs) {
918 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs)do {} while (0);
919 return;
920 }
921 intr = &xhci->intr[v];
922
923 if (intr->er_full) {
924 DPRINTF("xhci_event(): ER full, queueing\n")do {} while (0);
925 if (((intr->ev_buffer_put+1) % EV_QUEUE(((3*24)+16)*64)) == intr->ev_buffer_get) {
926 fprintf(stderrstderr, "xhci: event queue full, dropping event!\n");
927 return;
928 }
929 intr->ev_buffer[intr->ev_buffer_put++] = *event;
930 if (intr->ev_buffer_put == EV_QUEUE(((3*24)+16)*64)) {
931 intr->ev_buffer_put = 0;
932 }
933 return;
934 }
935
936 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
937 if (erdp < intr->er_start ||
938 erdp >= (intr->er_start + TRB_SIZE16*intr->er_size)) {
939 fprintf(stderrstderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"%" "l" "x""\n", erdp);
940 fprintf(stderrstderr, "xhci: ER[%d] at "DMA_ADDR_FMT"%" "l" "x"" len %d\n",
941 v, intr->er_start, intr->er_size);
942 xhci_die(xhci);
943 return;
944 }
945
946 dp_idx = (erdp - intr->er_start) / TRB_SIZE16;
947 assert(dp_idx < intr->er_size)((dp_idx < intr->er_size) ? (void) (0) : __assert_fail (
"dp_idx < intr->er_size", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 947, __PRETTY_FUNCTION__))
;
948
949 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) {
950 DPRINTF("xhci_event(): ER full, queueing\n")do {} while (0);
951#ifndef ER_FULL_HACK
952 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
953 xhci_write_event(xhci, &full);
954#endif
955 intr->er_full = 1;
956 if (((intr->ev_buffer_put+1) % EV_QUEUE(((3*24)+16)*64)) == intr->ev_buffer_get) {
957 fprintf(stderrstderr, "xhci: event queue full, dropping event!\n");
958 return;
959 }
960 intr->ev_buffer[intr->ev_buffer_put++] = *event;
961 if (intr->ev_buffer_put == EV_QUEUE(((3*24)+16)*64)) {
962 intr->ev_buffer_put = 0;
963 }
964 } else {
965 xhci_write_event(xhci, event, v);
966 }
967
968 xhci_intr_raise(xhci, v);
969}
970
971static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
972 dma_addr_t base)
973{
974 ring->dequeue = base;
975 ring->ccs = 1;
976}
977
978static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
979 dma_addr_t *addr)
980{
981 PCIDevice *pci_dev = PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 981, __func__))
;
982
983 while (1) {
984 TRBType type;
985 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE16);
986 trb->addr = ring->dequeue;
987 trb->ccs = ring->ccs;
988 le64_to_cpus(&trb->parameter);
989 le32_to_cpus(&trb->status);
990 le32_to_cpus(&trb->control);
991
992 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
993 trb->parameter, trb->status, trb->control);
994
995 if ((trb->control & TRB_C(1<<0)) != ring->ccs) {
996 return 0;
997 }
998
999 type = TRB_TYPE(*trb)(((*trb).control >> 10) & 0x3f);
1000
1001 if (type != TR_LINK) {
1002 if (addr) {
1003 *addr = ring->dequeue;
1004 }
1005 ring->dequeue += TRB_SIZE16;
1006 return type;
1007 } else {
1008 ring->dequeue = xhci_mask64(trb->parameter);
1009 if (trb->control & TRB_LK_TC(1<<1)) {
1010 ring->ccs = !ring->ccs;
1011 }
1012 }
1013 }
1014}
1015
1016static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
1017{
1018 PCIDevice *pci_dev = PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1018, __func__))
;
1019 XHCITRB trb;
1020 int length = 0;
1021 dma_addr_t dequeue = ring->dequeue;
1022 bool_Bool ccs = ring->ccs;
1023 /* hack to bundle together the two/three TDs that make a setup transfer */
1024 bool_Bool control_td_set = 0;
1025
1026 while (1) {
1027 TRBType type;
1028 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE16);
1029 le64_to_cpus(&trb.parameter);
1030 le32_to_cpus(&trb.status);
1031 le32_to_cpus(&trb.control);
1032
1033 if ((trb.control & TRB_C(1<<0)) != ccs) {
1034 return -length;
1035 }
1036
1037 type = TRB_TYPE(trb)(((trb).control >> 10) & 0x3f);
1038
1039 if (type == TR_LINK) {
1040 dequeue = xhci_mask64(trb.parameter);
1041 if (trb.control & TRB_LK_TC(1<<1)) {
1042 ccs = !ccs;
1043 }
1044 continue;
1045 }
1046
1047 length += 1;
1048 dequeue += TRB_SIZE16;
1049
1050 if (type == TR_SETUP) {
1051 control_td_set = 1;
1052 } else if (type == TR_STATUS) {
1053 control_td_set = 0;
1054 }
1055
1056 if (!control_td_set && !(trb.control & TRB_TR_CH(1<<4))) {
1057 return length;
1058 }
1059 }
1060}
1061
1062static void xhci_er_reset(XHCIState *xhci, int v)
1063{
1064 XHCIInterrupter *intr = &xhci->intr[v];
1065 XHCIEvRingSeg seg;
1066
1067 if (intr->erstsz == 0) {
1068 /* disabled */
1069 intr->er_start = 0;
1070 intr->er_size = 0;
1071 return;
1072 }
1073 /* cache the (sole) event ring segment location */
1074 if (intr->erstsz != 1) {
1075 fprintf(stderrstderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
1076 xhci_die(xhci);
1077 return;
1078 }
1079 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
1080 pci_dma_read(PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1080, __func__))
, erstba, &seg, sizeof(seg));
1081 le32_to_cpus(&seg.addr_low);
1082 le32_to_cpus(&seg.addr_high);
1083 le32_to_cpus(&seg.size);
1084 if (seg.size < 16 || seg.size > 4096) {
1085 fprintf(stderrstderr, "xhci: invalid value for segment size: %d\n", seg.size);
1086 xhci_die(xhci);
1087 return;
1088 }
1089 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
1090 intr->er_size = seg.size;
1091
1092 intr->er_ep_idx = 0;
1093 intr->er_pcs = 1;
1094 intr->er_full = 0;
1095
1096 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",do {} while (0)
1097 v, intr->er_start, intr->er_size)do {} while (0);
1098}
1099
1100static void xhci_run(XHCIState *xhci)
1101{
1102 trace_usb_xhci_run();
1103 xhci->usbsts &= ~USBSTS_HCH(1<<0);
1104 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1105}
1106
1107static void xhci_stop(XHCIState *xhci)
1108{
1109 trace_usb_xhci_stop();
1110 xhci->usbsts |= USBSTS_HCH(1<<0);
1111 xhci->crcr_low &= ~CRCR_CRR(1<<3);
1112}
1113
1114static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
1115 dma_addr_t base)
1116{
1117 XHCIStreamContext *stctx;
1118 unsigned int i;
1119
1120 stctx = g_new0(XHCIStreamContext, count)((XHCIStreamContext *) g_malloc0_n ((count), sizeof (XHCIStreamContext
)))
;
1121 for (i = 0; i < count; i++) {
1122 stctx[i].pctx = base + i * 16;
1123 stctx[i].sct = -1;
1124 }
1125 return stctx;
1126}
1127
1128static void xhci_reset_streams(XHCIEPContext *epctx)
1129{
1130 unsigned int i;
1131
1132 for (i = 0; i < epctx->nr_pstreams; i++) {
1133 epctx->pstreams[i].sct = -1;
1134 }
1135}
1136
1137static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
1138{
1139 assert(epctx->pstreams == NULL)((epctx->pstreams == ((void*)0)) ? (void) (0) : __assert_fail
("epctx->pstreams == ((void*)0)", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1139, __PRETTY_FUNCTION__))
;
1140 epctx->nr_pstreams = 2 << (epctx->max_pstreams + 1);
1141 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
1142}
1143
1144static void xhci_free_streams(XHCIEPContext *epctx)
1145{
1146 assert(epctx->pstreams != NULL)((epctx->pstreams != ((void*)0)) ? (void) (0) : __assert_fail
("epctx->pstreams != ((void*)0)", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1146, __PRETTY_FUNCTION__))
;
1147
1148 g_free(epctx->pstreams);
1149 epctx->pstreams = NULL((void*)0);
1150 epctx->nr_pstreams = 0;
1151}
1152
1153static int xhci_epmask_to_eps_with_streams(XHCIState *xhci,
1154 unsigned int slotid,
1155 uint32_t epmask,
1156 XHCIEPContext **epctxs,
1157 USBEndpoint **eps)
1158{
1159 XHCISlot *slot;
1160 XHCIEPContext *epctx;
1161 USBEndpoint *ep;
1162 int i, j;
1163
1164 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1164
, __PRETTY_FUNCTION__))
;
1165
1166 slot = &xhci->slots[slotid - 1];
1167
1168 for (i = 2, j = 0; i <= 31; i++) {
1169 if (!(epmask & (1 << i))) {
1170 continue;
1171 }
1172
1173 epctx = slot->eps[i - 1];
1174 ep = xhci_epid_to_usbep(xhci, slotid, i);
1175 if (!epctx || !epctx->nr_pstreams || !ep) {
1176 continue;
1177 }
1178
1179 if (epctxs) {
1180 epctxs[j] = epctx;
1181 }
1182 eps[j++] = ep;
1183 }
1184 return j;
1185}
1186
1187static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid,
1188 uint32_t epmask)
1189{
1190 USBEndpoint *eps[30];
1191 int nr_eps;
1192
1193 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL((void*)0), eps);
1194 if (nr_eps) {
1195 usb_device_free_streams(eps[0]->dev, eps, nr_eps);
1196 }
1197}
1198
1199static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid,
1200 uint32_t epmask)
1201{
1202 XHCIEPContext *epctxs[30];
1203 USBEndpoint *eps[30];
1204 int i, r, nr_eps, req_nr_streams, dev_max_streams;
1205
1206 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs,
1207 eps);
1208 if (nr_eps == 0) {
1209 return CC_SUCCESS;
1210 }
1211
1212 req_nr_streams = epctxs[0]->nr_pstreams;
1213 dev_max_streams = eps[0]->max_streams;
1214
1215 for (i = 1; i < nr_eps; i++) {
1216 /*
1217 * HdG: I don't expect these to ever trigger, but if they do we need
1218 * to come up with another solution, ie group identical endpoints
1219 * together and make an usb_device_alloc_streams call per group.
1220 */
1221 if (epctxs[i]->nr_pstreams != req_nr_streams) {
1222 FIXME("guest streams config not identical for all eps")do { fprintf(stderr, "FIXME %s:%d %s\n", __func__, 1222, "guest streams config not identical for all eps"
); abort(); } while (0)
;
1223 return CC_RESOURCE_ERROR;
1224 }
1225 if (eps[i]->max_streams != dev_max_streams) {
1226 FIXME("device streams config not identical for all eps")do { fprintf(stderr, "FIXME %s:%d %s\n", __func__, 1226, "device streams config not identical for all eps"
); abort(); } while (0)
;
1227 return CC_RESOURCE_ERROR;
1228 }
1229 }
1230
1231 /*
1232 * max-streams in both the device descriptor and in the controller is a
1233 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
1234 * streams the guest will ask for 5 rounded up to the next power of 2 which
1235 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
1236 *
1237 * For redirected devices however this is an issue, as there we must ask
1238 * the real xhci controller to alloc streams, and the host driver for the
1239 * real xhci controller will likely disallow allocating more streams then
1240 * the device can handle.
1241 *
1242 * So we limit the requested nr_streams to the maximum number the device
1243 * can handle.
1244 */
1245 if (req_nr_streams > dev_max_streams) {
1246 req_nr_streams = dev_max_streams;
1247 }
1248
1249 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams);
1250 if (r != 0) {
1251 fprintf(stderrstderr, "xhci: alloc streams failed\n");
1252 return CC_RESOURCE_ERROR;
1253 }
1254
1255 return CC_SUCCESS;
1256}
1257
1258static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1259 unsigned int streamid,
1260 uint32_t *cc_error)
1261{
1262 XHCIStreamContext *sctx;
1263 dma_addr_t base;
1264 uint32_t ctx[2], sct;
1265
1266 assert(streamid != 0)((streamid != 0) ? (void) (0) : __assert_fail ("streamid != 0"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1266
, __PRETTY_FUNCTION__))
;
1267 if (epctx->lsa) {
1268 if (streamid >= epctx->nr_pstreams) {
1269 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1270 return NULL((void*)0);
1271 }
1272 sctx = epctx->pstreams + streamid;
1273 } else {
1274 FIXME("secondary streams not implemented yet")do { fprintf(stderr, "FIXME %s:%d %s\n", __func__, 1274, "secondary streams not implemented yet"
); abort(); } while (0)
;
1275 }
1276
1277 if (sctx->sct == -1) {
1278 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
1279 sct = (ctx[0] >> 1) & 0x07;
1280 if (epctx->lsa && sct != 1) {
1281 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1282 return NULL((void*)0);
1283 }
1284 sctx->sct = sct;
1285 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1286 xhci_ring_init(epctx->xhci, &sctx->ring, base);
1287 }
1288 return sctx;
1289}
1290
1291static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
1292 XHCIStreamContext *sctx, uint32_t state)
1293{
1294 XHCIRing *ring = NULL((void*)0);
1295 uint32_t ctx[5];
1296 uint32_t ctx2[2];
1297
1298 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1299 ctx[0] &= ~EP_STATE_MASK0x7;
1300 ctx[0] |= state;
1301
1302 /* update ring dequeue ptr */
1303 if (epctx->nr_pstreams) {
1304 if (sctx != NULL((void*)0)) {
1305 ring = &sctx->ring;
1306 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1307 ctx2[0] &= 0xe;
1308 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1309 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1310 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1311 }
1312 } else {
1313 ring = &epctx->ring;
1314 }
1315 if (ring) {
1316 ctx[2] = ring->dequeue | ring->ccs;
1317 ctx[3] = (ring->dequeue >> 16) >> 16;
1318
1319 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",do {} while (0)
1320 epctx->pctx, state, ctx[3], ctx[2])do {} while (0);
1321 }
1322
1323 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1324 if (epctx->state != state) {
1325 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1326 ep_state_name(epctx->state),
1327 ep_state_name(state));
1328 }
1329 epctx->state = state;
1330}
1331
1332static void xhci_ep_kick_timer(void *opaque)
1333{
1334 XHCIEPContext *epctx = opaque;
1335 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0);
1336}
1337
1338static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1339 unsigned int slotid,
1340 unsigned int epid)
1341{
1342 XHCIEPContext *epctx;
1343 int i;
1344
1345 epctx = g_new0(XHCIEPContext, 1)((XHCIEPContext *) g_malloc0_n ((1), sizeof (XHCIEPContext)));
1346 epctx->xhci = xhci;
1347 epctx->slotid = slotid;
1348 epctx->epid = epid;
1349
1350 for (i = 0; i < ARRAY_SIZE(epctx->transfers)(sizeof(epctx->transfers) / sizeof((epctx->transfers)[0
]))
; i++) {
1351 epctx->transfers[i].xhci = xhci;
1352 epctx->transfers[i].slotid = slotid;
1353 epctx->transfers[i].epid = epid;
1354 usb_packet_init(&epctx->transfers[i].packet);
1355 }
1356 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
1357
1358 return epctx;
1359}
1360
1361static void xhci_init_epctx(XHCIEPContext *epctx,
1362 dma_addr_t pctx, uint32_t *ctx)
1363{
1364 dma_addr_t dequeue;
1365
1366 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1367
1368 epctx->type = (ctx[1] >> EP_TYPE_SHIFT3) & EP_TYPE_MASK0x7;
1369 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type)do {} while (0);
1370 epctx->pctx = pctx;
1371 epctx->max_psize = ctx[1]>>16;
1372 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
1373 epctx->max_pstreams = (ctx[0] >> 10) & 0xf;
1374 epctx->lsa = (ctx[0] >> 15) & 1;
1375 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",do {} while (0)
1376 epid/2, epid%2, epctx->max_psize)do {} while (0);
1377 if (epctx->max_pstreams) {
1378 xhci_alloc_streams(epctx, dequeue);
1379 } else {
1380 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
1381 epctx->ring.ccs = ctx[2] & 1;
1382 }
1383
1384 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff);
1385}
1386
1387static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1388 unsigned int epid, dma_addr_t pctx,
1389 uint32_t *ctx)
1390{
1391 XHCISlot *slot;
1392 XHCIEPContext *epctx;
1393
1394 trace_usb_xhci_ep_enable(slotid, epid);
1395 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1395
, __PRETTY_FUNCTION__))
;
1396 assert(epid >= 1 && epid <= 31)((epid >= 1 && epid <= 31) ? (void) (0) : __assert_fail
("epid >= 1 && epid <= 31", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1396, __PRETTY_FUNCTION__))
;
1397
1398 slot = &xhci->slots[slotid-1];
1399 if (slot->eps[epid-1]) {
1400 xhci_disable_ep(xhci, slotid, epid);
1401 }
1402
1403 epctx = xhci_alloc_epctx(xhci, slotid, epid);
1404 slot->eps[epid-1] = epctx;
1405 xhci_init_epctx(epctx, pctx, ctx);
1406
1407 epctx->mfindex_last = 0;
1408
1409 epctx->state = EP_RUNNING(1<<0);
1410 ctx[0] &= ~EP_STATE_MASK0x7;
1411 ctx[0] |= EP_RUNNING(1<<0);
1412
1413 return CC_SUCCESS;
1414}
1415
1416static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report)
1417{
1418 int killed = 0;
1419
1420 if (report && (t->running_async || t->running_retry)) {
1421 t->status = report;
1422 xhci_xfer_report(t);
1423 }
1424
1425 if (t->running_async) {
1426 usb_cancel_packet(&t->packet);
1427 t->running_async = 0;
1428 killed = 1;
1429 }
1430 if (t->running_retry) {
1431 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1];
1432 if (epctx) {
1433 epctx->retry = NULL((void*)0);
1434 timer_del(epctx->kick_timer);
1435 }
1436 t->running_retry = 0;
1437 killed = 1;
1438 }
1439 if (t->trbs) {
1440 g_free(t->trbs);
1441 }
1442
1443 t->trbs = NULL((void*)0);
1444 t->trb_count = t->trb_alloced = 0;
1445
1446 return killed;
1447}
1448
1449static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1450 unsigned int epid, TRBCCode report)
1451{
1452 XHCISlot *slot;
1453 XHCIEPContext *epctx;
1454 int i, xferi, killed = 0;
1455 USBEndpoint *ep = NULL((void*)0);
1456 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1456
, __PRETTY_FUNCTION__))
;
1457 assert(epid >= 1 && epid <= 31)((epid >= 1 && epid <= 31) ? (void) (0) : __assert_fail
("epid >= 1 && epid <= 31", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1457, __PRETTY_FUNCTION__))
;
1458
1459 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid)do {} while (0);
1460
1461 slot = &xhci->slots[slotid-1];
1462
1463 if (!slot->eps[epid-1]) {
1464 return 0;
1465 }
1466
1467 epctx = slot->eps[epid-1];
1468
1469 xferi = epctx->next_xfer;
1470 for (i = 0; i < TD_QUEUE24; i++) {
1471 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi], report);
1472 if (killed) {
1473 report = 0; /* Only report once */
1474 }
1475 epctx->transfers[xferi].packet.ep = NULL((void*)0);
1476 xferi = (xferi + 1) % TD_QUEUE24;
1477 }
1478
1479 ep = xhci_epid_to_usbep(xhci, slotid, epid);
1480 if (ep) {
1481 usb_device_ep_stopped(ep->dev, ep);
1482 }
1483 return killed;
1484}
1485
1486static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1487 unsigned int epid)
1488{
1489 XHCISlot *slot;
1490 XHCIEPContext *epctx;
1491 int i;
1492
1493 trace_usb_xhci_ep_disable(slotid, epid);
1494 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1494
, __PRETTY_FUNCTION__))
;
1495 assert(epid >= 1 && epid <= 31)((epid >= 1 && epid <= 31) ? (void) (0) : __assert_fail
("epid >= 1 && epid <= 31", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1495, __PRETTY_FUNCTION__))
;
1496
1497 slot = &xhci->slots[slotid-1];
1498
1499 if (!slot->eps[epid-1]) {
1500 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid)do {} while (0);
1501 return CC_SUCCESS;
1502 }
1503
1504 xhci_ep_nuke_xfers(xhci, slotid, epid, 0);
1505
1506 epctx = slot->eps[epid-1];
1507
1508 if (epctx->nr_pstreams) {
1509 xhci_free_streams(epctx);
1510 }
1511
1512 for (i = 0; i < ARRAY_SIZE(epctx->transfers)(sizeof(epctx->transfers) / sizeof((epctx->transfers)[0
]))
; i++) {
1513 usb_packet_cleanup(&epctx->transfers[i].packet);
1514 }
1515
1516 xhci_set_ep_state(xhci, epctx, NULL((void*)0), EP_DISABLED(0<<0));
1517
1518 timer_free(epctx->kick_timer);
1519 g_free(epctx);
1520 slot->eps[epid-1] = NULL((void*)0);
1521
1522 return CC_SUCCESS;
1523}
1524
1525static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1526 unsigned int epid)
1527{
1528 XHCISlot *slot;
1529 XHCIEPContext *epctx;
1530
1531 trace_usb_xhci_ep_stop(slotid, epid);
1532 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1532
, __PRETTY_FUNCTION__))
;
1533
1534 if (epid < 1 || epid > 31) {
1535 fprintf(stderrstderr, "xhci: bad ep %d\n", epid);
1536 return CC_TRB_ERROR;
1537 }
1538
1539 slot = &xhci->slots[slotid-1];
1540
1541 if (!slot->eps[epid-1]) {
1542 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid)do {} while (0);
1543 return CC_EP_NOT_ENABLED_ERROR;
1544 }
1545
1546 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) {
1547 fprintf(stderrstderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
1548 "data might be lost\n");
1549 }
1550
1551 epctx = slot->eps[epid-1];
1552
1553 xhci_set_ep_state(xhci, epctx, NULL((void*)0), EP_STOPPED(3<<0));
1554
1555 if (epctx->nr_pstreams) {
1556 xhci_reset_streams(epctx);
1557 }
1558
1559 return CC_SUCCESS;
1560}
1561
1562static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1563 unsigned int epid)
1564{
1565 XHCISlot *slot;
1566 XHCIEPContext *epctx;
1567
1568 trace_usb_xhci_ep_reset(slotid, epid);
1569 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1569
, __PRETTY_FUNCTION__))
;
1570
1571 if (epid < 1 || epid > 31) {
1572 fprintf(stderrstderr, "xhci: bad ep %d\n", epid);
1573 return CC_TRB_ERROR;
1574 }
1575
1576 slot = &xhci->slots[slotid-1];
1577
1578 if (!slot->eps[epid-1]) {
1579 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid)do {} while (0);
1580 return CC_EP_NOT_ENABLED_ERROR;
1581 }
1582
1583 epctx = slot->eps[epid-1];
1584
1585 if (epctx->state != EP_HALTED(2<<0)) {
1586 fprintf(stderrstderr, "xhci: reset EP while EP %d not halted (%d)\n",
1587 epid, epctx->state);
1588 return CC_CONTEXT_STATE_ERROR;
1589 }
1590
1591 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) {
1592 fprintf(stderrstderr, "xhci: FIXME: endpoint reset w/ xfers running, "
1593 "data might be lost\n");
1594 }
1595
1596 uint8_t ep = epid>>1;
1597
1598 if (epid & 1) {
1599 ep |= 0x80;
Value stored to 'ep' is never read
1600 }
1601
1602 if (!xhci->slots[slotid-1].uport ||
1603 !xhci->slots[slotid-1].uport->dev ||
1604 !xhci->slots[slotid-1].uport->dev->attached) {
1605 return CC_USB_TRANSACTION_ERROR;
1606 }
1607
1608 xhci_set_ep_state(xhci, epctx, NULL((void*)0), EP_STOPPED(3<<0));
1609
1610 if (epctx->nr_pstreams) {
1611 xhci_reset_streams(epctx);
1612 }
1613
1614 return CC_SUCCESS;
1615}
1616
1617static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1618 unsigned int epid, unsigned int streamid,
1619 uint64_t pdequeue)
1620{
1621 XHCISlot *slot;
1622 XHCIEPContext *epctx;
1623 XHCIStreamContext *sctx;
1624 dma_addr_t dequeue;
1625
1626 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1626
, __PRETTY_FUNCTION__))
;
1627
1628 if (epid < 1 || epid > 31) {
1629 fprintf(stderrstderr, "xhci: bad ep %d\n", epid);
1630 return CC_TRB_ERROR;
1631 }
1632
1633 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
1634 dequeue = xhci_mask64(pdequeue);
1635
1636 slot = &xhci->slots[slotid-1];
1637
1638 if (!slot->eps[epid-1]) {
1639 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid)do {} while (0);
1640 return CC_EP_NOT_ENABLED_ERROR;
1641 }
1642
1643 epctx = slot->eps[epid-1];
1644
1645 if (epctx->state != EP_STOPPED(3<<0)) {
1646 fprintf(stderrstderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1647 return CC_CONTEXT_STATE_ERROR;
1648 }
1649
1650 if (epctx->nr_pstreams) {
1651 uint32_t err;
1652 sctx = xhci_find_stream(epctx, streamid, &err);
1653 if (sctx == NULL((void*)0)) {
1654 return err;
1655 }
1656 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1657 sctx->ring.ccs = dequeue & 1;
1658 } else {
1659 sctx = NULL((void*)0);
1660 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1661 epctx->ring.ccs = dequeue & 1;
1662 }
1663
1664 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED(3<<0));
1665
1666 return CC_SUCCESS;
1667}
1668
1669static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
1670{
1671 XHCIState *xhci = xfer->xhci;
1672 int i;
1673
1674 xfer->int_req = false0;
1675 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 1675, __func__))
, xfer->trb_count);
1676 for (i = 0; i < xfer->trb_count; i++) {
1677 XHCITRB *trb = &xfer->trbs[i];
1678 dma_addr_t addr;
1679 unsigned int chunk = 0;
1680
1681 if (trb->control & TRB_TR_IOC(1<<5)) {
1682 xfer->int_req = true1;
1683 }
1684
1685 switch (TRB_TYPE(*trb)(((*trb).control >> 10) & 0x3f)) {
1686 case TR_DATA:
1687 if ((!(trb->control & TRB_TR_DIR(1<<16))) != (!in_xfer)) {
1688 fprintf(stderrstderr, "xhci: data direction mismatch for TR_DATA\n");
1689 goto err;
1690 }
1691 /* fallthrough */
1692 case TR_NORMAL:
1693 case TR_ISOCH:
1694 addr = xhci_mask64(trb->parameter);
1695 chunk = trb->status & 0x1ffff;
1696 if (trb->control & TRB_TR_IDT(1<<6)) {
1697 if (chunk > 8 || in_xfer) {
1698 fprintf(stderrstderr, "xhci: invalid immediate data TRB\n");
1699 goto err;
1700 }
1701 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1702 } else {
1703 qemu_sglist_add(&xfer->sgl, addr, chunk);
1704 }
1705 break;
1706 }
1707 }
1708
1709 return 0;
1710
1711err:
1712 qemu_sglist_destroy(&xfer->sgl);
1713 xhci_die(xhci);
1714 return -1;
1715}
1716
1717static void xhci_xfer_unmap(XHCITransfer *xfer)
1718{
1719 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1720 qemu_sglist_destroy(&xfer->sgl);
1721}
1722
1723static void xhci_xfer_report(XHCITransfer *xfer)
1724{
1725 uint32_t edtla = 0;
1726 unsigned int left;
1727 bool_Bool reported = 0;
1728 bool_Bool shortpkt = 0;
1729 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1730 XHCIState *xhci = xfer->xhci;
1731 int i;
1732
1733 left = xfer->packet.actual_length;
1734
1735 for (i = 0; i < xfer->trb_count; i++) {
1736 XHCITRB *trb = &xfer->trbs[i];
1737 unsigned int chunk = 0;
1738
1739 switch (TRB_TYPE(*trb)(((*trb).control >> 10) & 0x3f)) {
1740 case TR_DATA:
1741 case TR_NORMAL:
1742 case TR_ISOCH:
1743 chunk = trb->status & 0x1ffff;
1744 if (chunk > left) {
1745 chunk = left;
1746 if (xfer->status == CC_SUCCESS) {
1747 shortpkt = 1;
1748 }
1749 }
1750 left -= chunk;
1751 edtla += chunk;
1752 break;
1753 case TR_STATUS:
1754 reported = 0;
1755 shortpkt = 0;
1756 break;
1757 }
1758
1759 if (!reported && ((trb->control & TRB_TR_IOC(1<<5)) ||
1760 (shortpkt && (trb->control & TRB_TR_ISP(1<<2))) ||
1761 (xfer->status != CC_SUCCESS && left == 0))) {
1762 event.slotid = xfer->slotid;
1763 event.epid = xfer->epid;
1764 event.length = (trb->status & 0x1ffff) - chunk;
1765 event.flags = 0;
1766 event.ptr = trb->addr;
1767 if (xfer->status == CC_SUCCESS) {
1768 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1769 } else {
1770 event.ccode = xfer->status;
1771 }
1772 if (TRB_TYPE(*trb)(((*trb).control >> 10) & 0x3f) == TR_EVDATA) {
1773 event.ptr = trb->parameter;
1774 event.flags |= TRB_EV_ED(1<<2);
1775 event.length = edtla & 0xffffff;
1776 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length)do {} while (0);
1777 edtla = 0;
1778 }
1779 xhci_event(xhci, &event, TRB_INTR(*trb)(((*trb).status >> 22) & 0x3ff));
1780 reported = 1;
1781 if (xfer->status != CC_SUCCESS) {
1782 return;
1783 }
1784 }
1785 }
1786}
1787
1788static void xhci_stall_ep(XHCITransfer *xfer)
1789{
1790 XHCIState *xhci = xfer->xhci;
1791 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1792 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1793 uint32_t err;
1794 XHCIStreamContext *sctx;
1795
1796 if (epctx->nr_pstreams) {
1797 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1798 if (sctx == NULL((void*)0)) {
1799 return;
1800 }
1801 sctx->ring.dequeue = xfer->trbs[0].addr;
1802 sctx->ring.ccs = xfer->trbs[0].ccs;
1803 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED(2<<0));
1804 } else {
1805 epctx->ring.dequeue = xfer->trbs[0].addr;
1806 epctx->ring.ccs = xfer->trbs[0].ccs;
1807 xhci_set_ep_state(xhci, epctx, NULL((void*)0), EP_HALTED(2<<0));
1808 }
1809}
1810
1811static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1812 XHCIEPContext *epctx);
1813
1814static int xhci_setup_packet(XHCITransfer *xfer)
1815{
1816 XHCIState *xhci = xfer->xhci;
1817 USBEndpoint *ep;
1818 int dir;
1819
1820 dir = xfer->in_xfer ? USB_TOKEN_IN0x69 : USB_TOKEN_OUT0xe1;
1821
1822 if (xfer->packet.ep) {
1823 ep = xfer->packet.ep;
1824 } else {
1825 ep = xhci_epid_to_usbep(xhci, xfer->slotid, xfer->epid);
1826 if (!ep) {
1827 fprintf(stderrstderr, "xhci: slot %d has no device\n",
1828 xfer->slotid);
1829 return -1;
1830 }
1831 }
1832
1833 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN0x69); /* Also sets int_req */
1834 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
1835 xfer->trbs[0].addr, false0, xfer->int_req);
1836 usb_packet_map(&xfer->packet, &xfer->sgl);
1837 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",do {} while (0)
1838 xfer->packet.pid, ep->dev->addr, ep->nr)do {} while (0);
1839 return 0;
1840}
1841
1842static int xhci_complete_packet(XHCITransfer *xfer)
1843{
1844 if (xfer->packet.status == USB_RET_ASYNC(-6)) {
1845 trace_usb_xhci_xfer_async(xfer);
1846 xfer->running_async = 1;
1847 xfer->running_retry = 0;
1848 xfer->complete = 0;
1849 return 0;
1850 } else if (xfer->packet.status == USB_RET_NAK(-2)) {
1851 trace_usb_xhci_xfer_nak(xfer);
1852 xfer->running_async = 0;
1853 xfer->running_retry = 1;
1854 xfer->complete = 0;
1855 return 0;
1856 } else {
1857 xfer->running_async = 0;
1858 xfer->running_retry = 0;
1859 xfer->complete = 1;
1860 xhci_xfer_unmap(xfer);
1861 }
1862
1863 if (xfer->packet.status == USB_RET_SUCCESS(0)) {
1864 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
1865 xfer->status = CC_SUCCESS;
1866 xhci_xfer_report(xfer);
1867 return 0;
1868 }
1869
1870 /* error */
1871 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1872 switch (xfer->packet.status) {
1873 case USB_RET_NODEV(-1):
1874 case USB_RET_IOERROR(-5):
1875 xfer->status = CC_USB_TRANSACTION_ERROR;
1876 xhci_xfer_report(xfer);
1877 xhci_stall_ep(xfer);
1878 break;
1879 case USB_RET_STALL(-3):
1880 xfer->status = CC_STALL_ERROR;
1881 xhci_xfer_report(xfer);
1882 xhci_stall_ep(xfer);
1883 break;
1884 case USB_RET_BABBLE(-4):
1885 xfer->status = CC_BABBLE_DETECTED;
1886 xhci_xfer_report(xfer);
1887 xhci_stall_ep(xfer);
1888 break;
1889 default:
1890 fprintf(stderrstderr, "%s: FIXME: status = %d\n", __func__,
1891 xfer->packet.status);
1892 FIXME("unhandled USB_RET_*")do { fprintf(stderr, "FIXME %s:%d %s\n", __func__, 1892, "unhandled USB_RET_*"
); abort(); } while (0)
;
1893 }
1894 return 0;
1895}
1896
1897static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1898{
1899 XHCITRB *trb_setup, *trb_status;
1900 uint8_t bmRequestType;
1901
1902 trb_setup = &xfer->trbs[0];
1903 trb_status = &xfer->trbs[xfer->trb_count-1];
1904
1905 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
1906
1907 /* at most one Event Data TRB allowed after STATUS */
1908 if (TRB_TYPE(*trb_status)(((*trb_status).control >> 10) & 0x3f) == TR_EVDATA && xfer->trb_count > 2) {
1909 trb_status--;
1910 }
1911
1912 /* do some sanity checks */
1913 if (TRB_TYPE(*trb_setup)(((*trb_setup).control >> 10) & 0x3f) != TR_SETUP) {
1914 fprintf(stderrstderr, "xhci: ep0 first TD not SETUP: %d\n",
1915 TRB_TYPE(*trb_setup)(((*trb_setup).control >> 10) & 0x3f));
1916 return -1;
1917 }
1918 if (TRB_TYPE(*trb_status)(((*trb_status).control >> 10) & 0x3f) != TR_STATUS) {
1919 fprintf(stderrstderr, "xhci: ep0 last TD not STATUS: %d\n",
1920 TRB_TYPE(*trb_status)(((*trb_status).control >> 10) & 0x3f));
1921 return -1;
1922 }
1923 if (!(trb_setup->control & TRB_TR_IDT(1<<6))) {
1924 fprintf(stderrstderr, "xhci: Setup TRB doesn't have IDT set\n");
1925 return -1;
1926 }
1927 if ((trb_setup->status & 0x1ffff) != 8) {
1928 fprintf(stderrstderr, "xhci: Setup TRB has bad length (%d)\n",
1929 (trb_setup->status & 0x1ffff));
1930 return -1;
1931 }
1932
1933 bmRequestType = trb_setup->parameter;
1934
1935 xfer->in_xfer = bmRequestType & USB_DIR_IN0x80;
1936 xfer->iso_xfer = false0;
1937 xfer->timed_xfer = false0;
1938
1939 if (xhci_setup_packet(xfer) < 0) {
1940 return -1;
1941 }
1942 xfer->packet.parameter = trb_setup->parameter;
1943
1944 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1945
1946 xhci_complete_packet(xfer);
1947 if (!xfer->running_async && !xfer->running_retry) {
1948 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0);
1949 }
1950 return 0;
1951}
1952
1953static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
1954 XHCIEPContext *epctx, uint64_t mfindex)
1955{
1956 uint64_t asap = ((mfindex + epctx->interval - 1) &
1957 ~(epctx->interval-1));
1958 uint64_t kick = epctx->mfindex_last + epctx->interval;
1959
1960 assert(epctx->interval != 0)((epctx->interval != 0) ? (void) (0) : __assert_fail ("epctx->interval != 0"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 1960
, __PRETTY_FUNCTION__))
;
1961 xfer->mfindex_kick = MAX(asap, kick)(((asap) > (kick)) ? (asap) : (kick));
1962}
1963
1964static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1965 XHCIEPContext *epctx, uint64_t mfindex)
1966{
1967 if (xfer->trbs[0].control & TRB_TR_SIA(1<<31)) {
1968 uint64_t asap = ((mfindex + epctx->interval - 1) &
1969 ~(epctx->interval-1));
1970 if (asap >= epctx->mfindex_last &&
1971 asap <= epctx->mfindex_last + epctx->interval * 4) {
1972 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1973 } else {
1974 xfer->mfindex_kick = asap;
1975 }
1976 } else {
1977 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT20)
1978 & TRB_TR_FRAMEID_MASK0x7ff;
1979 xfer->mfindex_kick |= mfindex & ~0x3fff;
1980 if (xfer->mfindex_kick < mfindex) {
1981 xfer->mfindex_kick += 0x4000;
1982 }
1983 }
1984}
1985
1986static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1987 XHCIEPContext *epctx, uint64_t mfindex)
1988{
1989 if (xfer->mfindex_kick > mfindex) {
1990 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1991 (xfer->mfindex_kick - mfindex) * 125000);
1992 xfer->running_retry = 1;
1993 } else {
1994 epctx->mfindex_last = xfer->mfindex_kick;
1995 timer_del(epctx->kick_timer);
1996 xfer->running_retry = 0;
1997 }
1998}
1999
2000
2001static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
2002{
2003 uint64_t mfindex;
2004
2005 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid)do {} while (0);
2006
2007 xfer->in_xfer = epctx->type>>2;
2008
2009 switch(epctx->type) {
2010 case ET_INTR_OUT:
2011 case ET_INTR_IN:
2012 xfer->pkts = 0;
2013 xfer->iso_xfer = false0;
2014 xfer->timed_xfer = true1;
2015 mfindex = xhci_mfindex_get(xhci);
2016 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
2017 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2018 if (xfer->running_retry) {
2019 return -1;
2020 }
2021 break;
2022 case ET_BULK_OUT:
2023 case ET_BULK_IN:
2024 xfer->pkts = 0;
2025 xfer->iso_xfer = false0;
2026 xfer->timed_xfer = false0;
2027 break;
2028 case ET_ISO_OUT:
2029 case ET_ISO_IN:
2030 xfer->pkts = 1;
2031 xfer->iso_xfer = true1;
2032 xfer->timed_xfer = true1;
2033 mfindex = xhci_mfindex_get(xhci);
2034 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
2035 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2036 if (xfer->running_retry) {
2037 return -1;
2038 }
2039 break;
2040 default:
2041 fprintf(stderrstderr, "xhci: unknown or unhandled EP "
2042 "(type %d, in %d, ep %02x)\n",
2043 epctx->type, xfer->in_xfer, xfer->epid);
2044 return -1;
2045 }
2046
2047 if (xhci_setup_packet(xfer) < 0) {
2048 return -1;
2049 }
2050 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2051
2052 xhci_complete_packet(xfer);
2053 if (!xfer->running_async && !xfer->running_retry) {
2054 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid);
2055 }
2056 return 0;
2057}
2058
2059static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
2060{
2061 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
2062 return xhci_submit(xhci, xfer, epctx);
2063}
2064
2065static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
2066 unsigned int epid, unsigned int streamid)
2067{
2068 XHCIStreamContext *stctx;
2069 XHCIEPContext *epctx;
2070 XHCIRing *ring;
2071 USBEndpoint *ep = NULL((void*)0);
2072 uint64_t mfindex;
2073 int length;
2074 int i;
2075
2076 trace_usb_xhci_ep_kick(slotid, epid, streamid);
2077 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 2077
, __PRETTY_FUNCTION__))
;
2078 assert(epid >= 1 && epid <= 31)((epid >= 1 && epid <= 31) ? (void) (0) : __assert_fail
("epid >= 1 && epid <= 31", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 2078, __PRETTY_FUNCTION__))
;
2079
2080 if (!xhci->slots[slotid-1].enabled) {
2081 fprintf(stderrstderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
2082 return;
2083 }
2084 epctx = xhci->slots[slotid-1].eps[epid-1];
2085 if (!epctx) {
2086 fprintf(stderrstderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
2087 epid, slotid);
2088 return;
2089 }
2090
2091 /* If the device has been detached, but the guest has not noticed this
2092 yet the 2 above checks will succeed, but we must NOT continue */
2093 if (!xhci->slots[slotid - 1].uport ||
2094 !xhci->slots[slotid - 1].uport->dev ||
2095 !xhci->slots[slotid - 1].uport->dev->attached) {
2096 return;
2097 }
2098
2099 if (epctx->retry) {
2100 XHCITransfer *xfer = epctx->retry;
2101
2102 trace_usb_xhci_xfer_retry(xfer);
2103 assert(xfer->running_retry)((xfer->running_retry) ? (void) (0) : __assert_fail ("xfer->running_retry"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 2103
, __PRETTY_FUNCTION__))
;
2104 if (xfer->timed_xfer) {
2105 /* time to kick the transfer? */
2106 mfindex = xhci_mfindex_get(xhci);
2107 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2108 if (xfer->running_retry) {
2109 return;
2110 }
2111 xfer->timed_xfer = 0;
2112 xfer->running_retry = 1;
2113 }
2114 if (xfer->iso_xfer) {
2115 /* retry iso transfer */
2116 if (xhci_setup_packet(xfer) < 0) {
2117 return;
2118 }
2119 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2120 assert(xfer->packet.status != USB_RET_NAK)((xfer->packet.status != (-2)) ? (void) (0) : __assert_fail
("xfer->packet.status != (-2)", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 2120, __PRETTY_FUNCTION__))
;
2121 xhci_complete_packet(xfer);
2122 } else {
2123 /* retry nak'ed transfer */
2124 if (xhci_setup_packet(xfer) < 0) {
2125 return;
2126 }
2127 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2128 if (xfer->packet.status == USB_RET_NAK(-2)) {
2129 return;
2130 }
2131 xhci_complete_packet(xfer);
2132 }
2133 assert(!xfer->running_retry)((!xfer->running_retry) ? (void) (0) : __assert_fail ("!xfer->running_retry"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 2133
, __PRETTY_FUNCTION__))
;
2134 epctx->retry = NULL((void*)0);
2135 }
2136
2137 if (epctx->state == EP_HALTED(2<<0)) {
2138 DPRINTF("xhci: ep halted, not running schedule\n")do {} while (0);
2139 return;
2140 }
2141
2142
2143 if (epctx->nr_pstreams) {
2144 uint32_t err;
2145 stctx = xhci_find_stream(epctx, streamid, &err);
2146 if (stctx == NULL((void*)0)) {
2147 return;
2148 }
2149 ring = &stctx->ring;
2150 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING(1<<0));
2151 } else {
2152 ring = &epctx->ring;
2153 streamid = 0;
2154 xhci_set_ep_state(xhci, epctx, NULL((void*)0), EP_RUNNING(1<<0));
2155 }
2156 assert(ring->dequeue != 0)((ring->dequeue != 0) ? (void) (0) : __assert_fail ("ring->dequeue != 0"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 2156
, __PRETTY_FUNCTION__))
;
2157
2158 while (1) {
2159 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
2160 if (xfer->running_async || xfer->running_retry) {
2161 break;
2162 }
2163 length = xhci_ring_chain_length(xhci, ring);
2164 if (length < 0) {
2165 break;
2166 } else if (length == 0) {
2167 break;
2168 }
2169 if (xfer->trbs && xfer->trb_alloced < length) {
2170 xfer->trb_count = 0;
2171 xfer->trb_alloced = 0;
2172 g_free(xfer->trbs);
2173 xfer->trbs = NULL((void*)0);
2174 }
2175 if (!xfer->trbs) {
2176 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
2177 xfer->trb_alloced = length;
2178 }
2179 xfer->trb_count = length;
2180
2181 for (i = 0; i < length; i++) {
2182 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL))((xhci_ring_fetch(xhci, ring, &xfer->trbs[i], ((void*)
0))) ? (void) (0) : __assert_fail ("xhci_ring_fetch(xhci, ring, &xfer->trbs[i], ((void*)0))"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 2182
, __PRETTY_FUNCTION__))
;
2183 }
2184 xfer->streamid = streamid;
2185
2186 if (epid == 1) {
2187 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
2188 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE24;
2189 ep = xfer->packet.ep;
2190 } else {
2191 fprintf(stderrstderr, "xhci: error firing CTL transfer\n");
2192 }
2193 } else {
2194 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
2195 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE24;
2196 } else {
2197 if (!xfer->timed_xfer) {
2198 fprintf(stderrstderr, "xhci: error firing data transfer\n");
2199 }
2200 }
2201 }
2202
2203 if (epctx->state == EP_HALTED(2<<0)) {
2204 break;
2205 }
2206 if (xfer->running_retry) {
2207 DPRINTF("xhci: xfer nacked, stopping schedule\n")do {} while (0);
2208 epctx->retry = xfer;
2209 break;
2210 }
2211 }
2212
2213 ep = xhci_epid_to_usbep(xhci, slotid, epid);
2214 if (ep) {
2215 usb_device_flush_ep_queue(ep->dev, ep);
2216 }
2217}
2218
2219static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
2220{
2221 trace_usb_xhci_slot_enable(slotid);
2222 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 2222
, __PRETTY_FUNCTION__))
;
2223 xhci->slots[slotid-1].enabled = 1;
2224 xhci->slots[slotid-1].uport = NULL((void*)0);
2225 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
2226
2227 return CC_SUCCESS;
2228}
2229
2230static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2231{
2232 int i;
2233
2234 trace_usb_xhci_slot_disable(slotid);
2235 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 2235
, __PRETTY_FUNCTION__))
;
2236
2237 for (i = 1; i <= 31; i++) {
2238 if (xhci->slots[slotid-1].eps[i-1]) {
2239 xhci_disable_ep(xhci, slotid, i);
2240 }
2241 }
2242
2243 xhci->slots[slotid-1].enabled = 0;
2244 xhci->slots[slotid-1].addressed = 0;
2245 xhci->slots[slotid-1].uport = NULL((void*)0);
2246 return CC_SUCCESS;
2247}
2248
2249static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2250{
2251 USBPort *uport;
2252 char path[32];
2253 int i, pos, port;
2254
2255 port = (slot_ctx[1]>>16) & 0xFF;
2256 port = xhci->ports[port-1].uport->index+1;
2257 pos = snprintf(path, sizeof(path), "%d", port);
2258 for (i = 0; i < 5; i++) {
2259 port = (slot_ctx[0] >> 4*i) & 0x0f;
2260 if (!port) {
2261 break;
2262 }
2263 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2264 }
2265
2266 QTAILQ_FOREACH(uport, &xhci->bus.used, next)for ((uport) = ((&xhci->bus.used)->tqh_first); (uport
); (uport) = ((uport)->next.tqe_next))
{
2267 if (strcmp(uport->path, path) == 0) {
2268 return uport;
2269 }
2270 }
2271 return NULL((void*)0);
2272}
2273
2274static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2275 uint64_t pictx, bool_Bool bsr)
2276{
2277 XHCISlot *slot;
2278 USBPort *uport;
2279 USBDevice *dev;
2280 dma_addr_t ictx, octx, dcbaap;
2281 uint64_t poctx;
2282 uint32_t ictl_ctx[2];
2283 uint32_t slot_ctx[4];
2284 uint32_t ep0_ctx[5];
2285 int i;
2286 TRBCCode res;
2287
2288 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 2288
, __PRETTY_FUNCTION__))
;
2289
2290 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
2291 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 2291, __func__))
, dcbaap + 8 * slotid);
2292 ictx = xhci_mask64(pictx);
2293 octx = xhci_mask64(poctx);
2294
2295 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx)do {} while (0);
2296 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx)do {} while (0);
2297
2298 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2299
2300 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
2301 fprintf(stderrstderr, "xhci: invalid input context control %08x %08x\n",
2302 ictl_ctx[0], ictl_ctx[1]);
2303 return CC_TRB_ERROR;
2304 }
2305
2306 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2307 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
2308
2309 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",do {} while (0)
2310 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3])do {} while (0);
2311
2312 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",do {} while (0)
2313 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4])do {} while (0);
2314
2315 uport = xhci_lookup_uport(xhci, slot_ctx);
2316 if (uport == NULL((void*)0)) {
2317 fprintf(stderrstderr, "xhci: port not found\n");
2318 return CC_TRB_ERROR;
2319 }
2320 trace_usb_xhci_slot_address(slotid, uport->path);
2321
2322 dev = uport->dev;
2323 if (!dev || !dev->attached) {
2324 fprintf(stderrstderr, "xhci: port %s not connected\n", uport->path);
2325 return CC_USB_TRANSACTION_ERROR;
2326 }
2327
2328 for (i = 0; i < xhci->numslots; i++) {
2329 if (i == slotid-1) {
2330 continue;
2331 }
2332 if (xhci->slots[i].uport == uport) {
2333 fprintf(stderrstderr, "xhci: port %s already assigned to slot %d\n",
2334 uport->path, i+1);
2335 return CC_TRB_ERROR;
2336 }
2337 }
2338
2339 slot = &xhci->slots[slotid-1];
2340 slot->uport = uport;
2341 slot->ctx = octx;
2342
2343 if (bsr) {
2344 slot_ctx[3] = SLOT_DEFAULT1 << SLOT_STATE_SHIFT27;
2345 } else {
2346 USBPacket p;
2347 uint8_t buf[1];
2348
2349 slot_ctx[3] = (SLOT_ADDRESSED2 << SLOT_STATE_SHIFT27) | slotid;
2350 usb_device_reset(dev);
2351 memset(&p, 0, sizeof(p));
2352 usb_packet_addbuf(&p, buf, sizeof(buf));
2353 usb_packet_setup(&p, USB_TOKEN_OUT0xe1,
2354 usb_ep_get(dev, USB_TOKEN_OUT0xe1, 0), 0,
2355 0, false0, false0);
2356 usb_device_handle_control(dev, &p,
2357 DeviceOutRequest((0|(0x00 << 5)|0x00)<<8) | USB_REQ_SET_ADDRESS0x05,
2358 slotid, 0, 0, NULL((void*)0));
2359 assert(p.status != USB_RET_ASYNC)((p.status != (-6)) ? (void) (0) : __assert_fail ("p.status != (-6)"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 2359
, __PRETTY_FUNCTION__))
;
2360 }
2361
2362 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2363
2364 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",do {} while (0)
2365 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3])do {} while (0);
2366 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",do {} while (0)
2367 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4])do {} while (0);
2368
2369 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2370 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2371
2372 xhci->slots[slotid-1].addressed = 1;
2373 return res;
2374}
2375
2376
2377static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2378 uint64_t pictx, bool_Bool dc)
2379{
2380 dma_addr_t ictx, octx;
2381 uint32_t ictl_ctx[2];
2382 uint32_t slot_ctx[4];
2383 uint32_t islot_ctx[4];
2384 uint32_t ep_ctx[5];
2385 int i;
2386 TRBCCode res;
2387
2388 trace_usb_xhci_slot_configure(slotid);
2389 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 2389
, __PRETTY_FUNCTION__))
;
2390
2391 ictx = xhci_mask64(pictx);
2392 octx = xhci->slots[slotid-1].ctx;
2393
2394 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx)do {} while (0);
2395 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx)do {} while (0);
2396
2397 if (dc) {
2398 for (i = 2; i <= 31; i++) {
2399 if (xhci->slots[slotid-1].eps[i-1]) {
2400 xhci_disable_ep(xhci, slotid, i);
2401 }
2402 }
2403
2404 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2405 slot_ctx[3] &= ~(SLOT_STATE_MASK0x1f << SLOT_STATE_SHIFT27);
2406 slot_ctx[3] |= SLOT_ADDRESSED2 << SLOT_STATE_SHIFT27;
2407 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",do {} while (0)
2408 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3])do {} while (0);
2409 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2410
2411 return CC_SUCCESS;
2412 }
2413
2414 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2415
2416 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
2417 fprintf(stderrstderr, "xhci: invalid input context control %08x %08x\n",
2418 ictl_ctx[0], ictl_ctx[1]);
2419 return CC_TRB_ERROR;
2420 }
2421
2422 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2423 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2424
2425 if (SLOT_STATE(slot_ctx[3])(((slot_ctx[3])>>27)&0x1f) < SLOT_ADDRESSED2) {
2426 fprintf(stderrstderr, "xhci: invalid slot state %08x\n", slot_ctx[3]);
2427 return CC_CONTEXT_STATE_ERROR;
2428 }
2429
2430 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]);
2431
2432 for (i = 2; i <= 31; i++) {
2433 if (ictl_ctx[0] & (1<<i)) {
2434 xhci_disable_ep(xhci, slotid, i);
2435 }
2436 if (ictl_ctx[1] & (1<<i)) {
2437 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
2438 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",do {} while (0)
2439 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],do {} while (0)
2440 ep_ctx[3], ep_ctx[4])do {} while (0);
2441 xhci_disable_ep(xhci, slotid, i);
2442 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2443 if (res != CC_SUCCESS) {
2444 return res;
2445 }
2446 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",do {} while (0)
2447 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],do {} while (0)
2448 ep_ctx[3], ep_ctx[4])do {} while (0);
2449 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
2450 }
2451 }
2452
2453 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]);
2454 if (res != CC_SUCCESS) {
2455 for (i = 2; i <= 31; i++) {
2456 if (ictl_ctx[1] & (1 << i)) {
2457 xhci_disable_ep(xhci, slotid, i);
2458 }
2459 }
2460 return res;
2461 }
2462
2463 slot_ctx[3] &= ~(SLOT_STATE_MASK0x1f << SLOT_STATE_SHIFT27);
2464 slot_ctx[3] |= SLOT_CONFIGURED3 << SLOT_STATE_SHIFT27;
2465 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK0x1f << SLOT_CONTEXT_ENTRIES_SHIFT27);
2466 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK0x1f <<
2467 SLOT_CONTEXT_ENTRIES_SHIFT27);
2468 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",do {} while (0)
2469 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3])do {} while (0);
2470
2471 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2472
2473 return CC_SUCCESS;
2474}
2475
2476
2477static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2478 uint64_t pictx)
2479{
2480 dma_addr_t ictx, octx;
2481 uint32_t ictl_ctx[2];
2482 uint32_t iep0_ctx[5];
2483 uint32_t ep0_ctx[5];
2484 uint32_t islot_ctx[4];
2485 uint32_t slot_ctx[4];
2486
2487 trace_usb_xhci_slot_evaluate(slotid);
2488 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 2488
, __PRETTY_FUNCTION__))
;
2489
2490 ictx = xhci_mask64(pictx);
2491 octx = xhci->slots[slotid-1].ctx;
2492
2493 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx)do {} while (0);
2494 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx)do {} while (0);
2495
2496 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2497
2498 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
2499 fprintf(stderrstderr, "xhci: invalid input context control %08x %08x\n",
2500 ictl_ctx[0], ictl_ctx[1]);
2501 return CC_TRB_ERROR;
2502 }
2503
2504 if (ictl_ctx[1] & 0x1) {
2505 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2506
2507 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",do {} while (0)
2508 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3])do {} while (0);
2509
2510 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2511
2512 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2513 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2514 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
2515 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
2516
2517 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",do {} while (0)
2518 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3])do {} while (0);
2519
2520 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2521 }
2522
2523 if (ictl_ctx[1] & 0x2) {
2524 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2525
2526 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",do {} while (0)
2527 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],do {} while (0)
2528 iep0_ctx[3], iep0_ctx[4])do {} while (0);
2529
2530 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2531
2532 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2533 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2534
2535 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",do {} while (0)
2536 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4])do {} while (0);
2537
2538 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2539 }
2540
2541 return CC_SUCCESS;
2542}
2543
2544static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2545{
2546 uint32_t slot_ctx[4];
2547 dma_addr_t octx;
2548 int i;
2549
2550 trace_usb_xhci_slot_reset(slotid);
2551 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 2551
, __PRETTY_FUNCTION__))
;
2552
2553 octx = xhci->slots[slotid-1].ctx;
2554
2555 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx)do {} while (0);
2556
2557 for (i = 2; i <= 31; i++) {
2558 if (xhci->slots[slotid-1].eps[i-1]) {
2559 xhci_disable_ep(xhci, slotid, i);
2560 }
2561 }
2562
2563 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2564 slot_ctx[3] &= ~(SLOT_STATE_MASK0x1f << SLOT_STATE_SHIFT27);
2565 slot_ctx[3] |= SLOT_DEFAULT1 << SLOT_STATE_SHIFT27;
2566 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",do {} while (0)
2567 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3])do {} while (0);
2568 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2569
2570 return CC_SUCCESS;
2571}
2572
2573static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2574{
2575 unsigned int slotid;
2576 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT24) & TRB_CR_SLOTID_MASK0xff;
2577 if (slotid < 1 || slotid > xhci->numslots) {
2578 fprintf(stderrstderr, "xhci: bad slot id %d\n", slotid);
2579 event->ccode = CC_TRB_ERROR;
2580 return 0;
2581 } else if (!xhci->slots[slotid-1].enabled) {
2582 fprintf(stderrstderr, "xhci: slot id %d not enabled\n", slotid);
2583 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2584 return 0;
2585 }
2586 return slotid;
2587}
2588
2589/* cleanup slot state on usb device detach */
2590static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2591{
2592 int slot, ep;
2593
2594 for (slot = 0; slot < xhci->numslots; slot++) {
2595 if (xhci->slots[slot].uport == uport) {
2596 break;
2597 }
2598 }
2599 if (slot == xhci->numslots) {
2600 return;
2601 }
2602
2603 for (ep = 0; ep < 31; ep++) {
2604 if (xhci->slots[slot].eps[ep]) {
2605 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0);
2606 }
2607 }
2608 xhci->slots[slot].uport = NULL((void*)0);
2609}
2610
2611static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2612{
2613 dma_addr_t ctx;
2614 uint8_t bw_ctx[xhci->numports+1];
2615
2616 DPRINTF("xhci_get_port_bandwidth()\n")do {} while (0);
2617
2618 ctx = xhci_mask64(pctx);
2619
2620 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx)do {} while (0);
2621
2622 /* TODO: actually implement real values here */
2623 bw_ctx[0] = 0;
2624 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
2625 pci_dma_write(PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 2625, __func__))
, ctx, bw_ctx, sizeof(bw_ctx));
2626
2627 return CC_SUCCESS;
2628}
2629
2630static uint32_t rotl(uint32_t v, unsigned count)
2631{
2632 count &= 31;
2633 return (v << count) | (v >> (32 - count));
2634}
2635
2636
2637static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2638{
2639 uint32_t val;
2640 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2641 val += rotl(lo + 0x49434878, hi & 0x1F);
2642 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2643 return ~val;
2644}
2645
2646static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
2647{
2648 PCIDevice *pci_dev = PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 2648, __func__))
;
2649 uint32_t buf[8];
2650 uint32_t obuf[8];
2651 dma_addr_t paddr = xhci_mask64(addr);
2652
2653 pci_dma_read(pci_dev, paddr, &buf, 32);
2654
2655 memcpy(obuf, buf, sizeof(obuf));
2656
2657 if ((buf[0] & 0xff) == 2) {
2658 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2659 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2660 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2661 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2662 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2663 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2664 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2665 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2666 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2667 }
2668
2669 pci_dma_write(pci_dev, paddr, &obuf, 32);
2670}
2671
2672static void xhci_process_commands(XHCIState *xhci)
2673{
2674 XHCITRB trb;
2675 TRBType type;
2676 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2677 dma_addr_t addr;
2678 unsigned int i, slotid = 0;
2679
2680 DPRINTF("xhci_process_commands()\n")do {} while (0);
2681 if (!xhci_running(xhci)) {
2682 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n")do {} while (0);
2683 return;
2684 }
2685
2686 xhci->crcr_low |= CRCR_CRR(1<<3);
2687
2688 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2689 event.ptr = addr;
2690 switch (type) {
2691 case CR_ENABLE_SLOT:
2692 for (i = 0; i < xhci->numslots; i++) {
2693 if (!xhci->slots[i].enabled) {
2694 break;
2695 }
2696 }
2697 if (i >= xhci->numslots) {
2698 fprintf(stderrstderr, "xhci: no device slots available\n");
2699 event.ccode = CC_NO_SLOTS_ERROR;
2700 } else {
2701 slotid = i+1;
2702 event.ccode = xhci_enable_slot(xhci, slotid);
2703 }
2704 break;
2705 case CR_DISABLE_SLOT:
2706 slotid = xhci_get_slot(xhci, &event, &trb);
2707 if (slotid) {
2708 event.ccode = xhci_disable_slot(xhci, slotid);
2709 }
2710 break;
2711 case CR_ADDRESS_DEVICE:
2712 slotid = xhci_get_slot(xhci, &event, &trb);
2713 if (slotid) {
2714 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2715 trb.control & TRB_CR_BSR(1<<9));
2716 }
2717 break;
2718 case CR_CONFIGURE_ENDPOINT:
2719 slotid = xhci_get_slot(xhci, &event, &trb);
2720 if (slotid) {
2721 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2722 trb.control & TRB_CR_DC(1<<9));
2723 }
2724 break;
2725 case CR_EVALUATE_CONTEXT:
2726 slotid = xhci_get_slot(xhci, &event, &trb);
2727 if (slotid) {
2728 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2729 }
2730 break;
2731 case CR_STOP_ENDPOINT:
2732 slotid = xhci_get_slot(xhci, &event, &trb);
2733 if (slotid) {
2734 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT16)
2735 & TRB_CR_EPID_MASK0x1f;
2736 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2737 }
2738 break;
2739 case CR_RESET_ENDPOINT:
2740 slotid = xhci_get_slot(xhci, &event, &trb);
2741 if (slotid) {
2742 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT16)
2743 & TRB_CR_EPID_MASK0x1f;
2744 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2745 }
2746 break;
2747 case CR_SET_TR_DEQUEUE:
2748 slotid = xhci_get_slot(xhci, &event, &trb);
2749 if (slotid) {
2750 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT16)
2751 & TRB_CR_EPID_MASK0x1f;
2752 unsigned int streamid = (trb.status >> 16) & 0xffff;
2753 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2754 epid, streamid,
2755 trb.parameter);
2756 }
2757 break;
2758 case CR_RESET_DEVICE:
2759 slotid = xhci_get_slot(xhci, &event, &trb);
2760 if (slotid) {
2761 event.ccode = xhci_reset_slot(xhci, slotid);
2762 }
2763 break;
2764 case CR_GET_PORT_BANDWIDTH:
2765 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2766 break;
2767 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2768 xhci_via_challenge(xhci, trb.parameter);
2769 break;
2770 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2771 event.type = 48; /* NEC reply */
2772 event.length = 0x3025;
2773 break;
2774 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2775 {
2776 uint32_t chi = trb.parameter >> 32;
2777 uint32_t clo = trb.parameter;
2778 uint32_t val = xhci_nec_challenge(chi, clo);
2779 event.length = val & 0xFFFF;
2780 event.epid = val >> 16;
2781 slotid = val >> 24;
2782 event.type = 48; /* NEC reply */
2783 }
2784 break;
2785 default:
2786 trace_usb_xhci_unimplemented("command", type);
2787 event.ccode = CC_TRB_ERROR;
2788 break;
2789 }
2790 event.slotid = slotid;
2791 xhci_event(xhci, &event, 0);
2792 }
2793}
2794
2795static bool_Bool xhci_port_have_device(XHCIPort *port)
2796{
2797 if (!port->uport->dev || !port->uport->dev->attached) {
2798 return false0; /* no device present */
2799 }
2800 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2801 return false0; /* speed mismatch */
2802 }
2803 return true1;
2804}
2805
2806static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2807{
2808 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2809 port->portnr << 24 };
2810
2811 if ((port->portsc & bits) == bits) {
2812 return;
2813 }
2814 trace_usb_xhci_port_notify(port->portnr, bits);
2815 port->portsc |= bits;
2816 if (!xhci_running(port->xhci)) {
2817 return;
2818 }
2819 xhci_event(port->xhci, &ev, 0);
2820}
2821
2822static void xhci_port_update(XHCIPort *port, int is_detach)
2823{
2824 uint32_t pls = PLS_RX_DETECT;
2825
2826 port->portsc = PORTSC_PP(1<<9);
2827 if (!is_detach && xhci_port_have_device(port)) {
2828 port->portsc |= PORTSC_CCS(1<<0);
2829 switch (port->uport->dev->speed) {
2830 case USB_SPEED_LOW0:
2831 port->portsc |= PORTSC_SPEED_LOW(2<<10);
2832 pls = PLS_POLLING;
2833 break;
2834 case USB_SPEED_FULL1:
2835 port->portsc |= PORTSC_SPEED_FULL(1<<10);
2836 pls = PLS_POLLING;
2837 break;
2838 case USB_SPEED_HIGH2:
2839 port->portsc |= PORTSC_SPEED_HIGH(3<<10);
2840 pls = PLS_POLLING;
2841 break;
2842 case USB_SPEED_SUPER3:
2843 port->portsc |= PORTSC_SPEED_SUPER(4<<10);
2844 port->portsc |= PORTSC_PED(1<<1);
2845 pls = PLS_U0;
2846 break;
2847 }
2848 }
2849 set_field(&port->portsc, pls, PORTSC_PLS)do { uint32_t val = *&port->portsc; val &= ~( 0xf <<
5); val |= ((pls) & 0xf) << 5; *&port->portsc
= val; } while (0)
;
2850 trace_usb_xhci_port_link(port->portnr, pls);
2851 xhci_port_notify(port, PORTSC_CSC(1<<17));
2852}
2853
2854static void xhci_port_reset(XHCIPort *port, bool_Bool warm_reset)
2855{
2856 trace_usb_xhci_port_reset(port->portnr);
2857
2858 if (!xhci_port_have_device(port)) {
2859 return;
2860 }
2861
2862 usb_device_reset(port->uport->dev);
2863
2864 switch (port->uport->dev->speed) {
2865 case USB_SPEED_SUPER3:
2866 if (warm_reset) {
2867 port->portsc |= PORTSC_WRC(1<<19);
2868 }
2869 /* fall through */
2870 case USB_SPEED_LOW0:
2871 case USB_SPEED_FULL1:
2872 case USB_SPEED_HIGH2:
2873 set_field(&port->portsc, PLS_U0, PORTSC_PLS)do { uint32_t val = *&port->portsc; val &= ~( 0xf <<
5); val |= ((PLS_U0) & 0xf) << 5; *&port->portsc
= val; } while (0)
;
2874 trace_usb_xhci_port_link(port->portnr, PLS_U0);
2875 port->portsc |= PORTSC_PED(1<<1);
2876 break;
2877 }
2878
2879 port->portsc &= ~PORTSC_PR(1<<4);
2880 xhci_port_notify(port, PORTSC_PRC(1<<21));
2881}
2882
2883static void xhci_reset(DeviceState *dev)
2884{
2885 XHCIState *xhci = XHCI(dev)((XHCIState *)object_dynamic_cast_assert(((Object *)((dev))),
("nec-usb-xhci"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 2885, __func__))
;
2886 int i;
2887
2888 trace_usb_xhci_reset();
2889 if (!(xhci->usbsts & USBSTS_HCH(1<<0))) {
2890 fprintf(stderrstderr, "xhci: reset while running!\n");
2891 }
2892
2893 xhci->usbcmd = 0;
2894 xhci->usbsts = USBSTS_HCH(1<<0);
2895 xhci->dnctrl = 0;
2896 xhci->crcr_low = 0;
2897 xhci->crcr_high = 0;
2898 xhci->dcbaap_low = 0;
2899 xhci->dcbaap_high = 0;
2900 xhci->config = 0;
2901
2902 for (i = 0; i < xhci->numslots; i++) {
2903 xhci_disable_slot(xhci, i+1);
2904 }
2905
2906 for (i = 0; i < xhci->numports; i++) {
2907 xhci_port_update(xhci->ports + i, 0);
2908 }
2909
2910 for (i = 0; i < xhci->numintrs; i++) {
2911 xhci->intr[i].iman = 0;
2912 xhci->intr[i].imod = 0;
2913 xhci->intr[i].erstsz = 0;
2914 xhci->intr[i].erstba_low = 0;
2915 xhci->intr[i].erstba_high = 0;
2916 xhci->intr[i].erdp_low = 0;
2917 xhci->intr[i].erdp_high = 0;
2918 xhci->intr[i].msix_used = 0;
2919
2920 xhci->intr[i].er_ep_idx = 0;
2921 xhci->intr[i].er_pcs = 1;
2922 xhci->intr[i].er_full = 0;
2923 xhci->intr[i].ev_buffer_put = 0;
2924 xhci->intr[i].ev_buffer_get = 0;
2925 }
2926
2927 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2928 xhci_mfwrap_update(xhci);
2929}
2930
2931static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
2932{
2933 XHCIState *xhci = ptr;
2934 uint32_t ret;
2935
2936 switch (reg) {
2937 case 0x00: /* HCIVERSION, CAPLENGTH */
2938 ret = 0x01000000 | LEN_CAP0x40;
2939 break;
2940 case 0x04: /* HCSPARAMS 1 */
2941 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2942 | (xhci->numintrs<<8) | xhci->numslots;
2943 break;
2944 case 0x08: /* HCSPARAMS 2 */
2945 ret = 0x0000000f;
2946 break;
2947 case 0x0c: /* HCSPARAMS 3 */
2948 ret = 0x00000000;
2949 break;
2950 case 0x10: /* HCCPARAMS */
2951 if (sizeof(dma_addr_t) == 4) {
2952 ret = 0x00087000;
2953 } else {
2954 ret = 0x00087001;
2955 }
2956 break;
2957 case 0x14: /* DBOFF */
2958 ret = OFF_DOORBELL0x2000;
2959 break;
2960 case 0x18: /* RTSOFF */
2961 ret = OFF_RUNTIME0x1000;
2962 break;
2963
2964 /* extended capabilities */
2965 case 0x20: /* Supported Protocol:00 */
2966 ret = 0x02000402; /* USB 2.0 */
2967 break;
2968 case 0x24: /* Supported Protocol:04 */
2969 ret = 0x20425355; /* "USB " */
2970 break;
2971 case 0x28: /* Supported Protocol:08 */
2972 ret = 0x00000001 | (xhci->numports_2<<8);
2973 break;
2974 case 0x2c: /* Supported Protocol:0c */
2975 ret = 0x00000000; /* reserved */
2976 break;
2977 case 0x30: /* Supported Protocol:00 */
2978 ret = 0x03000002; /* USB 3.0 */
2979 break;
2980 case 0x34: /* Supported Protocol:04 */
2981 ret = 0x20425355; /* "USB " */
2982 break;
2983 case 0x38: /* Supported Protocol:08 */
2984 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8);
2985 break;
2986 case 0x3c: /* Supported Protocol:0c */
2987 ret = 0x00000000; /* reserved */
2988 break;
2989 default:
2990 trace_usb_xhci_unimplemented("cap read", reg);
2991 ret = 0;
2992 }
2993
2994 trace_usb_xhci_cap_read(reg, ret);
2995 return ret;
2996}
2997
2998static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
2999{
3000 XHCIPort *port = ptr;
3001 uint32_t ret;
3002
3003 switch (reg) {
3004 case 0x00: /* PORTSC */
3005 ret = port->portsc;
3006 break;
3007 case 0x04: /* PORTPMSC */
3008 case 0x08: /* PORTLI */
3009 ret = 0;
3010 break;
3011 case 0x0c: /* reserved */
3012 default:
3013 trace_usb_xhci_unimplemented("port read", reg);
3014 ret = 0;
3015 }
3016
3017 trace_usb_xhci_port_read(port->portnr, reg, ret);
3018 return ret;
3019}
3020
3021static void xhci_port_write(void *ptr, hwaddr reg,
3022 uint64_t val, unsigned size)
3023{
3024 XHCIPort *port = ptr;
3025 uint32_t portsc, notify;
3026
3027 trace_usb_xhci_port_write(port->portnr, reg, val);
3028
3029 switch (reg) {
3030 case 0x00: /* PORTSC */
3031 /* write-1-to-start bits */
3032 if (val & PORTSC_WPR(1<<31)) {
3033 xhci_port_reset(port, true1);
3034 break;
3035 }
3036 if (val & PORTSC_PR(1<<4)) {
3037 xhci_port_reset(port, false0);
3038 break;
3039 }
3040
3041 portsc = port->portsc;
3042 notify = 0;
3043 /* write-1-to-clear bits*/
3044 portsc &= ~(val & (PORTSC_CSC(1<<17)|PORTSC_PEC(1<<18)|PORTSC_WRC(1<<19)|PORTSC_OCC(1<<20)|
3045 PORTSC_PRC(1<<21)|PORTSC_PLC(1<<22)|PORTSC_CEC(1<<23)));
3046 if (val & PORTSC_LWS(1<<16)) {
3047 /* overwrite PLS only when LWS=1 */
3048 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS)(((port->portsc) >> 5) & 0xf);
3049 uint32_t new_pls = get_field(val, PORTSC_PLS)(((val) >> 5) & 0xf);
3050 switch (new_pls) {
3051 case PLS_U0:
3052 if (old_pls != PLS_U0) {
3053 set_field(&portsc, new_pls, PORTSC_PLS)do { uint32_t val = *&portsc; val &= ~( 0xf << 5
); val |= ((new_pls) & 0xf) << 5; *&portsc = val
; } while (0)
;
3054 trace_usb_xhci_port_link(port->portnr, new_pls);
3055 notify = PORTSC_PLC(1<<22);
3056 }
3057 break;
3058 case PLS_U3:
3059 if (old_pls < PLS_U3) {
3060 set_field(&portsc, new_pls, PORTSC_PLS)do { uint32_t val = *&portsc; val &= ~( 0xf << 5
); val |= ((new_pls) & 0xf) << 5; *&portsc = val
; } while (0)
;
3061 trace_usb_xhci_port_link(port->portnr, new_pls);
3062 }
3063 break;
3064 case PLS_RESUME:
3065 /* windows does this for some reason, don't spam stderr */
3066 break;
3067 default:
3068 fprintf(stderrstderr, "%s: ignore pls write (old %d, new %d)\n",
3069 __func__, old_pls, new_pls);
3070 break;
3071 }
3072 }
3073 /* read/write bits */
3074 portsc &= ~(PORTSC_PP(1<<9)|PORTSC_WCE(1<<25)|PORTSC_WDE(1<<26)|PORTSC_WOE(1<<27));
3075 portsc |= (val & (PORTSC_PP(1<<9)|PORTSC_WCE(1<<25)|PORTSC_WDE(1<<26)|PORTSC_WOE(1<<27)));
3076 port->portsc = portsc;
3077 if (notify) {
3078 xhci_port_notify(port, notify);
3079 }
3080 break;
3081 case 0x04: /* PORTPMSC */
3082 case 0x08: /* PORTLI */
3083 default:
3084 trace_usb_xhci_unimplemented("port write", reg);
3085 }
3086}
3087
3088static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
3089{
3090 XHCIState *xhci = ptr;
3091 uint32_t ret;
3092
3093 switch (reg) {
3094 case 0x00: /* USBCMD */
3095 ret = xhci->usbcmd;
3096 break;
3097 case 0x04: /* USBSTS */
3098 ret = xhci->usbsts;
3099 break;
3100 case 0x08: /* PAGESIZE */
3101 ret = 1; /* 4KiB */
3102 break;
3103 case 0x14: /* DNCTRL */
3104 ret = xhci->dnctrl;
3105 break;
3106 case 0x18: /* CRCR low */
3107 ret = xhci->crcr_low & ~0xe;
3108 break;
3109 case 0x1c: /* CRCR high */
3110 ret = xhci->crcr_high;
3111 break;
3112 case 0x30: /* DCBAAP low */
3113 ret = xhci->dcbaap_low;
3114 break;
3115 case 0x34: /* DCBAAP high */
3116 ret = xhci->dcbaap_high;
3117 break;
3118 case 0x38: /* CONFIG */
3119 ret = xhci->config;
3120 break;
3121 default:
3122 trace_usb_xhci_unimplemented("oper read", reg);
3123 ret = 0;
3124 }
3125
3126 trace_usb_xhci_oper_read(reg, ret);
3127 return ret;
3128}
3129
3130static void xhci_oper_write(void *ptr, hwaddr reg,
3131 uint64_t val, unsigned size)
3132{
3133 XHCIState *xhci = ptr;
3134 DeviceState *d = DEVICE(ptr)((DeviceState *)object_dynamic_cast_assert(((Object *)((ptr))
), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 3134, __func__))
;
3135
3136 trace_usb_xhci_oper_write(reg, val);
3137
3138 switch (reg) {
3139 case 0x00: /* USBCMD */
3140 if ((val & USBCMD_RS(1<<0)) && !(xhci->usbcmd & USBCMD_RS(1<<0))) {
3141 xhci_run(xhci);
3142 } else if (!(val & USBCMD_RS(1<<0)) && (xhci->usbcmd & USBCMD_RS(1<<0))) {
3143 xhci_stop(xhci);
3144 }
3145 if (val & USBCMD_CSS(1<<8)) {
3146 /* save state */
3147 xhci->usbsts &= ~USBSTS_SRE(1<<10);
3148 }
3149 if (val & USBCMD_CRS(1<<9)) {
3150 /* restore state */
3151 xhci->usbsts |= USBSTS_SRE(1<<10);
3152 }
3153 xhci->usbcmd = val & 0xc0f;
3154 xhci_mfwrap_update(xhci);
3155 if (val & USBCMD_HCRST(1<<1)) {
3156 xhci_reset(d);
3157 }
3158 xhci_intx_update(xhci);
3159 break;
3160
3161 case 0x04: /* USBSTS */
3162 /* these bits are write-1-to-clear */
3163 xhci->usbsts &= ~(val & (USBSTS_HSE(1<<2)|USBSTS_EINT(1<<3)|USBSTS_PCD(1<<4)|USBSTS_SRE(1<<10)));
3164 xhci_intx_update(xhci);
3165 break;
3166
3167 case 0x14: /* DNCTRL */
3168 xhci->dnctrl = val & 0xffff;
3169 break;
3170 case 0x18: /* CRCR low */
3171 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR(1<<3));
3172 break;
3173 case 0x1c: /* CRCR high */
3174 xhci->crcr_high = val;
3175 if (xhci->crcr_low & (CRCR_CA(1<<2)|CRCR_CS(1<<1)) && (xhci->crcr_low & CRCR_CRR(1<<3))) {
3176 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
3177 xhci->crcr_low &= ~CRCR_CRR(1<<3);
3178 xhci_event(xhci, &event, 0);
3179 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low)do {} while (0);
3180 } else {
3181 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
3182 xhci_ring_init(xhci, &xhci->cmd_ring, base);
3183 }
3184 xhci->crcr_low &= ~(CRCR_CA(1<<2) | CRCR_CS(1<<1));
3185 break;
3186 case 0x30: /* DCBAAP low */
3187 xhci->dcbaap_low = val & 0xffffffc0;
3188 break;
3189 case 0x34: /* DCBAAP high */
3190 xhci->dcbaap_high = val;
3191 break;
3192 case 0x38: /* CONFIG */
3193 xhci->config = val & 0xff;
3194 break;
3195 default:
3196 trace_usb_xhci_unimplemented("oper write", reg);
3197 }
3198}
3199
3200static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
3201 unsigned size)
3202{
3203 XHCIState *xhci = ptr;
3204 uint32_t ret = 0;
3205
3206 if (reg < 0x20) {
3207 switch (reg) {
3208 case 0x00: /* MFINDEX */
3209 ret = xhci_mfindex_get(xhci) & 0x3fff;
3210 break;
3211 default:
3212 trace_usb_xhci_unimplemented("runtime read", reg);
3213 break;
3214 }
3215 } else {
3216 int v = (reg - 0x20) / 0x20;
3217 XHCIInterrupter *intr = &xhci->intr[v];
3218 switch (reg & 0x1f) {
3219 case 0x00: /* IMAN */
3220 ret = intr->iman;
3221 break;
3222 case 0x04: /* IMOD */
3223 ret = intr->imod;
3224 break;
3225 case 0x08: /* ERSTSZ */
3226 ret = intr->erstsz;
3227 break;
3228 case 0x10: /* ERSTBA low */
3229 ret = intr->erstba_low;
3230 break;
3231 case 0x14: /* ERSTBA high */
3232 ret = intr->erstba_high;
3233 break;
3234 case 0x18: /* ERDP low */
3235 ret = intr->erdp_low;
3236 break;
3237 case 0x1c: /* ERDP high */
3238 ret = intr->erdp_high;
3239 break;
3240 }
3241 }
3242
3243 trace_usb_xhci_runtime_read(reg, ret);
3244 return ret;
3245}
3246
3247static void xhci_runtime_write(void *ptr, hwaddr reg,
3248 uint64_t val, unsigned size)
3249{
3250 XHCIState *xhci = ptr;
3251 int v = (reg - 0x20) / 0x20;
3252 XHCIInterrupter *intr = &xhci->intr[v];
3253 trace_usb_xhci_runtime_write(reg, val);
3254
3255 if (reg < 0x20) {
3256 trace_usb_xhci_unimplemented("runtime write", reg);
3257 return;
3258 }
3259
3260 switch (reg & 0x1f) {
3261 case 0x00: /* IMAN */
3262 if (val & IMAN_IP(1<<0)) {
3263 intr->iman &= ~IMAN_IP(1<<0);
3264 }
3265 intr->iman &= ~IMAN_IE(1<<1);
3266 intr->iman |= val & IMAN_IE(1<<1);
3267 if (v == 0) {
3268 xhci_intx_update(xhci);
3269 }
3270 xhci_msix_update(xhci, v);
3271 break;
3272 case 0x04: /* IMOD */
3273 intr->imod = val;
3274 break;
3275 case 0x08: /* ERSTSZ */
3276 intr->erstsz = val & 0xffff;
3277 break;
3278 case 0x10: /* ERSTBA low */
3279 /* XXX NEC driver bug: it doesn't align this to 64 bytes
3280 intr->erstba_low = val & 0xffffffc0; */
3281 intr->erstba_low = val & 0xfffffff0;
3282 break;
3283 case 0x14: /* ERSTBA high */
3284 intr->erstba_high = val;
3285 xhci_er_reset(xhci, v);
3286 break;
3287 case 0x18: /* ERDP low */
3288 if (val & ERDP_EHB(1<<3)) {
3289 intr->erdp_low &= ~ERDP_EHB(1<<3);
3290 }
3291 intr->erdp_low = (val & ~ERDP_EHB(1<<3)) | (intr->erdp_low & ERDP_EHB(1<<3));
3292 break;
3293 case 0x1c: /* ERDP high */
3294 intr->erdp_high = val;
3295 xhci_events_update(xhci, v);
3296 break;
3297 default:
3298 trace_usb_xhci_unimplemented("oper write", reg);
3299 }
3300}
3301
3302static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
3303 unsigned size)
3304{
3305 /* doorbells always read as 0 */
3306 trace_usb_xhci_doorbell_read(reg, 0);
3307 return 0;
3308}
3309
3310static void xhci_doorbell_write(void *ptr, hwaddr reg,
3311 uint64_t val, unsigned size)
3312{
3313 XHCIState *xhci = ptr;
3314 unsigned int epid, streamid;
3315
3316 trace_usb_xhci_doorbell_write(reg, val);
3317
3318 if (!xhci_running(xhci)) {
3319 fprintf(stderrstderr, "xhci: wrote doorbell while xHC stopped or paused\n");
3320 return;
3321 }
3322
3323 reg >>= 2;
3324
3325 if (reg == 0) {
3326 if (val == 0) {
3327 xhci_process_commands(xhci);
3328 } else {
3329 fprintf(stderrstderr, "xhci: bad doorbell 0 write: 0x%x\n",
3330 (uint32_t)val);
3331 }
3332 } else {
3333 epid = val & 0xff;
3334 streamid = (val >> 16) & 0xffff;
3335 if (reg > xhci->numslots) {
3336 fprintf(stderrstderr, "xhci: bad doorbell %d\n", (int)reg);
3337 } else if (epid > 31) {
3338 fprintf(stderrstderr, "xhci: bad doorbell %d write: 0x%x\n",
3339 (int)reg, (uint32_t)val);
3340 } else {
3341 xhci_kick_ep(xhci, reg, epid, streamid);
3342 }
3343 }
3344}
3345
3346static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3347 unsigned width)
3348{
3349 /* nothing */
3350}
3351
3352static const MemoryRegionOps xhci_cap_ops = {
3353 .read = xhci_cap_read,
3354 .write = xhci_cap_write,
3355 .valid.min_access_size = 1,
3356 .valid.max_access_size = 4,
3357 .impl.min_access_size = 4,
3358 .impl.max_access_size = 4,
3359 .endianness = DEVICE_LITTLE_ENDIAN,
3360};
3361
3362static const MemoryRegionOps xhci_oper_ops = {
3363 .read = xhci_oper_read,
3364 .write = xhci_oper_write,
3365 .valid.min_access_size = 4,
3366 .valid.max_access_size = 4,
3367 .endianness = DEVICE_LITTLE_ENDIAN,
3368};
3369
3370static const MemoryRegionOps xhci_port_ops = {
3371 .read = xhci_port_read,
3372 .write = xhci_port_write,
3373 .valid.min_access_size = 4,
3374 .valid.max_access_size = 4,
3375 .endianness = DEVICE_LITTLE_ENDIAN,
3376};
3377
3378static const MemoryRegionOps xhci_runtime_ops = {
3379 .read = xhci_runtime_read,
3380 .write = xhci_runtime_write,
3381 .valid.min_access_size = 4,
3382 .valid.max_access_size = 4,
3383 .endianness = DEVICE_LITTLE_ENDIAN,
3384};
3385
3386static const MemoryRegionOps xhci_doorbell_ops = {
3387 .read = xhci_doorbell_read,
3388 .write = xhci_doorbell_write,
3389 .valid.min_access_size = 4,
3390 .valid.max_access_size = 4,
3391 .endianness = DEVICE_LITTLE_ENDIAN,
3392};
3393
3394static void xhci_attach(USBPort *usbport)
3395{
3396 XHCIState *xhci = usbport->opaque;
3397 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3398
3399 xhci_port_update(port, 0);
3400}
3401
3402static void xhci_detach(USBPort *usbport)
3403{
3404 XHCIState *xhci = usbport->opaque;
3405 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3406
3407 xhci_detach_slot(xhci, usbport);
3408 xhci_port_update(port, 1);
3409}
3410
3411static void xhci_wakeup(USBPort *usbport)
3412{
3413 XHCIState *xhci = usbport->opaque;
3414 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3415
3416 if (get_field(port->portsc, PORTSC_PLS)(((port->portsc) >> 5) & 0xf) != PLS_U3) {
3417 return;
3418 }
3419 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS)do { uint32_t val = *&port->portsc; val &= ~( 0xf <<
5); val |= ((PLS_RESUME) & 0xf) << 5; *&port->
portsc = val; } while (0)
;
3420 xhci_port_notify(port, PORTSC_PLC(1<<22));
3421}
3422
3423static void xhci_complete(USBPort *port, USBPacket *packet)
3424{
3425 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet)({ const typeof(((XHCITransfer *) 0)->packet) *__mptr = (packet
); (XHCITransfer *) ((char *) __mptr - __builtin_offsetof(XHCITransfer
, packet));})
;
3426
3427 if (packet->status == USB_RET_REMOVE_FROM_QUEUE(-8)) {
3428 xhci_ep_nuke_one_xfer(xfer, 0);
3429 return;
3430 }
3431 xhci_complete_packet(xfer);
3432 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid);
3433}
3434
3435static void xhci_child_detach(USBPort *uport, USBDevice *child)
3436{
3437 USBBus *bus = usb_bus_from_device(child);
3438 XHCIState *xhci = container_of(bus, XHCIState, bus)({ const typeof(((XHCIState *) 0)->bus) *__mptr = (bus); (
XHCIState *) ((char *) __mptr - __builtin_offsetof(XHCIState,
bus));})
;
3439
3440 xhci_detach_slot(xhci, uport);
3441}
3442
3443static USBPortOps xhci_uport_ops = {
3444 .attach = xhci_attach,
3445 .detach = xhci_detach,
3446 .wakeup = xhci_wakeup,
3447 .complete = xhci_complete,
3448 .child_detach = xhci_child_detach,
3449};
3450
3451static int xhci_find_epid(USBEndpoint *ep)
3452{
3453 if (ep->nr == 0) {
3454 return 1;
3455 }
3456 if (ep->pid == USB_TOKEN_IN0x69) {
3457 return ep->nr * 2 + 1;
3458 } else {
3459 return ep->nr * 2;
3460 }
3461}
3462
3463static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci,
3464 unsigned int slotid, unsigned int epid)
3465{
3466 assert(slotid >= 1 && slotid <= xhci->numslots)((slotid >= 1 && slotid <= xhci->numslots) ?
(void) (0) : __assert_fail ("slotid >= 1 && slotid <= xhci->numslots"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 3466
, __PRETTY_FUNCTION__))
;
3467
3468 if (!xhci->slots[slotid - 1].uport) {
3469 return NULL((void*)0);
3470 }
3471
3472 return usb_ep_get(xhci->slots[slotid - 1].uport->dev,
3473 (epid & 1) ? USB_TOKEN_IN0x69 : USB_TOKEN_OUT0xe1, epid >> 1);
3474}
3475
3476static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3477 unsigned int stream)
3478{
3479 XHCIState *xhci = container_of(bus, XHCIState, bus)({ const typeof(((XHCIState *) 0)->bus) *__mptr = (bus); (
XHCIState *) ((char *) __mptr - __builtin_offsetof(XHCIState,
bus));})
;
3480 int slotid;
3481
3482 DPRINTF("%s\n", __func__)do {} while (0);
3483 slotid = ep->dev->addr;
3484 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
3485 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr)do {} while (0);
3486 return;
3487 }
3488 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
3489}
3490
3491static USBBusOps xhci_bus_ops = {
3492 .wakeup_endpoint = xhci_wakeup_endpoint,
3493};
3494
3495static void usb_xhci_init(XHCIState *xhci)
3496{
3497 DeviceState *dev = DEVICE(xhci)((DeviceState *)object_dynamic_cast_assert(((Object *)((xhci)
)), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 3497, __func__))
;
3498 XHCIPort *port;
3499 int i, usbports, speedmask;
3500
3501 xhci->usbsts = USBSTS_HCH(1<<0);
3502
3503 if (xhci->numports_2 > MAXPORTS_215) {
3504 xhci->numports_2 = MAXPORTS_215;
3505 }
3506 if (xhci->numports_3 > MAXPORTS_315) {
3507 xhci->numports_3 = MAXPORTS_315;
3508 }
3509 usbports = MAX(xhci->numports_2, xhci->numports_3)(((xhci->numports_2) > (xhci->numports_3)) ? (xhci->
numports_2) : (xhci->numports_3))
;
3510 xhci->numports = xhci->numports_2 + xhci->numports_3;
3511
3512 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev);
3513
3514 for (i = 0; i < usbports; i++) {
3515 speedmask = 0;
3516 if (i < xhci->numports_2) {
3517 port = &xhci->ports[i];
3518 port->portnr = i + 1;
3519 port->uport = &xhci->uports[i];
3520 port->speedmask =
3521 USB_SPEED_MASK_LOW(1 << 0) |
3522 USB_SPEED_MASK_FULL(1 << 1) |
3523 USB_SPEED_MASK_HIGH(1 << 2);
3524 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
3525 speedmask |= port->speedmask;
3526 }
3527 if (i < xhci->numports_3) {
3528 port = &xhci->ports[i + xhci->numports_2];
3529 port->portnr = i + 1 + xhci->numports_2;
3530 port->uport = &xhci->uports[i];
3531 port->speedmask = USB_SPEED_MASK_SUPER(1 << 3);
3532 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
3533 speedmask |= port->speedmask;
3534 }
3535 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
3536 &xhci_uport_ops, speedmask);
3537 }
3538}
3539
3540static int usb_xhci_initfn(struct PCIDevice *dev)
3541{
3542 int i, ret;
3543
3544 XHCIState *xhci = XHCI(dev)((XHCIState *)object_dynamic_cast_assert(((Object *)((dev))),
("nec-usb-xhci"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 3544, __func__))
;
3545
3546 dev->config[PCI_CLASS_PROG0x09] = 0x30; /* xHCI */
3547 dev->config[PCI_INTERRUPT_PIN0x3d] = 0x01; /* interrupt pin 1 */
3548 dev->config[PCI_CACHE_LINE_SIZE0x0c] = 0x10;
3549 dev->config[0x60] = 0x30; /* release number */
3550
3551 usb_xhci_init(xhci);
3552
3553 if (xhci->numintrs > MAXINTRS16) {
3554 xhci->numintrs = MAXINTRS16;
3555 }
3556 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */
3557 xhci->numintrs++;
3558 }
3559 if (xhci->numintrs < 1) {
3560 xhci->numintrs = 1;
3561 }
3562 if (xhci->numslots > MAXSLOTS64) {
3563 xhci->numslots = MAXSLOTS64;
3564 }
3565 if (xhci->numslots < 1) {
3566 xhci->numslots = 1;
3567 }
3568
3569 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
3570
3571 memory_region_init(&xhci->mem, OBJECT(xhci)((Object *)(xhci)), "xhci", LEN_REGS0x4000);
3572 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci)((Object *)(xhci)), &xhci_cap_ops, xhci,
3573 "capabilities", LEN_CAP0x40);
3574 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci)((Object *)(xhci)), &xhci_oper_ops, xhci,
3575 "operational", 0x400);
3576 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci)((Object *)(xhci)), &xhci_runtime_ops, xhci,
3577 "runtime", LEN_RUNTIME((16 + 1) * 0x20));
3578 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci)((Object *)(xhci)), &xhci_doorbell_ops, xhci,
3579 "doorbell", LEN_DOORBELL((64 + 1) * 0x20));
3580
3581 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3582 memory_region_add_subregion(&xhci->mem, OFF_OPER0x40, &xhci->mem_oper);
3583 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME0x1000, &xhci->mem_runtime);
3584 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL0x2000, &xhci->mem_doorbell);
3585
3586 for (i = 0; i < xhci->numports; i++) {
3587 XHCIPort *port = &xhci->ports[i];
3588 uint32_t offset = OFF_OPER0x40 + 0x400 + 0x10 * i;
3589 port->xhci = xhci;
3590 memory_region_init_io(&port->mem, OBJECT(xhci)((Object *)(xhci)), &xhci_port_ops, port,
3591 port->name, 0x10);
3592 memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3593 }
3594
3595 pci_register_bar(dev, 0,
3596 PCI_BASE_ADDRESS_SPACE_MEMORY0x00|PCI_BASE_ADDRESS_MEM_TYPE_640x04,
3597 &xhci->mem);
3598
3599 ret = pcie_endpoint_cap_init(dev, 0xa0);
3600 assert(ret >= 0)((ret >= 0) ? (void) (0) : __assert_fail ("ret >= 0", "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 3600, __PRETTY_FUNCTION__))
;
3601
3602 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) {
3603 msi_init(dev, 0x70, xhci->numintrs, true1, false0);
3604 }
3605 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) {
3606 msix_init(dev, xhci->numintrs,
3607 &xhci->mem, 0, OFF_MSIX_TABLE0x3000,
3608 &xhci->mem, 0, OFF_MSIX_PBA0x3800,
3609 0x90);
3610 }
3611
3612 return 0;
3613}
3614
3615static int usb_xhci_post_load(void *opaque, int version_id)
3616{
3617 XHCIState *xhci = opaque;
3618 PCIDevice *pci_dev = PCI_DEVICE(xhci)((PCIDevice *)object_dynamic_cast_assert(((Object *)((xhci)))
, ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 3618, __func__))
;
3619 XHCISlot *slot;
3620 XHCIEPContext *epctx;
3621 dma_addr_t dcbaap, pctx;
3622 uint32_t slot_ctx[4];
3623 uint32_t ep_ctx[5];
3624 int slotid, epid, state, intr;
3625
3626 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
3627
3628 for (slotid = 1; slotid <= xhci->numslots; slotid++) {
3629 slot = &xhci->slots[slotid-1];
3630 if (!slot->addressed) {
3631 continue;
3632 }
3633 slot->ctx =
3634 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
3635 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
3636 slot->uport = xhci_lookup_uport(xhci, slot_ctx);
3637 assert(slot->uport && slot->uport->dev)((slot->uport && slot->uport->dev) ? (void) (
0) : __assert_fail ("slot->uport && slot->uport->dev"
, "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c", 3637
, __PRETTY_FUNCTION__))
;
3638
3639 for (epid = 1; epid <= 32; epid++) {
3640 pctx = slot->ctx + 32 * epid;
3641 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx));
3642 state = ep_ctx[0] & EP_STATE_MASK0x7;
3643 if (state == EP_DISABLED(0<<0)) {
3644 continue;
3645 }
3646 epctx = xhci_alloc_epctx(xhci, slotid, epid);
3647 slot->eps[epid-1] = epctx;
3648 xhci_init_epctx(epctx, pctx, ep_ctx);
3649 epctx->state = state;
3650 if (state == EP_RUNNING(1<<0)) {
3651 /* kick endpoint after vmload is finished */
3652 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3653 }
3654 }
3655 }
3656
3657 for (intr = 0; intr < xhci->numintrs; intr++) {
3658 if (xhci->intr[intr].msix_used) {
3659 msix_vector_use(pci_dev, intr);
3660 } else {
3661 msix_vector_unuse(pci_dev, intr);
3662 }
3663 }
3664
3665 return 0;
3666}
3667
3668static const VMStateDescription vmstate_xhci_ring = {
3669 .name = "xhci-ring",
3670 .version_id = 1,
3671 .fields = (VMStateField[]) {
3672 VMSTATE_UINT64(dequeue, XHCIRing){ .name = ("dequeue"), .version_id = (0), .field_exists = (((
void*)0)), .size = sizeof(uint64_t), .info = &(vmstate_info_uint64
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIRing
, dequeue) + ((uint64_t*)0 - (typeof(((XHCIRing *)0)->dequeue
)*)0)), }
,
3673 VMSTATE_BOOL(ccs, XHCIRing){ .name = ("ccs"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(_Bool), .info = &(vmstate_info_bool
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIRing
, ccs) + ((_Bool*)0 - (typeof(((XHCIRing *)0)->ccs)*)0)), }
,
3674 VMSTATE_END_OF_LIST(){}
3675 }
3676};
3677
3678static const VMStateDescription vmstate_xhci_port = {
3679 .name = "xhci-port",
3680 .version_id = 1,
3681 .fields = (VMStateField[]) {
3682 VMSTATE_UINT32(portsc, XHCIPort){ .name = ("portsc"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIPort
, portsc) + ((uint32_t*)0 - (typeof(((XHCIPort *)0)->portsc
)*)0)), }
,
3683 VMSTATE_END_OF_LIST(){}
3684 }
3685};
3686
3687static const VMStateDescription vmstate_xhci_slot = {
3688 .name = "xhci-slot",
3689 .version_id = 1,
3690 .fields = (VMStateField[]) {
3691 VMSTATE_BOOL(enabled, XHCISlot){ .name = ("enabled"), .version_id = (0), .field_exists = (((
void*)0)), .size = sizeof(_Bool), .info = &(vmstate_info_bool
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCISlot
, enabled) + ((_Bool*)0 - (typeof(((XHCISlot *)0)->enabled
)*)0)), }
,
3692 VMSTATE_BOOL(addressed, XHCISlot){ .name = ("addressed"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(_Bool), .info = &(vmstate_info_bool
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCISlot
, addressed) + ((_Bool*)0 - (typeof(((XHCISlot *)0)->addressed
)*)0)), }
,
3693 VMSTATE_END_OF_LIST(){}
3694 }
3695};
3696
3697static const VMStateDescription vmstate_xhci_event = {
3698 .name = "xhci-event",
3699 .version_id = 1,
3700 .fields = (VMStateField[]) {
3701 VMSTATE_UINT32(type, XHCIEvent){ .name = ("type"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIEvent
, type) + ((uint32_t*)0 - (typeof(((XHCIEvent *)0)->type)*
)0)), }
,
3702 VMSTATE_UINT32(ccode, XHCIEvent){ .name = ("ccode"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIEvent
, ccode) + ((uint32_t*)0 - (typeof(((XHCIEvent *)0)->ccode
)*)0)), }
,
3703 VMSTATE_UINT64(ptr, XHCIEvent){ .name = ("ptr"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint64_t), .info = &(vmstate_info_uint64
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIEvent
, ptr) + ((uint64_t*)0 - (typeof(((XHCIEvent *)0)->ptr)*)0
)), }
,
3704 VMSTATE_UINT32(length, XHCIEvent){ .name = ("length"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIEvent
, length) + ((uint32_t*)0 - (typeof(((XHCIEvent *)0)->length
)*)0)), }
,
3705 VMSTATE_UINT32(flags, XHCIEvent){ .name = ("flags"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIEvent
, flags) + ((uint32_t*)0 - (typeof(((XHCIEvent *)0)->flags
)*)0)), }
,
3706 VMSTATE_UINT8(slotid, XHCIEvent){ .name = ("slotid"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint8_t), .info = &(vmstate_info_uint8
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIEvent
, slotid) + ((uint8_t*)0 - (typeof(((XHCIEvent *)0)->slotid
)*)0)), }
,
3707 VMSTATE_UINT8(epid, XHCIEvent){ .name = ("epid"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint8_t), .info = &(vmstate_info_uint8
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIEvent
, epid) + ((uint8_t*)0 - (typeof(((XHCIEvent *)0)->epid)*)
0)), }
,
3708 }
3709};
3710
3711static bool_Bool xhci_er_full(void *opaque, int version_id)
3712{
3713 struct XHCIInterrupter *intr = opaque;
3714 return intr->er_full;
3715}
3716
3717static const VMStateDescription vmstate_xhci_intr = {
3718 .name = "xhci-intr",
3719 .version_id = 1,
3720 .fields = (VMStateField[]) {
3721 /* registers */
3722 VMSTATE_UINT32(iman, XHCIInterrupter){ .name = ("iman"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, iman) + ((uint32_t*)0 - (typeof(((XHCIInterrupter *)0)->
iman)*)0)), }
,
3723 VMSTATE_UINT32(imod, XHCIInterrupter){ .name = ("imod"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, imod) + ((uint32_t*)0 - (typeof(((XHCIInterrupter *)0)->
imod)*)0)), }
,
3724 VMSTATE_UINT32(erstsz, XHCIInterrupter){ .name = ("erstsz"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, erstsz) + ((uint32_t*)0 - (typeof(((XHCIInterrupter *)0)->
erstsz)*)0)), }
,
3725 VMSTATE_UINT32(erstba_low, XHCIInterrupter){ .name = ("erstba_low"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, erstba_low) + ((uint32_t*)0 - (typeof(((XHCIInterrupter *)0
)->erstba_low)*)0)), }
,
3726 VMSTATE_UINT32(erstba_high, XHCIInterrupter){ .name = ("erstba_high"), .version_id = (0), .field_exists =
(((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, erstba_high) + ((uint32_t*)0 - (typeof(((XHCIInterrupter *)
0)->erstba_high)*)0)), }
,
3727 VMSTATE_UINT32(erdp_low, XHCIInterrupter){ .name = ("erdp_low"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, erdp_low) + ((uint32_t*)0 - (typeof(((XHCIInterrupter *)0)->
erdp_low)*)0)), }
,
3728 VMSTATE_UINT32(erdp_high, XHCIInterrupter){ .name = ("erdp_high"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, erdp_high) + ((uint32_t*)0 - (typeof(((XHCIInterrupter *)0)
->erdp_high)*)0)), }
,
3729
3730 /* state */
3731 VMSTATE_BOOL(msix_used, XHCIInterrupter){ .name = ("msix_used"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(_Bool), .info = &(vmstate_info_bool
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, msix_used) + ((_Bool*)0 - (typeof(((XHCIInterrupter *)0)->
msix_used)*)0)), }
,
3732 VMSTATE_BOOL(er_pcs, XHCIInterrupter){ .name = ("er_pcs"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(_Bool), .info = &(vmstate_info_bool
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, er_pcs) + ((_Bool*)0 - (typeof(((XHCIInterrupter *)0)->er_pcs
)*)0)), }
,
3733 VMSTATE_UINT64(er_start, XHCIInterrupter){ .name = ("er_start"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint64_t), .info = &(vmstate_info_uint64
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, er_start) + ((uint64_t*)0 - (typeof(((XHCIInterrupter *)0)->
er_start)*)0)), }
,
3734 VMSTATE_UINT32(er_size, XHCIInterrupter){ .name = ("er_size"), .version_id = (0), .field_exists = (((
void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, er_size) + ((uint32_t*)0 - (typeof(((XHCIInterrupter *)0)->
er_size)*)0)), }
,
3735 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter){ .name = ("er_ep_idx"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, er_ep_idx) + ((uint32_t*)0 - (typeof(((XHCIInterrupter *)0)
->er_ep_idx)*)0)), }
,
3736
3737 /* event queue (used if ring is full) */
3738 VMSTATE_BOOL(er_full, XHCIInterrupter){ .name = ("er_full"), .version_id = (0), .field_exists = (((
void*)0)), .size = sizeof(_Bool), .info = &(vmstate_info_bool
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, er_full) + ((_Bool*)0 - (typeof(((XHCIInterrupter *)0)->
er_full)*)0)), }
,
3739 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full){ .name = ("ev_buffer_put"), .version_id = (0), .field_exists
= (xhci_er_full), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, ev_buffer_put) + ((uint32_t*)0 - (typeof(((XHCIInterrupter *
)0)->ev_buffer_put)*)0)), }
,
3740 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full){ .name = ("ev_buffer_get"), .version_id = (0), .field_exists
= (xhci_er_full), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIInterrupter
, ev_buffer_get) + ((uint32_t*)0 - (typeof(((XHCIInterrupter *
)0)->ev_buffer_get)*)0)), }
,
3741 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE,{ .name = ("ev_buffer"), .num = ((((3*24)+16)*64)), .field_exists
= (xhci_er_full), .version_id = (1), .vmsd = &(vmstate_xhci_event
), .size = sizeof(XHCIEvent), .flags = VMS_STRUCT|VMS_ARRAY, .
offset = (__builtin_offsetof(XHCIInterrupter, ev_buffer) + ((
XHCIEvent(*)[(((3*24)+16)*64)])0 - (typeof(((XHCIInterrupter *
)0)->ev_buffer)*)0)),}
3742 xhci_er_full, 1,{ .name = ("ev_buffer"), .num = ((((3*24)+16)*64)), .field_exists
= (xhci_er_full), .version_id = (1), .vmsd = &(vmstate_xhci_event
), .size = sizeof(XHCIEvent), .flags = VMS_STRUCT|VMS_ARRAY, .
offset = (__builtin_offsetof(XHCIInterrupter, ev_buffer) + ((
XHCIEvent(*)[(((3*24)+16)*64)])0 - (typeof(((XHCIInterrupter *
)0)->ev_buffer)*)0)),}
3743 vmstate_xhci_event, XHCIEvent){ .name = ("ev_buffer"), .num = ((((3*24)+16)*64)), .field_exists
= (xhci_er_full), .version_id = (1), .vmsd = &(vmstate_xhci_event
), .size = sizeof(XHCIEvent), .flags = VMS_STRUCT|VMS_ARRAY, .
offset = (__builtin_offsetof(XHCIInterrupter, ev_buffer) + ((
XHCIEvent(*)[(((3*24)+16)*64)])0 - (typeof(((XHCIInterrupter *
)0)->ev_buffer)*)0)),}
,
3744
3745 VMSTATE_END_OF_LIST(){}
3746 }
3747};
3748
3749static const VMStateDescription vmstate_xhci = {
3750 .name = "xhci",
3751 .version_id = 1,
3752 .post_load = usb_xhci_post_load,
3753 .fields = (VMStateField[]) {
3754 VMSTATE_PCIE_DEVICE(parent_obj, XHCIState){ .name = ("parent_obj"), .size = sizeof(PCIDevice), .vmsd = &
vmstate_pcie_device, .flags = VMS_STRUCT, .offset = (__builtin_offsetof
(XHCIState, parent_obj) + ((PCIDevice*)0 - (typeof(((XHCIState
*)0)->parent_obj)*)0)), }
,
3755 VMSTATE_MSIX(parent_obj, XHCIState){ .name = ("parent_obj"), .size = sizeof(PCIDevice), .vmsd = &
vmstate_msix, .flags = VMS_STRUCT, .offset = (__builtin_offsetof
(XHCIState, parent_obj) + ((PCIDevice*)0 - (typeof(((XHCIState
*)0)->parent_obj)*)0)), }
,
3756
3757 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,{ .name = ("ports"), .num_offset = (__builtin_offsetof(XHCIState
, numports) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->numports
)*)0)), .version_id = (1), .vmsd = &(vmstate_xhci_port), .
size = sizeof(XHCIPort), .flags = VMS_STRUCT|VMS_VARRAY_UINT32
, .offset = __builtin_offsetof(XHCIState, ports), }
3758 vmstate_xhci_port, XHCIPort){ .name = ("ports"), .num_offset = (__builtin_offsetof(XHCIState
, numports) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->numports
)*)0)), .version_id = (1), .vmsd = &(vmstate_xhci_port), .
size = sizeof(XHCIPort), .flags = VMS_STRUCT|VMS_VARRAY_UINT32
, .offset = __builtin_offsetof(XHCIState, ports), }
,
3759 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,{ .name = ("slots"), .num_offset = (__builtin_offsetof(XHCIState
, numslots) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->numslots
)*)0)), .version_id = (1), .vmsd = &(vmstate_xhci_slot), .
size = sizeof(XHCISlot), .flags = VMS_STRUCT|VMS_VARRAY_UINT32
, .offset = __builtin_offsetof(XHCIState, slots), }
3760 vmstate_xhci_slot, XHCISlot){ .name = ("slots"), .num_offset = (__builtin_offsetof(XHCIState
, numslots) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->numslots
)*)0)), .version_id = (1), .vmsd = &(vmstate_xhci_slot), .
size = sizeof(XHCISlot), .flags = VMS_STRUCT|VMS_VARRAY_UINT32
, .offset = __builtin_offsetof(XHCIState, slots), }
,
3761 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1,{ .name = ("intr"), .num_offset = (__builtin_offsetof(XHCIState
, numintrs) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->numintrs
)*)0)), .version_id = (1), .vmsd = &(vmstate_xhci_intr), .
size = sizeof(XHCIInterrupter), .flags = VMS_STRUCT|VMS_VARRAY_UINT32
, .offset = __builtin_offsetof(XHCIState, intr), }
3762 vmstate_xhci_intr, XHCIInterrupter){ .name = ("intr"), .num_offset = (__builtin_offsetof(XHCIState
, numintrs) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->numintrs
)*)0)), .version_id = (1), .vmsd = &(vmstate_xhci_intr), .
size = sizeof(XHCIInterrupter), .flags = VMS_STRUCT|VMS_VARRAY_UINT32
, .offset = __builtin_offsetof(XHCIState, intr), }
,
3763
3764 /* Operational Registers */
3765 VMSTATE_UINT32(usbcmd, XHCIState){ .name = ("usbcmd"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIState
, usbcmd) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->usbcmd
)*)0)), }
,
3766 VMSTATE_UINT32(usbsts, XHCIState){ .name = ("usbsts"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIState
, usbsts) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->usbsts
)*)0)), }
,
3767 VMSTATE_UINT32(dnctrl, XHCIState){ .name = ("dnctrl"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIState
, dnctrl) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->dnctrl
)*)0)), }
,
3768 VMSTATE_UINT32(crcr_low, XHCIState){ .name = ("crcr_low"), .version_id = (0), .field_exists = ((
(void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIState
, crcr_low) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->crcr_low
)*)0)), }
,
3769 VMSTATE_UINT32(crcr_high, XHCIState){ .name = ("crcr_high"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIState
, crcr_high) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->crcr_high
)*)0)), }
,
3770 VMSTATE_UINT32(dcbaap_low, XHCIState){ .name = ("dcbaap_low"), .version_id = (0), .field_exists = (
((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIState
, dcbaap_low) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->
dcbaap_low)*)0)), }
,
3771 VMSTATE_UINT32(dcbaap_high, XHCIState){ .name = ("dcbaap_high"), .version_id = (0), .field_exists =
(((void*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIState
, dcbaap_high) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->
dcbaap_high)*)0)), }
,
3772 VMSTATE_UINT32(config, XHCIState){ .name = ("config"), .version_id = (0), .field_exists = (((void
*)0)), .size = sizeof(uint32_t), .info = &(vmstate_info_uint32
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIState
, config) + ((uint32_t*)0 - (typeof(((XHCIState *)0)->config
)*)0)), }
,
3773
3774 /* Runtime Registers & state */
3775 VMSTATE_INT64(mfindex_start, XHCIState){ .name = ("mfindex_start"), .version_id = (0), .field_exists
= (((void*)0)), .size = sizeof(int64_t), .info = &(vmstate_info_int64
), .flags = VMS_SINGLE, .offset = (__builtin_offsetof(XHCIState
, mfindex_start) + ((int64_t*)0 - (typeof(((XHCIState *)0)->
mfindex_start)*)0)), }
,
3776 VMSTATE_TIMER(mfwrap_timer, XHCIState){ .name = ("mfwrap_timer"), .version_id = (0), .info = &(
vmstate_info_timer), .size = sizeof(QEMUTimer *), .flags = VMS_SINGLE
|VMS_POINTER, .offset = (__builtin_offsetof(XHCIState, mfwrap_timer
) + ((QEMUTimer **)0 - (typeof(((XHCIState *)0)->mfwrap_timer
)*)0)), }
,
3777 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing){ .name = ("cmd_ring"), .version_id = (1), .field_exists = ((
(void*)0)), .vmsd = &(vmstate_xhci_ring), .size = sizeof(
XHCIRing), .flags = VMS_STRUCT, .offset = (__builtin_offsetof
(XHCIState, cmd_ring) + ((XHCIRing*)0 - (typeof(((XHCIState *
)0)->cmd_ring)*)0)), }
,
3778
3779 VMSTATE_END_OF_LIST(){}
3780 }
3781};
3782
3783static Property xhci_properties[] = {
3784 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true){ .name = ("msi"), .info = &(qdev_prop_bit), .bitnr = (XHCI_FLAG_USE_MSI
), .offset = __builtin_offsetof(XHCIState, flags) + ((uint32_t
*)0 - (typeof(((XHCIState *)0)->flags)*)0), .qtype = QTYPE_QBOOL
, .defval = (_Bool)1, }
,
3785 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true){ .name = ("msix"), .info = &(qdev_prop_bit), .bitnr = (XHCI_FLAG_USE_MSI_X
), .offset = __builtin_offsetof(XHCIState, flags) + ((uint32_t
*)0 - (typeof(((XHCIState *)0)->flags)*)0), .qtype = QTYPE_QBOOL
, .defval = (_Bool)1, }
,
3786 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS){ .name = ("intrs"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(XHCIState, numintrs) + ((uint32_t*)0 - (
typeof(((XHCIState *)0)->numintrs)*)0), .qtype = QTYPE_QINT
, .defval = (uint32_t)16, }
,
3787 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS){ .name = ("slots"), .info = &(qdev_prop_uint32), .offset
= __builtin_offsetof(XHCIState, numslots) + ((uint32_t*)0 - (
typeof(((XHCIState *)0)->numslots)*)0), .qtype = QTYPE_QINT
, .defval = (uint32_t)64, }
,
3788 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4){ .name = ("p2"), .info = &(qdev_prop_uint32), .offset = __builtin_offsetof
(XHCIState, numports_2) + ((uint32_t*)0 - (typeof(((XHCIState
*)0)->numports_2)*)0), .qtype = QTYPE_QINT, .defval = (uint32_t
)4, }
,
3789 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4){ .name = ("p3"), .info = &(qdev_prop_uint32), .offset = __builtin_offsetof
(XHCIState, numports_3) + ((uint32_t*)0 - (typeof(((XHCIState
*)0)->numports_3)*)0), .qtype = QTYPE_QINT, .defval = (uint32_t
)4, }
,
3790 DEFINE_PROP_END_OF_LIST(){},
3791};
3792
3793static void xhci_class_init(ObjectClass *klass, void *data)
3794{
3795 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass)((PCIDeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("pci-device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 3795, __func__))
;
3796 DeviceClass *dc = DEVICE_CLASS(klass)((DeviceClass *)object_class_dynamic_cast_assert(((ObjectClass
*)((klass))), ("device"), "/home/stefan/src/qemu/qemu.org/qemu/hw/usb/hcd-xhci.c"
, 3796, __func__))
;
3797
3798 dc->vmsd = &vmstate_xhci;
3799 dc->props = xhci_properties;
3800 dc->reset = xhci_reset;
3801 set_bit(DEVICE_CATEGORY_USB, dc->categories);
3802 k->init = usb_xhci_initfn;
3803 k->vendor_id = PCI_VENDOR_ID_NEC0x1033;
3804 k->device_id = PCI_DEVICE_ID_NEC_UPD7202000x0194;
3805 k->class_id = PCI_CLASS_SERIAL_USB0x0c03;
3806 k->revision = 0x03;
3807 k->is_express = 1;
3808 k->no_hotplug = 1;
3809}
3810
3811static const TypeInfo xhci_info = {
3812 .name = TYPE_XHCI"nec-usb-xhci",
3813 .parent = TYPE_PCI_DEVICE"pci-device",
3814 .instance_size = sizeof(XHCIState),
3815 .class_init = xhci_class_init,
3816};
3817
3818static void xhci_register_types(void)
3819{
3820 type_register_static(&xhci_info);
3821}
3822
3823type_init(xhci_register_types)static void __attribute__((constructor)) do_qemu_init_xhci_register_types
(void) { register_module_init(xhci_register_types, MODULE_INIT_QOM
); }